1//Original:/proj/frio/dv/testcases/core/c_seq_ac_raise_mv/c_seq_ac_raise_mv.dsp
2// Spec Reference: sequencer stage AC  (raise + regmv)
3# mach: bfin
4# sim: --environment operating
5
6#include "test.h"
7.include "testutils.inc"
8start
9
10include(std.inc)
11include(selfcheck.inc)
12include(gen_int.inc)
13INIT_R_REGS(0);
14INIT_P_REGS(0);
15INIT_I_REGS(0);     // initialize the dsp address regs
16INIT_M_REGS(0);
17INIT_L_REGS(0);
18INIT_B_REGS(0);
19//CHECK_INIT(p5, 0xe0000000);
20include(symtable.inc)
21CHECK_INIT_DEF(p5);
22
23#ifndef STACKSIZE
24#define STACKSIZE 0x10
25#endif
26#ifndef EVT
27#define EVT  0xFFE02000
28#endif
29#ifndef EVT15
30#define EVT15  0xFFE0203C
31#endif
32#ifndef EVT_OVERRIDE
33#define EVT_OVERRIDE 0xFFE02100
34#endif
35#ifndef ITABLE
36#define ITABLE DATA_ADDR_1
37#endif
38
39GEN_INT_INIT(ITABLE) // set location for interrupt table
40
41//
42// Reset/Bootstrap Code
43//   (Here we should set the processor operating modes, initialize registers,
44//
45
46BOOT:
47
48                              // in reset mode now
49LD32_LABEL(sp, KSTACK);   // setup the stack pointer
50FP = SP;        // and frame pointer
51
52LD32(p0, EVT);      // Setup Event Vectors and Handlers
53LD32_LABEL(r0, EHANDLE);  // Emulation Handler (Int0)
54    [ P0 ++ ] = R0;
55
56LD32_LABEL(r0, RHANDLE);  // Reset Handler (Int1)
57    [ P0 ++ ] = R0;
58
59LD32_LABEL(r0, NHANDLE);  // NMI Handler (Int2)
60    [ P0 ++ ] = R0;
61
62LD32_LABEL(r0, XHANDLE);  // Exception Handler (Int3)
63    [ P0 ++ ] = R0;
64
65    [ P0 ++ ] = R0;        // IVT4 not used
66
67LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
68    [ P0 ++ ] = R0;
69
70LD32_LABEL(r0, THANDLE);  // Timer Handler (Int6)
71    [ P0 ++ ] = R0;
72
73LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
74    [ P0 ++ ] = R0;
75
76LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
77    [ P0 ++ ] = R0;
78
79LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
80    [ P0 ++ ] = R0;
81
82LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
83    [ P0 ++ ] = R0;
84
85LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
86    [ P0 ++ ] = R0;
87
88LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
89    [ P0 ++ ] = R0;
90
91LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
92    [ P0 ++ ] = R0;
93
94LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
95    [ P0 ++ ] = R0;
96
97LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
98    [ P0 ++ ] = R0;
99
100LD32(p0, EVT_OVERRIDE);
101    R0 = 0;
102    [ P0 ++ ] = R0;
103    R0 = -1;     // Change this to mask interrupts (*)
104    [ P0 ] = R0;   // IMASK
105CSYNC;
106
107DUMMY:
108
109    R0 = 0 (Z);
110
111LT0 = r0;       // set loop counters to something deterministic
112LB0 = r0;
113LC0 = r0;
114LT1 = r0;
115LB1 = r0;
116LC1 = r0;
117
118ASTAT = r0;     // reset other internal regs
119
120// The following code sets up the test for running in USER mode
121
122LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
123                        // ReturnFromInterrupt (RTI)
124RETI = r0;      // We need to load the return address
125
126// Comment the following line for a USER Mode test
127
128JUMP    STARTSUP;   // jump to code start for SUPERVISOR mode
129
130RTI;
131
132STARTSUP:
133LD32_LABEL(p1, BEGIN);
134
135LD32(p0, EVT15);
136    [ P0 ] = P1;   // IVG15 (General) handler (Int 15) load with start
137
138RAISE 15;   // after we RTI, INT 15 should be taken,& return to BEGIN in
139                // SUPERVISOR MODE & go to different RAISE in supervisor mode
140                // until the end of the test.
141
142NOP;    // Workaround for Bug 217
143RTI;
144
145//
146// The Main Program
147//
148STARTUSER:
149LD32_LABEL(sp, USTACK);   // setup the stack pointer
150FP = SP;            // set frame pointer
151JUMP BEGIN;
152
153//*********************************************************************
154
155BEGIN:
156
157                // COMMENT the following line for USER MODE tests
158    [ -- SP ] = RETI;  // enable interrupts in supervisor mode
159
160                // **** YOUR CODE GOES HERE ****
161
162
163
164    // PUT YOUR TEST HERE!
165// PUSH
166        R0 = 0xa01 (X);
167        R1 = 0xb02 (X);
168        R2 = 0xc03 (X);
169        R3 = 0xd04 (X);
170        R4 = 0xe05 (X);
171        R5 = 0xf06 (X);
172        R6 = 0x107 (X);
173        R7 = 0x208 (X);
174LD32(p1, 0x12345678);
175LD32(p2, 0x05612496);
176LD32(p3, 0xab5fd490);
177LD32(p4, 0xa581bd94);
178
179
180RAISE 2;    // RTN
181    P1 = R7;
182    R0 = P1;
183//      [--sp] = (r7-r0);
184
185RAISE 5;    // RTI
186    P2 = R6;
187    R1 = P2;
188
189//      [--sp] = (r7-r1);
190
191
192RAISE 6;    // RTI
193    P3 = R5;
194    R2 = P3;
195        [ -- SP ] = ( R7:2 );
196// POP
197
198RAISE 7;    // RTI
199    P4 = R4;
200    R3 = P4;
201//      (r7-r2) = [sp++];
202
203
204
205CHECKREG(r0, 0x00000208);
206CHECKREG(r1, 0x00000107);
207CHECKREG(r2, 0x00000F06);
208CHECKREG(r3, 0x00000E05);
209CHECKREG(r4, 0x00000E05);
210CHECKREG(r5, 0x00000F06);
211CHECKREG(r6, 0x00000107);
212CHECKREG(r7, 0x00000208);
213
214        R0 = 0xa41 (X);
215        R1 = 0xb52 (X);
216        R2 = 0xc63 (X);
217        R3 = 0xd74 (X);
218        R4 = 0xe85 (X);
219        R5 = 0xf96 (X);
220        R6 = 0x1a7 (X);
221        R7 = 0x2b8 (X);
222RAISE 8;    // RTI
223    P1 = R0;
224    R6 = P1;
225//      (r7-r1) = [sp++];
226CHECKREG(r0, 0x00000A41);
227CHECKREG(r1, 0x00000B52);
228CHECKREG(r2, 0x00000C63);
229CHECKREG(r3, 0x00000D74);
230CHECKREG(r4, 0x00000E85);
231CHECKREG(r5, 0x00000F96);
232CHECKREG(r6, 0x00000A41);
233CHECKREG(r7, 0x000002B8);
234
235RAISE 9;    // RTI
236    P2 = R1;
237    R7 = P2;
238//      (r7-r0) = [sp++];
239
240R0 = I0;
241R1 = I1;
242R2 = I2;
243R3 = I3;
244CHECKREG(r0, 0x00000006);
245CHECKREG(r1, 0x00000002);
246CHECKREG(r2, 0x00000002);
247CHECKREG(r3, 0x00000002);
248CHECKREG(r4, 0x00000E85);
249CHECKREG(r5, 0x00000F96);
250CHECKREG(r6, 0x00000A41);
251CHECKREG(r7, 0x00000B52);
252
253
254END:
255dbg_pass;            // End the test
256
257//*********************************************************************
258
259//
260// Handlers for Events
261//
262
263EHANDLE:            // Emulation Handler 0
264RTE;
265
266RHANDLE:            // Reset Handler 1
267RTI;
268
269NHANDLE:            // NMI Handler 2
270    I0 += 2;
271RTN;
272
273XHANDLE:            // Exception Handler 3
274    R1 = 3;
275RTX;
276
277HWHANDLE:           // HW Error Handler 5
278    I0 += 2;
279RTI;
280
281THANDLE:            // Timer Handler 6
282    I1 += 2;
283RTI;
284
285I7HANDLE:           // IVG 7 Handler
286    I2 += 2;
287RTI;
288
289I8HANDLE:           // IVG 8 Handler
290    I3 += 2;
291RTI;
292
293I9HANDLE:           // IVG 9 Handler
294    I0 += 2;
295RTI;
296
297I10HANDLE:          // IVG 10 Handler
298    R7 = 10;
299RTI;
300
301I11HANDLE:          // IVG 11 Handler
302    I0 = R0;
303    I1 = R1;
304    I2 = R2;
305    I3 = R3;
306    M0 = R4;
307    R0 = 11;
308RTI;
309
310I12HANDLE:          // IVG 12 Handler
311    R1 = 12;
312RTI;
313
314I13HANDLE:          // IVG 13 Handler
315    R2 = 13;
316RTI;
317
318I14HANDLE:          // IVG 14 Handler
319    R3 = 14;
320RTI;
321
322I15HANDLE:          // IVG 15 Handler
323    R4 = 15;
324RTI;
325
326NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
327
328//
329// Data Segment
330//
331
332.data
333DATA:
334    .space (0x10);
335
336// Stack Segments (Both Kernel and User)
337
338    .space (STACKSIZE);
339KSTACK:
340
341    .space (STACKSIZE);
342USTACK:
343