1# Blackfin testcase for having RETI set correctly
2# mach: bfin
3# sim: --environment operating
4
5#include "test.h"
6	.include "testutils.inc"
7
8	# This test keeps P5 as the base of the EVT table
9
10	.macro set_evt lvl:req, sym:req
11	loadsym R1, \sym;
12	[P5 + 4 * \lvl\()] = R1;
13	.endm
14
15	start
16
17	# First mark all EVTs as fails (they shouldn't be activated)
18	imm32 P5, EVT0;
19	P1 = P5;
20	loadsym R1, fail_lvl
21	imm32 P2, 16
22	LSETUP (1f, 1f) LC0 = P2;
231:	[P1++] = R1;
24
25	# We'll bounce up a few
26	set_evt 6, evt6;
27	set_evt 7, evt7;
28	set_evt 8, evt8;
29	set_evt 9, evt9;
30
31	# Lower ourselves down so we can RAISE up
32	set_evt 14, evt14;
33	loadsym R1, wait;
34	RETI = R1;
35	RAISE 14;
36	R7 = -1;
37	sti R7;
38	RTI;
39
40wait:
41	jump wait;
42
43evt14:
44	# Activate interrupt nesting early
45	[--SP] = RETI;
46
47	# We activate the interrupt here ...
48	loadsym R1, 1f;
49	RAISE 9;
50	# ... but we should RETI here
511:	JUMP fail_lvl;
52
53evt9:
54	R2 = RETI;
55	CC = R1 == R2;
56	IF !CC JUMP fail_lvl;
57
58	# We activate the interrupt here ...
59	loadsym R1, 1f;
60	RAISE 8;
61	[--SP] = RETI;
62	# ... but we should RETI here
631:	JUMP fail_lvl;
64
65evt8:
66	R2 = RETI;
67	CC = R1 == R2;
68	IF !CC JUMP fail_lvl;
69
70	# Activate interrupt nesting early
71	[--SP] = RETI;
72
73	# We activate the interrupt here ...
74	loadsym R1, 1f;
75	cli R7;
76	RAISE 7;
77	sti R7;
78	# ... but we should RETI here
791:	JUMP fail_lvl;
80
81evt7:
82	R2 = RETI;
83	CC = R1 == R2;
84	IF !CC JUMP fail_lvl;
85
86	# Activate interrupt nesting early
87	[--SP] = RETI;
88
89	# We activate the interrupt here ...
90	imm32 P0, IMASK
91	R7 = [P0];
92	R6 = 0;
93	[P0] = R6;
94	loadsym R1, 1f;
95	RAISE 6;
96	[P0] = R7;
97	# ... but we should RETI here
98	# don't jump to fail_lvl as the pipeline might advance
99	# the PC to the fail_lvl point before the ivg actually
100	# gets a chance to fire
1011:	JUMP 1b;
102
103evt6:
104	R2 = RETI;
105	CC = R1 == R2;
106	IF !CC JUMP fail_lvl;
107
108	dbg_pass
109
110fail_lvl:
111	dbg_fail;
112