1.text
2	#tdpbf16ps %tmm5,%tmm4,%tmm3 set VEX.W = 1 (illegal value).
3	.byte 0xc4
4	.byte 0xe2
5	.byte 0xd2
6	.byte 0x5c
7	.byte 0xdc
8	.fill 0x05, 0x01, 0x90
9	#tdpbf16ps %tmm5,%tmm4,%tmm3 set VEX.L = 1 (illegal value).
10	.byte 0xc4
11	.byte 0xe2
12	.byte 0x56
13	.byte 0x5c
14	.byte 0xdc
15	.fill 0x05, 0x01, 0x90
16	#tdpbf16ps %tmm5,%tmm4,%tmm3 set VEX.R = 0 (illegal value).
17	.byte 0xc4
18	.byte 0x62
19	.byte 0x52
20	.byte 0x5c
21	.byte 0xdc
22	#tdpbf16ps %tmm5,%tmm4,%tmm3 set VEX.B = 0 (illegal value).
23	.byte 0xc4
24	.byte 0xc2
25	.byte 0x52
26	.byte 0x5c
27	.byte 0xdc
28	#tdpbf16ps %tmm5,%tmm4,%tmm3 set VEX.VVVV = 0110 (illegal value).
29	.byte 0xc4
30	.byte 0xe2
31	.byte 0x32
32	.byte 0x5c
33	.byte 0xdc
34	#tileloadd (%rax),%tmm1 set R/M= 001 (illegal value) without SIB.
35	.byte 0xc4
36	.byte 0xe2
37	.byte 0x7b
38	.byte 0x4b
39	.byte 0x09
40	#tdpbuud %tmm1,%tmm1,%tmm1 All 3 TMM registers can't be identical.
41	.byte 0xc4
42	.byte 0xe2
43	.byte 0x70
44	.byte 0x5e
45	.byte 0xc9
46	#tdpbuud %tmm0,%tmm1,%tmm1 All 3 TMM registers can't be identical.
47	.byte 0xc4
48	.byte 0xe2
49	.byte 0x78
50	.byte 0x5e
51	.byte 0xc9
52	#tdpbuud %tmm1,%tmm0,%tmm1 All 3 TMM registers can't be identical.
53	.byte 0xc4
54	.byte 0xe2
55	.byte 0x70
56	.byte 0x5e
57	.byte 0xc8
58	#tdpbuud %tmm1,%tmm1,%tmm0 All 3 TMM registers can't be identical.
59	.byte 0xc4
60	.byte 0xe2
61	.byte 0x70
62	.byte 0x5e
63	.byte 0xc1
64