1 #objdump: -dw 2 #name: x86-64 AVX VNNI insns 3 4 .*: +file format .* 5 6 7 Disassembly of section .text: 8 9 0+ <_start>: 10 +[a-f0-9]+: 62 d2 5d 08 50 d4 vpdpbusd %xmm12,%xmm4,%xmm2 11 +[a-f0-9]+: 62 d2 5d 08 50 d4 vpdpbusd %xmm12,%xmm4,%xmm2 12 +[a-f0-9]+: c4 c2 59 50 d4 \{vex\} vpdpbusd %xmm12,%xmm4,%xmm2 13 +[a-f0-9]+: c4 c2 59 50 d4 \{vex\} vpdpbusd %xmm12,%xmm4,%xmm2 14 +[a-f0-9]+: c4 e2 59 50 11 \{vex\} vpdpbusd \(%rcx\),%xmm4,%xmm2 15 +[a-f0-9]+: c4 e2 59 50 11 \{vex\} vpdpbusd \(%rcx\),%xmm4,%xmm2 16 +[a-f0-9]+: 62 b2 5d 08 50 d6 vpdpbusd %xmm22,%xmm4,%xmm2 17 +[a-f0-9]+: 62 d2 5d 08 52 d4 vpdpwssd %xmm12,%xmm4,%xmm2 18 +[a-f0-9]+: 62 d2 5d 08 52 d4 vpdpwssd %xmm12,%xmm4,%xmm2 19 +[a-f0-9]+: c4 c2 59 52 d4 \{vex\} vpdpwssd %xmm12,%xmm4,%xmm2 20 +[a-f0-9]+: c4 c2 59 52 d4 \{vex\} vpdpwssd %xmm12,%xmm4,%xmm2 21 +[a-f0-9]+: c4 e2 59 52 11 \{vex\} vpdpwssd \(%rcx\),%xmm4,%xmm2 22 +[a-f0-9]+: c4 e2 59 52 11 \{vex\} vpdpwssd \(%rcx\),%xmm4,%xmm2 23 +[a-f0-9]+: 62 b2 5d 08 52 d6 vpdpwssd %xmm22,%xmm4,%xmm2 24 +[a-f0-9]+: 62 d2 5d 08 51 d4 vpdpbusds %xmm12,%xmm4,%xmm2 25 +[a-f0-9]+: 62 d2 5d 08 51 d4 vpdpbusds %xmm12,%xmm4,%xmm2 26 +[a-f0-9]+: c4 c2 59 51 d4 \{vex\} vpdpbusds %xmm12,%xmm4,%xmm2 27 +[a-f0-9]+: c4 c2 59 51 d4 \{vex\} vpdpbusds %xmm12,%xmm4,%xmm2 28 +[a-f0-9]+: c4 e2 59 51 11 \{vex\} vpdpbusds \(%rcx\),%xmm4,%xmm2 29 +[a-f0-9]+: c4 e2 59 51 11 \{vex\} vpdpbusds \(%rcx\),%xmm4,%xmm2 30 +[a-f0-9]+: 62 b2 5d 08 51 d6 vpdpbusds %xmm22,%xmm4,%xmm2 31 +[a-f0-9]+: 62 d2 5d 08 53 d4 vpdpwssds %xmm12,%xmm4,%xmm2 32 +[a-f0-9]+: 62 d2 5d 08 53 d4 vpdpwssds %xmm12,%xmm4,%xmm2 33 +[a-f0-9]+: c4 c2 59 53 d4 \{vex\} vpdpwssds %xmm12,%xmm4,%xmm2 34 +[a-f0-9]+: c4 c2 59 53 d4 \{vex\} vpdpwssds %xmm12,%xmm4,%xmm2 35 +[a-f0-9]+: c4 e2 59 53 11 \{vex\} vpdpwssds \(%rcx\),%xmm4,%xmm2 36 +[a-f0-9]+: c4 e2 59 53 11 \{vex\} vpdpwssds \(%rcx\),%xmm4,%xmm2 37 +[a-f0-9]+: 62 b2 5d 08 53 d6 vpdpwssds %xmm22,%xmm4,%xmm2 38 +[a-f0-9]+: 62 d2 5d 08 50 d4 vpdpbusd %xmm12,%xmm4,%xmm2 39 #pass 40