1# Check 64bit AVX512{BF16,VL} instructions
2
3	.allow_index_reg
4	.text
5_start:
6	vcvtne2ps2bf16	%ymm28, %ymm29, %ymm30	 #AVX512{BF16,VL}
7	vcvtne2ps2bf16	%xmm28, %xmm29, %xmm30	 #AVX512{BF16,VL}
8	vcvtne2ps2bf16	0x10000000(%rbp, %r14, 8), %ymm29, %ymm30{%k7}	 #AVX512{BF16,VL} MASK_ENABLING
9	vcvtne2ps2bf16	(%r9){1to8}, %ymm29, %ymm30	 #AVX512{BF16,VL} BROADCAST_EN
10	vcvtne2ps2bf16	4064(%rcx), %ymm29, %ymm30	 #AVX512{BF16,VL} Disp8
11	vcvtne2ps2bf16	-4096(%rdx){1to8}, %ymm29, %ymm30{%k7}{z}	 #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
12	vcvtne2ps2bf16	0x10000000(%rbp, %r14, 8), %xmm29, %xmm30{%k7}	 #AVX512{BF16,VL} MASK_ENABLING
13	vcvtne2ps2bf16	(%r9){1to4}, %xmm29, %xmm30	 #AVX512{BF16,VL} BROADCAST_EN
14	vcvtne2ps2bf16	2032(%rcx), %xmm29, %xmm30	 #AVX512{BF16,VL} Disp8
15	vcvtne2ps2bf16	-2048(%rdx){1to4}, %xmm29, %xmm28{%k7}{z}	 #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
16	vcvtneps2bf16	%xmm29, %xmm30	 #AVX512{BF16,VL}
17	vcvtneps2bf16	%ymm29, %xmm30	 #AVX512{BF16,VL}
18	vcvtneps2bf16x	0x10000000(%rbp, %r14, 8), %xmm30{%k7}	 #AVX512{BF16,VL} MASK_ENABLING
19	vcvtneps2bf16	(%r9){1to4}, %xmm21	 #AVX512{BF16,VL} BROADCAST_EN
20	vcvtneps2bf16x	(%rcx){1to4}, %xmm1	 #AVX512{BF16,VL} BROADCAST_EN
21	vcvtneps2bf16x	2032(%rcx), %xmm30	 #AVX512{BF16,VL} Disp8
22	vcvtneps2bf16	-2048(%rdx){1to4}, %xmm29{%k7}{z}	 #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
23	vcvtneps2bf16	(%r9){1to8}, %xmm22	 #AVX512{BF16,VL} BROADCAST_EN
24	vcvtneps2bf16y	(%rcx){1to8}, %xmm2	 #AVX512{BF16,VL} BROADCAST_EN
25	vcvtneps2bf16y	4064(%rcx), %xmm23	 #AVX512{BF16,VL} Disp8
26	vcvtneps2bf16	-4096(%rdx){1to8}, %xmm27{%k7}{z}	 #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
27	vdpbf16ps	%ymm28, %ymm29, %ymm30	 #AVX512{BF16,VL}
28	vdpbf16ps	%xmm28, %xmm29, %xmm30	 #AVX512{BF16,VL}
29	vdpbf16ps	0x10000000(%rbp, %r14, 8), %ymm29, %ymm30{%k7}	 #AVX512{BF16,VL} MASK_ENABLING
30	vdpbf16ps	(%r9){1to8}, %ymm29, %ymm30	 #AVX512{BF16,VL} BROADCAST_EN
31	vdpbf16ps	4064(%rcx), %ymm29, %ymm30	 #AVX512{BF16,VL} Disp8
32	vdpbf16ps	-4096(%rdx){1to8}, %ymm29, %ymm30{%k7}{z}	 #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
33	vdpbf16ps	0x10000000(%rbp, %r14, 8), %xmm29, %xmm30{%k7}	 #AVX512{BF16,VL} MASK_ENABLING
34	vdpbf16ps	(%r9){1to4}, %xmm29, %xmm30	 #AVX512{BF16,VL} BROADCAST_EN
35	vdpbf16ps	2032(%rcx), %xmm29, %xmm30	 #AVX512{BF16,VL} Disp8
36	vdpbf16ps	-2048(%rdx){1to4}, %xmm29, %xmm30{%k7}{z}	 #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
37
38.intel_syntax noprefix
39	vcvtne2ps2bf16	ymm30, ymm29, ymm28	 #AVX512{BF16,VL}
40	vcvtne2ps2bf16	xmm30, xmm29, xmm28	 #AVX512{BF16,VL}
41	vcvtne2ps2bf16	ymm30{k7}, ymm29, YMMWORD PTR [rbp+r14*8+0x10000000]	 #AVX512{BF16,VL} MASK_ENABLING
42	vcvtne2ps2bf16	ymm30, ymm29, DWORD PTR [r9]{1to8}	 #AVX512{BF16,VL} BROADCAST_EN
43	vcvtne2ps2bf16	ymm30, ymm29, YMMWORD PTR [rcx+4064]	 #AVX512{BF16,VL} Disp8
44	vcvtne2ps2bf16	ymm30{k7}{z}, ymm29, DWORD PTR [rdx-4096]{1to8}	 #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
45	vcvtne2ps2bf16	xmm30{k7}, xmm29, XMMWORD PTR [rbp+r14*8+0x10000000]	 #AVX512{BF16,VL} MASK_ENABLING
46	vcvtne2ps2bf16	xmm30, xmm29, DWORD PTR [r9]{1to4}	 #AVX512{BF16,VL} BROADCAST_EN
47	vcvtne2ps2bf16	xmm30, xmm29, XMMWORD PTR [rcx+2032]	 #AVX512{BF16,VL} Disp8
48	vcvtne2ps2bf16	xmm30{k7}{z}, xmm29, DWORD PTR [rdx-2048]{1to4}	 #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
49	vcvtneps2bf16	xmm30, xmm29	 #AVX512{BF16,VL}
50	vcvtneps2bf16	xmm30, ymm29	 #AVX512{BF16,VL}
51	vcvtneps2bf16	xmm30{k7}, XMMWORD PTR [rbp+r14*8+0x10000000]	 #AVX512{BF16,VL} MASK_ENABLING
52	vcvtneps2bf16	xmm5, [rcx]{1to4}	 #AVX512{BF16,VL} BROADCAST_EN
53	vcvtneps2bf16	xmm25, DWORD PTR [r9]{1to4}	 #AVX512{BF16,VL} BROADCAST_EN
54	vcvtneps2bf16	xmm30, XMMWORD PTR [rcx+2032]	 #AVX512{BF16,VL} Disp8
55	vcvtneps2bf16	xmm30{k7}{z}, DWORD PTR [rdx-2048]{1to4}	 #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
56	vcvtneps2bf16	xmm4, [rcx]{1to8}	 #AVX512{BF16,VL} BROADCAST_EN
57	vcvtneps2bf16	xmm24, DWORD PTR [r9]{1to8}	 #AVX512{BF16,VL} BROADCAST_EN
58	vcvtneps2bf16	xmm30, YMMWORD PTR [rcx+4064]	 #AVX512{BF16,VL} Disp8
59	vcvtneps2bf16	xmm30{k7}{z}, DWORD PTR [rdx-4096]{1to8}	 #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
60	vdpbf16ps	ymm30, ymm29, ymm28	 #AVX512{BF16,VL}
61	vdpbf16ps	xmm30, xmm29, xmm28	 #AVX512{BF16,VL}
62	vdpbf16ps	ymm30{k7}, ymm29, YMMWORD PTR [rbp+r14*8+0x10000000]	 #AVX512{BF16,VL} MASK_ENABLING
63	vdpbf16ps	ymm30, ymm29, DWORD PTR [r9]{1to8}	 #AVX512{BF16,VL} BROADCAST_EN
64	vdpbf16ps	ymm30, ymm29, YMMWORD PTR [rcx+4064]	 #AVX512{BF16,VL} Disp8
65	vdpbf16ps	ymm30{k7}{z}, ymm29, DWORD PTR [rdx-4096]{1to8}	 #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
66	vdpbf16ps	xmm30{k7}, xmm29, XMMWORD PTR [rbp+r14*8+0x10000000]	 #AVX512{BF16,VL} MASK_ENABLING
67	vdpbf16ps	xmm30, xmm29, DWORD PTR [r9]{1to4}	 #AVX512{BF16,VL} BROADCAST_EN
68	vdpbf16ps	xmm30, xmm29, XMMWORD PTR [rcx+2032]	 #AVX512{BF16,VL} Disp8
69	vdpbf16ps	xmm30{k7}{z}, xmm29, DWORD PTR [rdx-2048]{1to4}	 #AVX512{BF16,VL} Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
70