1 /*========================== begin_copyright_notice ============================ 2 3 Copyright (C) 2017-2021 Intel Corporation 4 5 SPDX-License-Identifier: MIT 6 7 ============================= end_copyright_notice ===========================*/ 8 9 #if !defined(__IGFXHWEUISAICL_H__) 10 #define __IGFXHWEUISAICL_H__ 11 12 namespace G11HDL 13 { 14 typedef enum tagDSTTYPE { 15 DSTTYPE_UD = 0x0, // Unsigned Doubleword integer 16 DSTTYPE_D = 0x1, // signed Doubleword integer 17 DSTTYPE_UW = 0x2, // Unsigned Word integer 18 DSTTYPE_W = 0x3, // signed Word integer 19 DSTTYPE_UB = 0x4, // Unsigned Byte integer 20 DSTTYPE_B = 0x5, // signed Byte integer 21 DSTTYPE_UQ = 0x6, // Unsigned Quadword integer 22 DSTTYPE_Q = 0x7, // signed Quadword integer 23 DSTTYPE_HF = 0x8, // Half Float (16-bit) 24 DSTTYPE_F = 0x9, // single precision Float (32-bit) 25 DSTTYPE_DF = 0xA, // Double precision Float (64-bit) 26 } DSTTYPE; 27 28 typedef enum tagSRCTYPE { 29 SRCTYPE_UD = 0x0, // Unsigned Doubleword 30 SRCTYPE_D = 0x1, // signed Doubleword 31 SRCTYPE_UW = 0x2, // Unsigned Word integer 32 SRCTYPE_W = 0x3, // signed Word integer 33 SRCTYPE_UB = 0x4, // unsigned Byte integer 34 SRCTYPE_B = 0x5, // signed Byte integer 35 SRCTYPE_UQ = 0x6, // Unsigned Quadword integer 36 SRCTYPE_Q = 0x7, // signed Quadword integer 37 SRCTYPE_HF = 0x8, // Half Float (16-bit) 38 SRCTYPE_F = 0x9, // single precision Float (32-bit) 39 SRCTYPE_DF = 0xA, // Double precision Float (64-bit) 40 } SRCTYPE; 41 42 typedef enum tagSRCIMMTYPE { 43 SRCIMMTYPE_UD = 0x0, // Unsigned Doubleword 44 SRCIMMTYPE_D = 0x1, // signed Doubleword 45 SRCIMMTYPE_UW = 0x2, // Unsigned Word integer 46 SRCIMMTYPE_W = 0x3, // signed Word integer 47 SRCIMMTYPE_UV = 0x4, // Packed Unsigned Half-Byte Integer Vector, 8 x 4-Bit Unsigned Integer. 48 SRCIMMTYPE_V = 0x5, // Packed Signed Half-Byte Integer Vector, 8 x 4-Bit Signed Integer 49 SRCIMMTYPE_UQ = 0x6, // Unsigned Quadword integer// Double precision Float (64-bit) 50 SRCIMMTYPE_Q = 0x7, // signed Quadword integer 51 SRCIMMTYPE_HF = 0x8, // Half Float (16-bit) 52 SRCIMMTYPE_F = 0x9, // single precision Float (32-bit) 53 SRCIMMTYPE_DF = 0xA, // Double precision Float (64-bit) 54 SRCIMMTYPE_VF = 0xB, // Packed Restricted Float Vector, 4 x 8-Bit Restricted Precision Floating-Point Number 55 } SRCIMMTYPE; 56 } 57 #endif 58