1 /*========================== begin_copyright_notice ============================
2
3 Copyright (C) 2017-2021 Intel Corporation
4
5 SPDX-License-Identifier: MIT
6
7 ============================= end_copyright_notice ===========================*/
8
9 /*
10 * ISA Instruction Description
11 *
12 * This file contains tables used to define ISA instructions.
13 * These tables are exposed in the corresponding header with
14 * external linkage alone with their associated enums.
15 */
16
17 #include "IGC/common/StringMacros.hpp"
18 #include "Common_ISA.h"
19 #include "IsaDescription.h"
20
21 struct ISA_Inst_Info ISA_Inst_Table[ISA_OPCODE_ENUM_SIZE] =
22 {
23 { ISA_RESERVED_0, ISA_Inst_Reserved, "reserved0", 0, 0 },
24 { ISA_ADD, ISA_Inst_Arith, "add", 2, 1 },
25 { ISA_AVG, ISA_Inst_Arith, "avg", 2, 1 },
26 { ISA_DIV, ISA_Inst_Arith, "div", 2, 1 },
27 { ISA_DP2, ISA_Inst_Arith, "dp2", 2, 1 },
28 { ISA_DP3, ISA_Inst_Arith, "dp3", 2, 1 },
29 { ISA_DP4, ISA_Inst_Arith, "dp4", 2, 1 },
30 { ISA_DPH, ISA_Inst_Arith, "dph", 2, 1 },
31 { ISA_EXP, ISA_Inst_Arith, "exp", 1, 1 },
32 { ISA_FRC, ISA_Inst_Arith, "frc", 1, 1 },
33 { ISA_LINE, ISA_Inst_Arith, "line", 2, 1 },
34 { ISA_LOG, ISA_Inst_Arith, "log", 1, 1 },
35 { ISA_MAD, ISA_Inst_Arith, "mad", 3, 1 },
36 { ISA_MULH, ISA_Inst_Arith, "mulh", 2, 1 },
37 { ISA_LRP, ISA_Inst_Arith, "lrp", 3, 1 },
38 { ISA_MOD, ISA_Inst_Arith, "mod", 2, 1 },
39 { ISA_MUL, ISA_Inst_Arith, "mul", 2, 1 },
40 { ISA_POW, ISA_Inst_Arith, "pow", 2, 1 },
41 { ISA_RNDD, ISA_Inst_Arith, "rndd", 1, 1 },
42 { ISA_RNDU, ISA_Inst_Arith, "rndu", 1, 1 },
43 { ISA_RNDE, ISA_Inst_Arith, "rnde", 1, 1 },
44 { ISA_RNDZ, ISA_Inst_Arith, "rndz", 1, 1 },
45 { ISA_SAD2, ISA_Inst_Arith, "sad2", 2, 1 },
46 { ISA_SIN, ISA_Inst_Arith, "sin", 1, 1 },
47 { ISA_COS, ISA_Inst_Arith, "cos", 1, 1 },
48 { ISA_SQRT, ISA_Inst_Arith, "sqrt", 1, 1 },
49 { ISA_RSQRT, ISA_Inst_Arith, "rsqrt", 1, 1 },
50 { ISA_INV, ISA_Inst_Arith, "inv", 1, 1 },
51 { ISA_DPASW, ISA_Inst_Misc, "dpasw", 3, 1 },
52 { ISA_FCVT, ISA_Inst_Mov, "fcvt", 1, 1 },
53 { ISA_SRND, ISA_Inst_Arith, "srnd", 2, 1 },
54 { ISA_LZD, ISA_Inst_Arith, "lzd", 1, 1 },
55 { ISA_AND, ISA_Inst_Logic, "and", 2, 1 },
56 { ISA_OR, ISA_Inst_Logic, "or", 2, 1 },
57 { ISA_XOR, ISA_Inst_Logic, "xor", 2, 1 },
58 { ISA_NOT, ISA_Inst_Logic, "not", 1, 1 },
59 { ISA_SHL, ISA_Inst_Logic, "shl", 2, 1 },
60 { ISA_SHR, ISA_Inst_Logic, "shr", 2, 1 },
61 { ISA_ASR, ISA_Inst_Logic, "asr", 2, 1 },
62 { ISA_CBIT, ISA_Inst_Logic, "cbit", 1, 1 },
63 { ISA_ADDR_ADD, ISA_Inst_Address, "addr_add", 2, 1 },
64 { ISA_MOV, ISA_Inst_Mov, "mov", 1, 1 },
65 { ISA_SEL, ISA_Inst_Mov, "sel", 2, 1 },
66 { ISA_SETP, ISA_Inst_Mov, "setp", 1, 1 },
67 { ISA_CMP, ISA_Inst_Compare, "cmp", 2, 1 },
68 { ISA_MOVS, ISA_Inst_Mov, "movs", 1, 1 },
69 { ISA_FBL, ISA_Inst_Logic, "fbl", 1, 1 },
70 { ISA_FBH, ISA_Inst_Logic, "fbh", 1, 1 },
71 { ISA_SUBROUTINE, ISA_Inst_Flow, "func", 1, 0 },
72 { ISA_LABEL, ISA_Inst_Flow, "label", 1, 0 },
73 { ISA_JMP, ISA_Inst_Flow, "jmp", 1, 0 },
74 { ISA_CALL, ISA_Inst_Flow, "call", 1, 0 },
75 { ISA_RET, ISA_Inst_Flow, "ret", 0, 0 },
76 { ISA_OWORD_LD, ISA_Inst_Data_Port, "oword_ld", 2, 1 },
77 { ISA_OWORD_ST, ISA_Inst_Data_Port, "oword_st", 3, 0 },
78 { ISA_MEDIA_LD, ISA_Inst_Data_Port, "media_ld", 5, 1 },
79 { ISA_MEDIA_ST, ISA_Inst_Data_Port, "media_st", 6, 0 },
80 { ISA_GATHER, ISA_Inst_Data_Port, "gather", 4, 1 },
81 { ISA_SCATTER, ISA_Inst_Data_Port, "scatter", 5, 0 },
82 { ISA_RESERVED_3B, ISA_Inst_Reserved, "reserved3b", 0, 0 },
83 { ISA_OWORD_LD_UNALIGNED, ISA_Inst_Data_Port, "oword_ld_unaligned", 2, 1 },
84 { ISA_RESERVED_3D, ISA_Inst_Reserved, "reserved3d", 0, 0 },
85 { ISA_RESERVED_3E, ISA_Inst_Reserved, "reserved3e", 0, 0 },
86 { ISA_RESERVED_3F, ISA_Inst_Reserved, "reserved3f", 0, 0 },
87 { ISA_SAMPLE, ISA_Inst_Sampler, "sample", 5, 1 },
88 { ISA_SAMPLE_UNORM, ISA_Inst_Sampler, "sample_unorm", 6, 1 },
89 { ISA_LOAD, ISA_Inst_Sampler, "load", 4, 1 },
90 { ISA_AVS, ISA_Inst_Sampler, "avs", 13, 1 },
91 { ISA_VA, ISA_Inst_Sampler , "va", 0, 0 },
92 { ISA_FMINMAX, ISA_Inst_Mov, "fminmax" , 2, 1 },
93 { ISA_BFE, ISA_Inst_Logic, "bfe" , 3, 1 },
94 { ISA_BFI, ISA_Inst_Logic, "bfi" , 4, 1 },
95 { ISA_BFREV, ISA_Inst_Logic, "bfrev" , 1, 1 },
96 { ISA_ADDC, ISA_Inst_Arith, "addc" , 2, 2 },
97 { ISA_SUBB, ISA_Inst_Arith, "subb" , 2, 2 },
98 { ISA_GATHER4_TYPED, ISA_Inst_Data_Port, "gather4_typed", 7, 1 },
99 { ISA_SCATTER4_TYPED, ISA_Inst_Data_Port, "scatter4_typed", 8, 0 },
100 { ISA_VA_SKL_PLUS, ISA_Inst_Sampler, "va_skl_plus", 0, 0 },
101 { ISA_SVM, ISA_Inst_SVM, "svm", 0, 0 },
102 { ISA_IFCALL, ISA_Inst_Flow, "ifcall", 3, 0 },
103 { ISA_FADDR, ISA_Inst_Flow, "faddr", 1, 1 },
104 { ISA_FILE, ISA_Inst_Misc, "file", 1, 0 },
105 { ISA_LOC, ISA_Inst_Misc, "loc", 1, 0 },
106 { ISA_RESERVED_53, ISA_Inst_Reserved, "reserved53", 0, 0 },
107 { ISA_VME_IME, ISA_Inst_Misc, "vme_ime", 5, 1 },
108 { ISA_VME_SIC, ISA_Inst_Misc, "vme_sic", 2, 1 },
109 { ISA_VME_FBR, ISA_Inst_Misc, "vme_fbr", 2, 1 },
110 { ISA_VME_IDM, ISA_Inst_Misc, "vme_idm", 2, 1 },
111 { ISA_RESERVED_58, ISA_Inst_Reserved, "reserved58", 0, 0 },
112 { ISA_BARRIER, ISA_Inst_Sync, "barrier", 0, 0 },
113 { ISA_SAMPLR_CACHE_FLUSH, ISA_Inst_Sync, "sampler_cache_flush", 0, 0 },
114 { ISA_WAIT, ISA_Inst_Sync, "wait", 0, 0 },
115 { ISA_FENCE, ISA_Inst_Sync, "fence", 0, 0 },
116 { ISA_RAW_SEND, ISA_Inst_Misc, "raw_send", 0, 0 },
117 { ISA_RESERVED_5E, ISA_Inst_Reserved, "reserved5E", 0, 0 },
118 { ISA_YIELD, ISA_Inst_Sync, "yield", 0, 0 },
119 { ISA_NBARRIER, ISA_Inst_Sync, "nbarrier", 0, 1 },
120 { ISA_RESERVED_61, ISA_Inst_Reserved, "reserved61", 0, 0 },
121 { ISA_RESERVED_62, ISA_Inst_Reserved, "reserved62", 0, 0 },
122 { ISA_RESERVED_63, ISA_Inst_Reserved, "reserved63", 0, 0 },
123 { ISA_RESERVED_64, ISA_Inst_Reserved, "reserved64", 0, 0 },
124 { ISA_RESERVED_65, ISA_Inst_Reserved, "reserved65", 0, 0 },
125 { ISA_RESERVED_66, ISA_Inst_Reserved, "reserved66", 0, 0 },
126 { ISA_FCALL, ISA_Inst_Flow, "fcall", 3, 0 },
127 { ISA_FRET, ISA_Inst_Flow, "fret", 0, 0 },
128 { ISA_SWITCHJMP, ISA_Inst_Flow, "switchjmp", 0, 0 },
129 { ISA_SAD2ADD, ISA_Inst_Arith, "sad2add", 3, 1 },
130 { ISA_PLANE, ISA_Inst_Arith, "plane", 2, 1 },
131 { ISA_GOTO, ISA_Inst_SIMD_Flow, "goto", 1, 0 },
132 { ISA_3D_SAMPLE, ISA_Inst_Sampler, "sample_3d", 5, 1 },
133 { ISA_3D_LOAD, ISA_Inst_Sampler, "load_3d", 5, 1 },
134 { ISA_3D_GATHER4, ISA_Inst_Sampler, "gather4_3d", 5, 1 },
135 { ISA_3D_INFO, ISA_Inst_Sampler, "info_3d", 2, 1 },
136 { ISA_3D_RT_WRITE, ISA_Inst_Data_Port, "rt_write_3d", 3, 0 },
137 { ISA_3D_URB_WRITE, ISA_Inst_Misc, "urb_write_3d", 6, 0 },
138 { ISA_3D_TYPED_ATOMIC, ISA_Inst_Data_Port, "typed_atomic", 9, 1 },
139 { ISA_GATHER4_SCALED, ISA_Inst_Data_Port, "gather4_scaled", 4, 1 },
140 { ISA_SCATTER4_SCALED, ISA_Inst_Data_Port, "scatter4_scaled", 5, 0 },
141 { ISA_RESERVED_76, ISA_Inst_Reserved, "reserved76", 0, 0 },
142 { ISA_RESERVED_77, ISA_Inst_Reserved, "reserved77", 0, 0 },
143 { ISA_GATHER_SCALED, ISA_Inst_Data_Port, "gather_scaled", 4, 1 },
144 { ISA_SCATTER_SCALED, ISA_Inst_Data_Port, "scatter_scaled", 5, 0 },
145 { ISA_RAW_SENDS, ISA_Inst_Misc, "raw_sends", 0, 0 },
146 { ISA_LIFETIME, ISA_Inst_Misc, "lifetime", 2, 0 },
147 { ISA_SBARRIER, ISA_Inst_Sync, "sbarrier", 1, 0 },
148 { ISA_DWORD_ATOMIC, ISA_Inst_Data_Port, "dword_atomic", 5, 1 },
149 { ISA_SQRTM, ISA_Inst_Arith, "sqrtm", 1, 1 },
150 { ISA_DIVM, ISA_Inst_Arith, "divm", 2, 1 },
151 { ISA_ROL, ISA_Inst_Logic, "rol", 2, 1 },
152 { ISA_ROR, ISA_Inst_Logic, "ror", 2, 1 },
153 { ISA_DP4A, ISA_Inst_Arith, "dp4a", 3, 1 },
154 { ISA_DPAS, ISA_Inst_Misc, "dpas", 3, 1 },
155 { ISA_ADD3, ISA_Inst_Arith, "add3", 3, 1 },
156 { ISA_BFN, ISA_Inst_Logic, "bfn", 3, 1 },
157 { ISA_QW_GATHER, ISA_Inst_Data_Port, "qw_gather", 3, 1 },
158 { ISA_QW_SCATTER, ISA_Inst_Data_Port, "qw_scatter", 4, 0 },
159 { ISA_BF_CVT, ISA_Inst_Mov, "bf_cvt", 1, 1 },
160 { ISA_LSC_UNTYPED, ISA_Inst_LSC, "lsc_untyped", 0, 0 },
161 { ISA_LSC_TYPED, ISA_Inst_LSC, "lsc_typed", 0, 0 },
162 { ISA_LSC_FENCE, ISA_Inst_LSC, "lsc_fence", 0, 0 },
163 { ISA_RESERVED_8C, ISA_Inst_Reserved, "reserved8c", 0, 0 },
164 { ISA_RESERVED_8D, ISA_Inst_Reserved, "reserved8d", 0, 0 },
165 { ISA_RESERVED_8E, ISA_Inst_Reserved, "reserved8e", 0, 0 },
166 { ISA_RESERVED_8F, ISA_Inst_Reserved, "reserved8f", 0, 0 },
167 { ISA_RESERVED_90, ISA_Inst_Reserved, "reserved90", 0, 0 },
168 { ISA_MADW, ISA_Inst_Arith, "madw", 3, 1 },
169 { ISA_ADD3O, ISA_Inst_Arith, "add3.o", 3, 1 }
170 };
171
172
173 VISA_INST_Desc CISA_INST_table[ISA_NUM_OPCODE] =
174 {
175 /// 0
176 { ALL, ISA_RESERVED_0, ISA_Inst_Reserved, "RESERVED_0", 0, 0,
177 {
178 },
179
180 },
181
182 /// 1
183 { ALL, ISA_ADD, ISA_Inst_Arith, "add", 5, SAME_DATA_TYPE,
184 {
185 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
186 {OPND_PRED, ISA_TYPE_UW, 0},
187 {OPND_VECTOR_DST_G_I, TYPE_INTEGER | TYPE_FLOAT_ALL, 0},
188 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_INTEGER | TYPE_FLOAT_ALL, 0},
189 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_INTEGER | TYPE_FLOAT_ALL, 0},
190 },
191
192 },
193
194 /// 2
195 { ALL, ISA_AVG, ISA_Inst_Arith, "avg", 5, SAME_DATA_TYPE,
196 {
197 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
198 {OPND_PRED, ISA_TYPE_UW, 0},
199 {OPND_VECTOR_DST_G_I, TYPE_INTEGER, 0},
200 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_INTEGER, 0},
201 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_INTEGER, 0},
202 },
203
204 },
205
206 /// 3
207 { ALL, ISA_DIV, ISA_Inst_Arith, "div", 5, SAME_DATA_TYPE,
208 {
209 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
210 {OPND_PRED, ISA_TYPE_UW, 0},
211 {OPND_VECTOR_DST_G_I, TYPE_INTEGER | TYPE_FLOAT, SAT_FLOAT_ONLY},
212 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_INTEGER | TYPE_FLOAT_HF, 0},
213 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_INTEGER | TYPE_FLOAT_HF, 0},
214 },
215
216 },
217
218 /// 0x4
219 { ALL, ISA_DP2, ISA_Inst_Arith, "dp2", 5, SAME_DATA_TYPE,
220 {
221 {OPND_EXECSIZE, ISA_TYPE_UB, GE_4},
222 {OPND_PRED, ISA_TYPE_UW, 0},
223 {OPND_VECTOR_DST_G_I, TYPE_FLOAT, SAT_C | HORIZON_STRIDE_1},
224 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT, HORIZON_STRIDE_1},
225 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT, HORIZON_STRIDE_1},
226 },
227
228 },
229
230 /// 5
231 { ALL, ISA_DP3, ISA_Inst_Arith, "dp3", 5, SAME_DATA_TYPE,
232 {
233 {OPND_EXECSIZE, ISA_TYPE_UB, GE_4},
234 {OPND_PRED, ISA_TYPE_UW, 0},
235 {OPND_VECTOR_DST_G_I, TYPE_FLOAT, SAT_C | HORIZON_STRIDE_1},
236 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT, HORIZON_STRIDE_1},
237 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT, HORIZON_STRIDE_1},
238 },
239
240 },
241
242 /// 6
243 { ALL, ISA_DP4, ISA_Inst_Arith, "dp4", 5, SAME_DATA_TYPE,
244 {
245 {OPND_EXECSIZE, ISA_TYPE_UB, GE_4},
246 {OPND_PRED, ISA_TYPE_UW, 0},
247 {OPND_VECTOR_DST_G_I, TYPE_FLOAT, SAT_C | HORIZON_STRIDE_1},
248 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT, HORIZON_STRIDE_1},
249 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT, HORIZON_STRIDE_1},
250 },
251
252 },
253
254 /// 7
255 { ALL, ISA_DPH, ISA_Inst_Arith, "dph", 5, SAME_DATA_TYPE,
256 {
257 {OPND_EXECSIZE, ISA_TYPE_UB, GE_4},
258 {OPND_PRED, ISA_TYPE_UW, 0},
259 {OPND_VECTOR_DST_G_I, TYPE_FLOAT, SAT_C | HORIZON_STRIDE_1},
260 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT, HORIZON_STRIDE_1},
261 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT, HORIZON_STRIDE_1},
262 },
263
264 },
265
266 /// 8
267 { ALL, ISA_EXP, ISA_Inst_Arith, "exp", 4, SAME_DATA_TYPE,
268 {
269 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
270 {OPND_PRED, ISA_TYPE_UW, 0},
271 {OPND_VECTOR_DST_G_I, TYPE_FLOAT_HF, SAT_C | HORIZON_STRIDE_1},
272 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_HF, HORIZON_STRIDE_1},
273 },
274
275 },
276
277 /// 9
278 { ALL, ISA_FRC, ISA_Inst_Arith, "frc", 4, SAME_DATA_TYPE,
279 {
280 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
281 {OPND_PRED, ISA_TYPE_UW, 0},
282 {OPND_VECTOR_DST_G_I, TYPE_FLOAT, 0},
283 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT, 0},
284 },
285
286 },
287
288 /// 10
289 { ALL, ISA_LINE, ISA_Inst_Arith, "line", 5, SAME_DATA_TYPE,
290 {
291 {OPND_EXECSIZE, ISA_TYPE_UB, GE_4},
292 {OPND_PRED, ISA_TYPE_UW, 0},
293 {OPND_VECTOR_DST_G_I, TYPE_INTEGER | TYPE_FLOAT, SAT_C},
294 {OPND_SRC_GEN, TYPE_INTEGER | TYPE_FLOAT, HORIZON_VERTICAL_STRIDE_0},
295 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_INTEGER | TYPE_FLOAT, 0},
296 },
297
298 },
299
300 /// 11
301 { ALL, ISA_LOG, ISA_Inst_Arith, "log", 4, SAME_DATA_TYPE,
302 {
303 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
304 {OPND_PRED, ISA_TYPE_UW, 0},
305 {OPND_VECTOR_DST_G_I, TYPE_FLOAT_HF, SAT_C},
306 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_HF, 0},
307 },
308
309 },
310
311 /// 12
312 { ALL, ISA_MAD, ISA_Inst_Arith, "mad", 6, SAME_DATA_TYPE,
313 {
314 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
315 {OPND_PRED, ISA_TYPE_UW, 0},
316 {OPND_VECTOR_DST_G_I, TYPE_FLOAT_ALL, SAT_FLOAT_ONLY},
317 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_ALL, 0},
318 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_ALL, 0},
319 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_ALL, 0},
320 },
321
322 },
323
324 /// 13
325 { ALL, ISA_MULH, ISA_Inst_Arith, "mulh", 5, SAME_DATA_TYPE,
326 {
327 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
328 {OPND_PRED, ISA_TYPE_UW, 0},
329 {OPND_VECTOR_DST_G_I, ISA_TYPE_UD | ISA_TYPE_D, 0},
330 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_UD | ISA_TYPE_D, 0},
331 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_UD | ISA_TYPE_D, 0},
332 },
333
334 },
335
336 /// 14
337 { ALL, ISA_LRP, ISA_Inst_Reserved, "lrp", 6, SAME_DATA_TYPE,
338 {
339 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
340 {OPND_PRED, ISA_TYPE_UW, 0},
341 {OPND_VECTOR_DST_G_I, TYPE_FLOAT, SAT_FLOAT_ONLY},
342 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT, 0},
343 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT, 0},
344 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT, 0},
345 },
346
347 },
348
349 /// 15
350 { ALL, ISA_MOD, ISA_Inst_Arith, "mod", 5, SAME_DATA_TYPE,
351 {
352 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
353 {OPND_PRED, ISA_TYPE_UW, 0},
354 {OPND_VECTOR_DST_G_I, TYPE_INTEGER, 0},
355 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_INTEGER, 0},
356 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_INTEGER, 0},
357 },
358
359 },
360
361 /// 16
362 { ALL, ISA_MUL, ISA_Inst_Arith, "mul", 5, SAME_DATA_TYPE,
363 {
364 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
365 {OPND_PRED, ISA_TYPE_UW, 0},
366 {OPND_VECTOR_DST_G_I, TYPE_FLOAT_ALL | TYPE_INTEGER, SAT_C},
367 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_ALL | TYPE_INTEGER, 0},
368 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_ALL | TYPE_INTEGER, 0},
369 },
370
371 },
372
373 /// 17
374 { ALL, ISA_POW, ISA_Inst_Arith, "pow", 5, SAME_DATA_TYPE,
375 {
376 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
377 {OPND_PRED, ISA_TYPE_UW, 0},
378 {OPND_VECTOR_DST_G_I, TYPE_FLOAT_HF, SAT_C},
379 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_HF, 0},
380 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_HF, 0},
381 },
382
383 },
384
385 /// 18
386 { ALL, ISA_RNDD, ISA_Inst_Arith, "rndd", 4, SAME_DATA_TYPE,
387 {
388 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
389 {OPND_PRED, ISA_TYPE_UW, 0},
390 {OPND_VECTOR_DST_G_I, TYPE_FLOAT, SAT_C},
391 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT, 0},
392 },
393
394 },
395
396 /// 19
397 { ALL, ISA_RNDU, ISA_Inst_Arith, "rndu", 4, SAME_DATA_TYPE,
398 {
399 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
400 {OPND_PRED, ISA_TYPE_UW, 0},
401 {OPND_VECTOR_DST_G_I, TYPE_FLOAT, SAT_C},
402 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT, 0},
403 },
404
405 },
406
407 /// 20
408 { ALL, ISA_RNDE, ISA_Inst_Arith, "rnde", 4, SAME_DATA_TYPE,
409 {
410 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
411 {OPND_PRED, ISA_TYPE_UW, 0},
412 {OPND_VECTOR_DST_G_I, TYPE_FLOAT, SAT_C},
413 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT, 0},
414 },
415
416 },
417
418 /// 21
419 { ALL, ISA_RNDZ, ISA_Inst_Arith, "rndz", 4, SAME_DATA_TYPE,
420 {
421 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
422 {OPND_PRED, ISA_TYPE_UW, 0},
423 {OPND_VECTOR_DST_G_I, TYPE_FLOAT, SAT_C},
424 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT, 0},
425 },
426
427 },
428
429 /// 22
430 { ALL, ISA_SAD2, ISA_Inst_Arith, "sad2", 5, SAME_DATA_TYPE,
431 {
432 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
433 {OPND_PRED, ISA_TYPE_UW, 0},
434 {OPND_VECTOR_DST_G_I, ISA_TYPE_W | ISA_TYPE_UW, SAT_C | HORIZON_STRIDE_2},
435 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_B | ISA_TYPE_UB, 0},
436 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_B | ISA_TYPE_UB, 0},
437 },
438
439 },
440
441 /// 23
442 { ALL, ISA_SIN, ISA_Inst_Arith, "sin", 4, SAME_DATA_TYPE,
443 {
444 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
445 {OPND_PRED, ISA_TYPE_UW, 0},
446 {OPND_VECTOR_DST_G_I, TYPE_FLOAT_HF, SAT_C},
447 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_HF, 0},
448 },
449
450 },
451
452 /// 24
453 { ALL, ISA_COS, ISA_Inst_Arith, "cos", 4, SAME_DATA_TYPE,
454 {
455 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
456 {OPND_PRED, ISA_TYPE_UW, 0},
457 {OPND_VECTOR_DST_G_I, TYPE_FLOAT_HF, SAT_C},
458 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_HF, 0},
459 },
460
461 },
462
463 /// 25
464 { ALL, ISA_SQRT, ISA_Inst_Arith, "sqrt", 4, SAME_DATA_TYPE,
465 {
466 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
467 {OPND_PRED, ISA_TYPE_UW, 0},
468 {OPND_VECTOR_DST_G_I, TYPE_FLOAT_HF, SAT_C},
469 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_HF, 0},
470 },
471
472 },
473
474 /// 26
475 { ALL, ISA_RSQRT, ISA_Inst_Arith, "rsqrt", 4, SAME_DATA_TYPE,
476 {
477 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
478 {OPND_PRED, ISA_TYPE_UW, 0},
479 {OPND_VECTOR_DST_G_I, TYPE_FLOAT_HF, SAT_C},
480 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_HF, 0},
481 },
482
483 },
484
485 /// 27
486 { ALL, ISA_INV, ISA_Inst_Arith, "inv", 4, SAME_DATA_TYPE,
487 {
488 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
489 {OPND_PRED, ISA_TYPE_UW, 0},
490 {OPND_VECTOR_DST_G_I, TYPE_FLOAT_HF, SAT_C},
491 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT_HF, 0},
492 },
493
494 },
495
496 /// 28 (0x1C)
497 { XeHP_SDV, ISA_DPASW, ISA_Inst_Misc, "dpasw", 6, SAME_DATA_TYPE,
498 {
499 { OPND_EXECSIZE, ISA_TYPE_UB, 0 },
500 { OPND_DST_GEN, ISA_TYPE_D | ISA_TYPE_UD | ISA_TYPE_F, GRF_ALIGNED },
501 { OPND_SRC_GEN, ISA_TYPE_D | ISA_TYPE_UD | ISA_TYPE_F, GRF_ALIGNED },
502 { OPND_SRC_GEN, ISA_TYPE_D | ISA_TYPE_UD, GRF_ALIGNED },
503 { OPND_SRC_GEN, ISA_TYPE_D | ISA_TYPE_UD, GRF_ALIGNED },
504 { OPND_OTHER, ISA_TYPE_UD, 0 }
505 },
506 },
507
508 /// 29 (0x1D)
509 { GENX_PVC, ISA_FCVT, ISA_Inst_Mov, "fcvt", 3, SAME_SPECIAL_KIND,
510 {
511 { OPND_EXECSIZE, ISA_TYPE_UB, 0 },
512 { OPND_DST_GEN, ISA_TYPE_UB | ISA_TYPE_UD | ISA_TYPE_HF | ISA_TYPE_F, 0 },
513 { OPND_SRC_GEN, ISA_TYPE_UB | ISA_TYPE_UD | ISA_TYPE_HF | ISA_TYPE_F, 0 },
514 },
515 },
516
517 /// 30 (0x1E)
518 { GENX_PVCXT, ISA_SRND, ISA_Inst_Arith, "srnd", 4, SAME_SPECIAL_KIND,
519 {
520 { OPND_EXECSIZE, ISA_TYPE_UB, 0 },
521 { OPND_DST_GEN, ISA_TYPE_UB | ISA_TYPE_HF, 0 },
522 { OPND_SRC_GEN, ISA_TYPE_F | ISA_TYPE_HF, 0 },
523 { OPND_SRC_GEN | OPND_IMM, ISA_TYPE_F | ISA_TYPE_HF, 0 },
524 },
525 },
526
527 /// 31
528 { ALL, ISA_LZD, ISA_Inst_Arith, "lzd", 4, SAME_DATA_TYPE,
529 {
530 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
531 {OPND_PRED, ISA_TYPE_UW, 0},
532 {OPND_VECTOR_DST_G_I, ISA_TYPE_UD, 0},
533 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_UD, 0},
534 },
535
536 },
537
538 /// 32
539 { ALL, ISA_AND, ISA_Inst_Logic, "and", 5, SAME_DATA_TYPE,
540 {
541 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
542 {OPND_PRED, ISA_TYPE_UW, PREDICATE_NONEPRED_OPND},
543 {OPND_VECTOR_DST_G_I_P, TYPE_INTEGER, 0},
544 {OPND_VECTOR_SRC_G_I_IMM_P_AO, TYPE_INTEGER, 0},
545 {OPND_VECTOR_SRC_G_I_IMM_P_AO, TYPE_INTEGER, 0},
546 },
547
548 },
549
550 /// 33
551 { ALL, ISA_OR, ISA_Inst_Logic, "or", 5, SAME_DATA_TYPE,
552 {
553 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
554 {OPND_PRED, ISA_TYPE_UW, PREDICATE_NONEPRED_OPND},
555 {OPND_VECTOR_DST_G_I_P, TYPE_INTEGER, 0},
556 {OPND_VECTOR_SRC_G_I_IMM_P_AO, TYPE_INTEGER, 0},
557 {OPND_VECTOR_SRC_G_I_IMM_P_AO, TYPE_INTEGER, 0},
558 },
559
560 },
561
562 /// 34
563 { ALL, ISA_XOR, ISA_Inst_Logic, "xor", 5, SAME_DATA_TYPE,
564 {
565 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
566 {OPND_PRED, ISA_TYPE_UW, PREDICATE_NONEPRED_OPND},
567 {OPND_VECTOR_DST_G_I_P, TYPE_INTEGER, 0},
568 {OPND_VECTOR_SRC_G_I_IMM_P_AO, TYPE_INTEGER, 0},
569 {OPND_VECTOR_SRC_G_I_IMM_P_AO, TYPE_INTEGER, 0},
570 },
571
572 },
573
574 /// 35
575 { ALL, ISA_NOT, ISA_Inst_Logic, "not", 4, SAME_DATA_TYPE,
576 {
577 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
578 {OPND_PRED, ISA_TYPE_UW, PREDICATE_NONEPRED_OPND},
579 {OPND_VECTOR_DST_G_I_P, TYPE_INTEGER, 0},
580 {OPND_VECTOR_SRC_G_I_IMM_P_AO, TYPE_INTEGER, 0},
581 },
582
583 },
584
585 /// 36
586 { ALL, ISA_SHL, ISA_Inst_Logic, "shl", 5, 0,
587 {
588 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
589 {OPND_PRED, ISA_TYPE_UW, PREDICATE_NONEPRED_OPND},
590 {OPND_VECTOR_DST_G_I, TYPE_INTEGER, 0},
591 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_INTEGER, 0},
592 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_INTEGER, 0},
593 },
594
595 },
596
597 /// 37
598 { ALL, ISA_SHR, ISA_Inst_Logic, "shr", 5, 0,
599 {
600 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
601 {OPND_PRED, ISA_TYPE_UW, PREDICATE_NONEPRED_OPND},
602 {OPND_VECTOR_DST_G_I, TYPE_INTEGER, 0},
603 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_INTEGER, 0},
604 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_INTEGER, 0},
605 },
606
607 },
608
609 /// 38
610 { ALL, ISA_ASR, ISA_Inst_Logic, "asr", 5, 0,
611 {
612 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
613 {OPND_PRED, ISA_TYPE_UW, PREDICATE_NONEPRED_OPND},
614 {OPND_VECTOR_DST_G_I, ISA_TYPE_B | ISA_TYPE_W | ISA_TYPE_D, 0},
615 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_B | ISA_TYPE_W | ISA_TYPE_D, 0},
616 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_INTEGER, 0},
617 },
618
619 },
620
621 /// 39
622 { ALL, ISA_CBIT, ISA_Inst_Logic, "cbit", 4, 0,
623 {
624 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
625 {OPND_PRED, ISA_TYPE_UW, PREDICATE_NONEPRED_OPND},
626 {OPND_VECTOR_DST_G_I, ISA_TYPE_UD, 0},
627 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_INTEGER, 0},
628 },
629
630 },
631
632 /// 40
633 { ALL, ISA_ADDR_ADD, ISA_Inst_Address, "addr_add", 4, 0,
634 {
635 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
636 {OPND_DST_ADDR, 0, 0},
637 {OPND_VECTOR_SRC_G_A_AO, 0, SCALAR_REGION},
638 {OPND_VECTOR_SRC_G_IMM_AO, ISA_TYPE_UW, 0},
639 },
640
641 },
642
643 /// 41
644 { ALL, ISA_MOV, ISA_Inst_Mov, "mov", 4, 0,
645 {
646 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
647 {OPND_PRED, ISA_TYPE_UW, 0},
648 {OPND_VECTOR_DST_G_I, 0, 0},
649 {OPND_VECTOR_SRC_G_I_IMM_AO, 0, 0},
650 },
651
652 },
653
654 /// 42
655 { ALL, ISA_SEL, ISA_Inst_Mov, "sel", 5, 0,
656 {
657 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
658 {OPND_PRED, ISA_TYPE_UW, 0},
659 {OPND_VECTOR_DST_G_I, 0, 0},
660 {OPND_VECTOR_SRC_G_I_IMM_AO, 0, 0},
661 {OPND_VECTOR_SRC_G_I_IMM_AO, 0, 0},
662 },
663
664 },
665
666 /// 43
667 { ALL, ISA_SETP, ISA_Inst_Mov, "setp", 3, 0,
668 {
669 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
670 {OPND_DST_PRED, 0, 0},
671 {OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_INTEGER, 0},
672 },
673
674 },
675
676 /// 44
677 { ALL, ISA_CMP, ISA_Inst_Compare, "cmp", 5, SAME_DATA_TYPE,
678 {
679 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
680 {OPND_CMP_SUBOP, ISA_TYPE_UB, 0},
681 {OPND_DST_PRED|OPND_DST_GEN, 0, 0},
682 {OPND_VECTOR_SRC_G_I_IMM_AO, 0, 0},
683 {OPND_VECTOR_SRC_G_I_IMM_AO, 0, 0},
684 },
685
686 },
687
688 /// 45
689 { ALL, ISA_MOVS, ISA_Inst_Mov, "movs", 3, SAME_SPECIAL_KIND,
690 {
691 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
692 {OPND_SPECIAL, ISA_TYPE_UW, 0},
693 {OPND_SPECIAL, ISA_TYPE_UW, 0},
694 },
695
696 },
697
698 /// 46
699 { ALL, ISA_FBL, ISA_Inst_Logic, "fbl", 4, 0,
700 {
701 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
702 {OPND_PRED, ISA_TYPE_UW, 0},
703 {OPND_VECTOR_DST_G_I, ISA_TYPE_UD, 0},
704 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_UD, 0},
705 },
706
707 },
708
709 /// 47
710 { ALL, ISA_FBH, ISA_Inst_Logic, "fbh", 4, 0,
711 {
712 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
713 {OPND_PRED, ISA_TYPE_UW, 0},
714 {OPND_VECTOR_DST_G_I, ISA_TYPE_UD, 0},
715 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_UD | ISA_TYPE_D, 0},
716 },
717
718 },
719
720 /// 48
721 { ALL, ISA_SUBROUTINE, ISA_Inst_Flow, "func", 1, 0,
722 {
723 {OPND_LABEL, ISA_TYPE_UW, 0},
724 },
725
726 },
727
728 /// 49
729 { ALL, ISA_LABEL, ISA_Inst_Flow, "label", 1, 0,
730 {
731 {OPND_LABEL, ISA_TYPE_UW, 0},
732 },
733
734 },
735
736 /// 50
737 { ALL, ISA_JMP, ISA_Inst_Flow, "jmp", 3, 0,
738 {
739 {OPND_EXECSIZE, ISA_TYPE_UB, SIZE_1},
740 {OPND_PRED, ISA_TYPE_UW, 0},
741 {OPND_LABEL, ISA_TYPE_UW, LABEL_BLOCK_C},
742 },
743
744 },
745
746 /// 51
747 { ALL, ISA_CALL, ISA_Inst_Flow, "call", 3, 0,
748 {
749 {OPND_EXECSIZE, ISA_TYPE_UB, SIZE_1},
750 {OPND_PRED, ISA_TYPE_UW, 0},
751 {OPND_LABEL, ISA_TYPE_UW, LABEL_FUNC_C},
752 },
753
754 },
755
756 /// 52
757 { ALL, ISA_RET, ISA_Inst_Flow, "ret", 2, 0,
758 {
759 {OPND_EXECSIZE, ISA_TYPE_UB, SIZE_1},
760 {OPND_PRED, ISA_TYPE_UW, 0},
761 },
762
763 },
764
765 /// 53
766 { ALL, ISA_OWORD_LD, ISA_Inst_Data_Port, "oword_ld", 5, 0,
767 {
768 {OPND_OWORD_SIZE, ISA_TYPE_UB, 0},
769 {OPND_IS_MODIFIED, ISA_TYPE_UB, 0},
770 {OPND_SURFACE, ISA_TYPE_UB, 0},
771 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_UD, SCALAR_REGION},
772 {OPND_RAW, 0, GE_READSIZE},
773 },
774
775 },
776
777 /// 54
778 { ALL, ISA_OWORD_ST, ISA_Inst_Data_Port, "oword_st", 4, 0,
779 {
780 {OPND_OWORD_SIZE, ISA_TYPE_UB, 0},
781 {OPND_SURFACE, ISA_TYPE_UB, 0},
782 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_UD, SCALAR_REGION},
783 {OPND_RAW, 0, GE_WRITESIZE},
784 },
785
786 },
787
788 /// 55
789 { ALL, ISA_MEDIA_LD, ISA_Inst_Data_Port, "media_ld", 8, 0,
790 {
791 {OPND_MEDIA_LD_MODIFIER, ISA_TYPE_UB, 0},
792 {OPND_SURFACE, ISA_TYPE_UB, 0},
793 {OPND_PLANE, ISA_TYPE_UB, VALUE_0_3},
794 {OPND_BLOCK_WIDTH, ISA_TYPE_UB, VALUE_1_32},
795 {OPND_BLOCK_HEIGHT, ISA_TYPE_UB, VALUE_1_64},
796 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_UD, SCALAR_REGION},
797 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_UD, SCALAR_REGION},
798 {OPND_RAW, 0, GRF_ALIGNED |SIZE_GE_WIDTH_M_HIEGH},
799 },
800
801 },
802
803 /// 56
804 { ALL, ISA_MEDIA_ST, ISA_Inst_Data_Port, "media_st", 8, 0,
805 {
806 {OPND_MEDIA_ST_MODIFIER, ISA_TYPE_UB, 0},
807 {OPND_SURFACE, ISA_TYPE_UB, 0},
808 {OPND_PLANE, ISA_TYPE_UB, VALUE_0_3},
809 {OPND_BLOCK_WIDTH, ISA_TYPE_UB, VALUE_1_32},
810 {OPND_BLOCK_HEIGHT, ISA_TYPE_UB, VALUE_1_64},
811 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_UD, SCALAR_REGION},
812 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_UD, SCALAR_REGION},
813 {OPND_RAW, 0, GRF_ALIGNED |SIZE_GE_WIDTH_M_HIEGH},
814 },
815
816 },
817
818 /// 57
819 { ALL, ISA_GATHER, ISA_Inst_Data_Port, "gather", 7, 0,
820 {
821 {OPND_ELEM_SIZE, ISA_TYPE_UB, 0},
822 {OPND_IS_MODIFIED, ISA_TYPE_UB, 0},
823 {OPND_ELEM_NUM, ISA_TYPE_UB, ELEM_NUM_8_16},
824 {OPND_SURFACE, ISA_TYPE_UB, 0},
825 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_UD, SCALAR_REGION},
826 {OPND_RAW, ISA_TYPE_UD, GRF_ALIGNED},
827 {OPND_RAW, ISA_TYPE_UD | ISA_TYPE_D | ISA_TYPE_F, GRF_ALIGNED},
828 },
829
830 },
831
832 /// 58
833 { ALL, ISA_SCATTER, ISA_Inst_Data_Port, "scatter", 6, 0,
834 {
835 {OPND_ELEM_SIZE, ISA_TYPE_UB, 0},
836 {OPND_ELEM_NUM, ISA_TYPE_UB, ELEM_NUM_8_16},
837 {OPND_SURFACE, ISA_TYPE_UB, 0},
838 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_UD, SCALAR_REGION},
839 {OPND_RAW, ISA_TYPE_UD, GRF_ALIGNED},
840 {OPND_RAW, ISA_TYPE_UD | ISA_TYPE_D | ISA_TYPE_F, GRF_ALIGNED},
841 },
842
843 },
844
845 /// 59
846 { ALL, ISA_RESERVED_3B, ISA_Inst_Reserved, "reserved_3B", 8, 0,
847 {
848 },
849
850 },
851
852 /// 60
853 { ALL, ISA_OWORD_LD_UNALIGNED, ISA_Inst_Data_Port, "oword_ld_unaligned", 5, 0,
854 {
855 {OPND_OWORD_SIZE, ISA_TYPE_UB, 0},
856 {OPND_IS_MODIFIED, ISA_TYPE_UB, 0},
857 {OPND_SURFACE, ISA_TYPE_UB, 0},
858 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_UD, SCALAR_REGION},
859 {OPND_RAW, ISA_TYPE_UD, GRF_ALIGNED | GE_READSIZE},
860 },
861
862 },
863
864 /// 61
865 { ALL, ISA_RESERVED_3D, ISA_Inst_Reserved, "reserved_3D", 0, 0,
866 {
867 },
868 },
869
870 /// 62
871 { ALL, ISA_RESERVED_3E, ISA_Inst_Reserved, "reserved_3E", 0, 0,
872 {
873 },
874 },
875
876 /// 63
877 { ALL, ISA_RESERVED_3F, ISA_Inst_Reserved, "reserved_3F", 0, 0,
878 {
879 },
880 },
881
882 /// 64
883 { ALL, ISA_SAMPLE, ISA_Inst_Sampler, "sample", 7, 0,
884 {
885 {OPND_CHANNEL_SIMD_MODE, ISA_TYPE_UB, 0},
886 {OPND_SAMPLE, ISA_TYPE_UB, 0},
887 {OPND_SURFACE, ISA_TYPE_UB, 0},
888 {OPND_RAW, ISA_TYPE_F, GRF_ALIGNED},
889 {OPND_RAW, ISA_TYPE_F, GRF_ALIGNED},
890 {OPND_RAW, ISA_TYPE_F, GRF_ALIGNED},
891 {OPND_RAW, ISA_TYPE_F, GRF_ALIGNED},
892 },
893
894 },
895
896 /// 65
897 { ALL, ISA_SAMPLE_UNORM, ISA_Inst_Sampler, "sample_unorm", 8, 0,
898 {
899 {OPND_CHAN_PATT, ISA_TYPE_UB, 0},
900 {OPND_SAMPLE, ISA_TYPE_UB, 0},
901 {OPND_SURFACE, ISA_TYPE_UB, 0},
902 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_F, SCALAR_REGION},
903 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_F, SCALAR_REGION},
904 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_F, SCALAR_REGION},
905 {OPND_RAW, ISA_TYPE_UW, GRF_ALIGNED},
906 },
907
908 },
909
910 /// 66
911 { ALL, ISA_LOAD, ISA_Inst_Sampler, "load", 6, 0,
912 {
913 {OPND_CHANNEL_SIMD_MODE, ISA_TYPE_UB, 0},
914 {OPND_SURFACE, ISA_TYPE_UB, 0},
915 {OPND_RAW, ISA_TYPE_F, GRF_ALIGNED},
916 {OPND_RAW, ISA_TYPE_F, GRF_ALIGNED},
917 {OPND_RAW, ISA_TYPE_F, GRF_ALIGNED},
918 {OPND_RAW, ISA_TYPE_F, GRF_ALIGNED},
919 },
920
921 },
922
923 /// 67
924 { ALL, ISA_AVS, ISA_Inst_Sampler, "avs", 15, 1,
925 {
926 {OPND_CHANNEL_SIMD_MODE, ISA_TYPE_UB, 0},
927 {OPND_SAMPLE, ISA_TYPE_UB, 0},
928 {OPND_SURFACE, ISA_TYPE_UB, 0},
929 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION}, //uOffset
930 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION}, //vOffset
931 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION}, //deltaU
932 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION}, //deltaV
933 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION}, //u2d
934 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION}, //groupID
935 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION}, //verticalBlockNumber
936 {OPND_OTHER, ISA_TYPE_UB, 0}, //cntrl
937 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION}, //v2d
938 {OPND_OTHER, ISA_TYPE_UB, 0}, //execMode
939 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UW | ISA_TYPE_UD, SCALAR_REGION}, //IEFBypass
940 {OPND_RAW, ISA_TYPE_F, GRF_ALIGNED}, //dst
941 },
942
943 },
944
945 /// 68
946 { ALL, ISA_VA, ISA_Inst_Sampler, "va", 1, 1,
947 {
948 {OPND_SUBOPCODE, ISA_TYPE_UB, 0}
949 },
950
951 },
952
953 /// 69
954 { ALL, ISA_FMINMAX, ISA_Inst_Mov, "fminmax", 5, 0,
955 {
956 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
957 {OP_EXT, ISA_TYPE_UB, 0},
958 {OPND_VECTOR_DST_G_I, 0, 0},
959 {OPND_VECTOR_SRC_G_I_IMM, 0, 0},
960 {OPND_VECTOR_SRC_G_I_IMM, 0, 0},
961
962 },
963
964 },
965
966 /// 70
967 { ALL, ISA_BFE, ISA_Inst_Logic, "bfe", 6, 0,
968 {
969 {OPND_EXECSIZE, ISA_TYPE_UB, 0}, /// exec_size
970 {OPND_PRED, ISA_TYPE_UW, 0}, /// predicate
971 {OPND_VECTOR_DST_G_I, ISA_TYPE_UD|ISA_TYPE_D, GRF_ALIGNED},
972 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UD|ISA_TYPE_D, GRF_ALIGNED},
973 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UD|ISA_TYPE_D, GRF_ALIGNED},
974 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UD|ISA_TYPE_D, GRF_ALIGNED},
975
976 },
977
978 },
979
980 /// 71
981 { ALL, ISA_BFI, ISA_Inst_Logic, "bfi", 7, 0,
982 {
983 {OPND_EXECSIZE, ISA_TYPE_UB, 0}, /// exec_size
984 {OPND_PRED, ISA_TYPE_UW, 0}, /// predicate
985 {OPND_VECTOR_DST_G_I, ISA_TYPE_UD|ISA_TYPE_D, GRF_ALIGNED},
986 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UD|ISA_TYPE_D, GRF_ALIGNED},
987 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UD|ISA_TYPE_D, GRF_ALIGNED},
988 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UD|ISA_TYPE_D, GRF_ALIGNED},
989 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UD|ISA_TYPE_D, GRF_ALIGNED},
990
991 },
992
993 },
994
995 /// 72
996 { ALL, ISA_BFREV, ISA_Inst_Logic, "bfrev", 4, 0,
997 {
998 {OPND_EXECSIZE, ISA_TYPE_UB, 0}, /// exec_size
999 {OPND_PRED, ISA_TYPE_UW, 0}, /// predicate
1000 {OPND_VECTOR_DST_G_I, ISA_TYPE_UD|ISA_TYPE_D, GRF_ALIGNED},
1001 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UD|ISA_TYPE_D, GRF_ALIGNED},
1002 },
1003
1004 },
1005
1006 /// 73
1007 { ALL, ISA_ADDC, ISA_Inst_Arith, "addc", 6, 0,
1008 {
1009 {OPND_EXECSIZE, ISA_TYPE_UB, 0}, /// exec_size
1010 {OPND_PRED, ISA_TYPE_UW, 0}, /// predicate
1011 {OPND_VECTOR_DST_G_I, ISA_TYPE_UD, GRF_ALIGNED},
1012 {OPND_VECTOR_DST_G_I, ISA_TYPE_UD, GRF_ALIGNED},
1013 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UD, GRF_ALIGNED},
1014 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UD, GRF_ALIGNED},
1015
1016 },
1017
1018 },
1019
1020 /// 74
1021 { ALL, ISA_SUBB, ISA_Inst_Arith, "subb", 6, 0,
1022 {
1023 {OPND_EXECSIZE, ISA_TYPE_UB, 0}, /// exec_size
1024 {OPND_PRED, ISA_TYPE_UW, 0}, /// predicate
1025 {OPND_VECTOR_DST_G_I, ISA_TYPE_UD, GRF_ALIGNED},
1026 {OPND_VECTOR_DST_G_I, ISA_TYPE_UD, GRF_ALIGNED},
1027 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UD, GRF_ALIGNED},
1028 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UD, GRF_ALIGNED},
1029
1030 },
1031
1032 },
1033
1034 /// 75
1035 { ALL, ISA_GATHER4_TYPED, ISA_Inst_Data_Port, "gather4_typed", 9, 0,
1036 {
1037 {OPND_EXECSIZE, ISA_TYPE_UB, 0}, /// exec_size
1038 {OPND_PRED, ISA_TYPE_UW, 0}, /// predicate
1039 {OPND_OTHER, ISA_TYPE_UB, 0}, /// channel mask
1040 {OPND_SURFACE, ISA_TYPE_UB, 0}, /// Surface
1041 {OPND_RAW, ISA_TYPE_UD, 0}, /// uOffset
1042 {OPND_RAW, ISA_TYPE_UD, 0}, /// vOffset
1043 {OPND_RAW, ISA_TYPE_UD, 0}, /// rOffset
1044 {OPND_RAW, ISA_TYPE_UD, 0}, /// lod
1045 {OPND_RAW, ISA_TYPE_UD|ISA_TYPE_D|ISA_TYPE_F, 0}, /// dst
1046 },
1047
1048 },
1049
1050 /// 76
1051 { ALL, ISA_SCATTER4_TYPED, ISA_Inst_Data_Port, "scatter4_typed", 9, 0,
1052 {
1053 {OPND_EXECSIZE, ISA_TYPE_UB, 0}, /// exec_size
1054 {OPND_PRED, ISA_TYPE_UW, 0}, /// predicate
1055 {OPND_OTHER, ISA_TYPE_UB, 0}, /// channel mask
1056 {OPND_SURFACE, ISA_TYPE_UB, 0}, /// Surface
1057 {OPND_RAW, ISA_TYPE_UD, 0}, /// uOffset
1058 {OPND_RAW, ISA_TYPE_UD, 0}, /// vOffset
1059 {OPND_RAW, ISA_TYPE_UD, 0}, /// rOffset
1060 {OPND_RAW, ISA_TYPE_UD, 0}, /// lod
1061 {OPND_RAW, ISA_TYPE_UD|ISA_TYPE_D|ISA_TYPE_F, 0}, /// dst
1062 },
1063
1064 },
1065
1066 /// 77
1067 { ALL, ISA_VA_SKL_PLUS, ISA_Inst_Sampler, "va_skl_plus", 1, 0,
1068 {
1069 {OPND_SUBOPCODE, ISA_TYPE_UB, 0}
1070 },
1071
1072 },
1073
1074 /// 78
1075 { ALL, ISA_SVM, ISA_Inst_SVM, "svm", 1, 0,
1076 {
1077 {OPND_SUBOPCODE, ISA_TYPE_UB, 0}
1078 },
1079
1080 },
1081
1082 /// 79
1083 { ALL, ISA_IFCALL, ISA_Inst_Flow, "ifcall", 5, 0,
1084 {
1085 { OPND_EXECSIZE, ISA_TYPE_UB, 0 },
1086 { OPND_PRED, ISA_TYPE_UW, 0 },
1087 { OPND_KIND, ISA_TYPE_UD, 0 }, /// function_addr
1088 { OPND_KIND, ISA_TYPE_UB, 0 }, /// arg_size
1089 { OPND_KIND, ISA_TYPE_UB, 0 }, /// return_size
1090 },
1091
1092 },
1093
1094 /// 80
1095 { ALL, ISA_FADDR, ISA_Inst_Flow, "faddr", 2, 0,
1096 {
1097 { OPND_KIND, ISA_TYPE_UW, 0 }, /// symbol name: index to string table
1098 { OPND_VECTOR_DST_G_I, ISA_TYPE_UD, 0 },
1099 },
1100
1101 },
1102
1103 /// 81
1104 { ALL, ISA_FILE, ISA_Inst_Misc, "file", 1, 0,
1105 {
1106 {OPND_STRING, ISA_TYPE_UD, LENGHT_LESS_256},
1107 },
1108
1109 },
1110
1111 /// 82
1112 { ALL, ISA_LOC, ISA_Inst_Misc, "loc", 1, 0,
1113 {
1114 {OPND_IMM, ISA_TYPE_UD, 0}, /// NOT finished
1115 },
1116
1117 },
1118
1119 /// 83
1120 { ALL, ISA_RESERVED_53, ISA_Inst_Reserved, "reserved_53", 0, 0,
1121 {
1122
1123 },
1124 },
1125
1126 /// 84
1127 { ALL, ISA_VME_IME, ISA_Inst_Misc, "vme_ime", 9, 0, /// VME_IME
1128 {
1129 {OPND_RAW, ISA_TYPE_UB, ELEM_NUM_96},
1130 {OPND_RAW, ISA_TYPE_UB, SIZE_STREAM_MODE_DEPENDENT_1},
1131 {OPND_STREAM_MODE, ISA_TYPE_UB, 0},
1132 {OPND_SEARCH_CRTL, ISA_TYPE_UB, 0},
1133 {OPND_SURFACE, ISA_TYPE_UB, 0},
1134 {OPND_RAW, ISA_TYPE_UW, ELEM_NUM_GE_2},
1135 {OPND_RAW, ISA_TYPE_UW, ELEM_NUM_GE_2},
1136 {OPND_RAW, ISA_TYPE_UB, ELEM_NUM_4},
1137 {OPND_RAW, ISA_TYPE_UB, SIZE_STREAM_MODE_DEPENDENT_2},
1138 },
1139
1140 },
1141
1142 /// 85
1143 { ALL, ISA_VME_SIC, ISA_Inst_Misc, "vme_sic", 4, 0, /// VME_SIC
1144 {
1145 {OPND_RAW, ISA_TYPE_UB, ELEM_NUM_96},
1146 {OPND_RAW, ISA_TYPE_UB, ELEM_NUM_128},
1147 {OPND_SURFACE, ISA_TYPE_UB, 0},
1148 {OPND_RAW, ISA_TYPE_UB, ELEM_NUM_224},
1149 },
1150
1151 },
1152
1153 /// 86
1154 { ALL, ISA_VME_FBR, ISA_Inst_Misc, "vme_fbr", 7, 0, /// VME_FBR
1155 {
1156 {OPND_RAW, ISA_TYPE_UB, ELEM_NUM_96},
1157 {OPND_RAW, ISA_TYPE_UB, ELEM_NUM_128},
1158 {OPND_SURFACE, ISA_TYPE_UB, 0},
1159 {OPND_MATRIX_MODE, ISA_TYPE_UB, 0},
1160 {OPND_SUBMATRIX_SHAPE, ISA_TYPE_UB, 0},
1161 {OPND_SUBPRE_SHAPE, ISA_TYPE_UB, 0},
1162 {OPND_RAW, ISA_TYPE_UB, ELEM_NUM_224},
1163 },
1164
1165 },
1166
1167 /// 87
1168 /// FIXME: fix ELEM_NUM type
1169 { GENX_SKL, ISA_VME_IDM, ISA_Inst_Misc, "vme_idm", 4, 0, /// VME_IDM
1170 {
1171 {OPND_RAW, ISA_TYPE_UB, ELEM_NUM_128},
1172 {OPND_RAW, ISA_TYPE_UB, ELEM_NUM_GE_32},
1173 {OPND_SURFACE, ISA_TYPE_UB, 0},
1174 {OPND_RAW, ISA_TYPE_UB, ELEM_NUM_GE_32},
1175 },
1176
1177 },
1178
1179 /// 88
1180 { ALL, ISA_RESERVED_58, ISA_Inst_Reserved, "reserved_58", 0, 0,
1181 {
1182 },
1183
1184 },
1185
1186 /// 89
1187 { ALL, ISA_BARRIER, ISA_Inst_Sync, "barrier", 0, 0,
1188 {
1189 },
1190
1191 },
1192
1193 /// 90
1194 { ALL, ISA_SAMPLR_CACHE_FLUSH, ISA_Inst_Sync, "samplr_cache_flush", 0, 0,
1195 {
1196 },
1197
1198 },
1199
1200 /// 91
1201 { ALL, ISA_WAIT, ISA_Inst_Reserved, "wait", 1, 0,
1202 {
1203 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UB, 0} // mask
1204 },
1205
1206 },
1207
1208 /// 92
1209 { ALL, ISA_FENCE, ISA_Inst_Reserved, "fence", 1, 0,
1210 {
1211 {OPND_IMM, ISA_TYPE_UB, 0}, /// mode
1212 },
1213
1214 },
1215
1216 /// 93
1217 { ALL, ISA_RAW_SEND, ISA_Inst_Misc, "raw_send", 9, 0,
1218 {
1219 {OPND_IMM, ISA_TYPE_UB, 0}, /// modifier
1220 {OPND_EXECSIZE, ISA_TYPE_UB, 0}, /// exec_size
1221 {OPND_PRED, ISA_TYPE_UW, 0}, /// predicate
1222 {OPND_IMM, ISA_TYPE_UD, 0}, /// exMsgDesc
1223 {OPND_IMM, ISA_TYPE_UB, 0}, /// numSrcs
1224 {OPND_IMM, ISA_TYPE_UB, 0}, /// numDst
1225 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UD, 0}, /// Desc
1226 {OPND_RAW, ISA_TYPE_UB, GRF_ALIGNED}, /// src
1227 {OPND_RAW, ISA_TYPE_UB, GRF_ALIGNED} /// dst
1228 },
1229
1230 },
1231
1232 /// 94
1233 { ALL, ISA_RESERVED_5E, ISA_Inst_Reserved, "reserved_5e", 0, 0,
1234 {
1235 },
1236
1237 },
1238
1239 /// 95
1240 { ALL, ISA_YIELD, ISA_Inst_Sync, "yield", 0, 0,
1241 {
1242 },
1243
1244 },
1245
1246 /// 96 (0x60)
1247 { GENX_PVC, ISA_NBARRIER, ISA_Inst_Sync, "nbarrier", 3, 0,
1248 {
1249 { OPND_IMM, ISA_TYPE_UB, 0 },
1250 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UB, 0 },
1251 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UB, 0 },
1252 },
1253 },
1254
1255 /// 97
1256 { ALL, ISA_RESERVED_61, ISA_Inst_Reserved, "reserved_61", 0, 0,
1257 {
1258 },
1259
1260 },
1261
1262 /// 98
1263 { ALL, ISA_RESERVED_62, ISA_Inst_Reserved, "reserved_62", 0, 0,
1264 {
1265 },
1266
1267 },
1268
1269 /// 99
1270 { ALL, ISA_RESERVED_63, ISA_Inst_Reserved, "reserved_63", 0, 0,
1271 {
1272 },
1273
1274 },
1275
1276 /// 100
1277 { ALL, ISA_RESERVED_64, ISA_Inst_Reserved, "reserved_64", 0, 0,
1278 {
1279 },
1280
1281 },
1282
1283 /// 101
1284 { ALL, ISA_RESERVED_65, ISA_Inst_Reserved, "reserved_65", 0, 0,
1285 {
1286 },
1287
1288 },
1289
1290 /// 102
1291 { ALL, ISA_RESERVED_66, ISA_Inst_Reserved, "reserved_66", 0, 0,
1292 {
1293 },
1294 },
1295
1296 /// 103
1297 /// minimum number of operands is 5. Argumetns are extra
1298 { ALL, ISA_FCALL, ISA_Inst_Flow, "fcall", 5, 0,
1299 {
1300 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
1301 {OPND_PRED, ISA_TYPE_UW, 0},
1302 {OPND_KIND, ISA_TYPE_UW, 0}, /// function_id
1303 {OPND_KIND, ISA_TYPE_UB, 0}, /// arg_size
1304 {OPND_KIND, ISA_TYPE_UB, 0}, /// return_size
1305 },
1306
1307 },
1308
1309 /// 104
1310 { ALL, ISA_FRET, ISA_Inst_Flow, "fret", 2, 0,
1311 {
1312 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
1313 {OPND_PRED, ISA_TYPE_UW, 0},
1314 },
1315
1316 },
1317
1318 /// 105
1319 { ALL, ISA_SWITCHJMP, ISA_Inst_Flow, "switchjmp", 4, 0, /// max size
1320 {
1321 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
1322 {OPND_IMM, ISA_TYPE_UB, 0},
1323 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_F, SCALAR_REGION},
1324 {OPND_LABEL, ISA_TYPE_UW, LABEL_BLOCK_C}, /// actual number of labels can be [1, 32]
1325 },
1326
1327 },
1328
1329 /// 106
1330 { ALL, ISA_SAD2ADD, ISA_Inst_Arith, "sad2add", 6, 0,
1331 {
1332 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
1333 {OPND_PRED, ISA_TYPE_UW, 0},
1334 {OPND_VECTOR_DST_G_I, ISA_TYPE_W | ISA_TYPE_UW, SAT_C | HORIZON_STRIDE_2},
1335 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_B | ISA_TYPE_UB, 0},
1336 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_B | ISA_TYPE_UB, 0},
1337 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_B | ISA_TYPE_UB, 0},
1338 },
1339
1340 },
1341
1342 /// 107
1343 { ALL, ISA_PLANE, ISA_Inst_Arith, "plane", 5, 0,
1344 {
1345 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
1346 {OPND_PRED, ISA_TYPE_UW, 0},
1347 {OPND_VECTOR_DST_G_I, ISA_TYPE_F, 0},
1348 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, 0},
1349 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, 0},
1350 },
1351
1352 },
1353
1354 /// 108
1355 { ALL, ISA_GOTO, ISA_Inst_SIMD_Flow, "goto", 3, 0,
1356 {
1357 {OPND_EXECSIZE, ISA_TYPE_UB, SIZE_1},
1358 {OPND_PRED, ISA_TYPE_UW, 0},
1359 {OPND_LABEL, ISA_TYPE_UW, LABEL_BLOCK_C},
1360 },
1361
1362 },
1363
1364 /// 109
1365 { ALL, ISA_3D_SAMPLE, ISA_Inst_Sampler, "3d_sample",
1366 9,
1367 0,
1368 {
1369 {OPND_OTHER, ISA_TYPE_UB, 0},
1370 {OPND_EXECSIZE, ISA_TYPE_UB, SIZE_1},
1371 {OPND_PRED, ISA_TYPE_UW, 0},
1372 {OPND_OTHER, ISA_TYPE_UB, 0}, /// Channel
1373 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_UD, SCALAR_REGION}, /// aoffimmi
1374 {OPND_SAMPLE, ISA_TYPE_UB, 0}, /// Sampler
1375 {OPND_SURFACE, ISA_TYPE_UB, 0}, /// Surface
1376 {OPND_RAW, ISA_TYPE_F, GRF_ALIGNED}, /// Destination
1377 {OPND_OTHER, ISA_TYPE_UB, 0}, /// numberMsgSpecific Operands
1378 },
1379
1380 },
1381
1382 /// 110
1383 { ALL, ISA_3D_LOAD, ISA_Inst_Sampler, "3d_load",
1384 8,
1385 0,
1386 {
1387 {OPND_OTHER, ISA_TYPE_UB, 0},
1388 {OPND_EXECSIZE, ISA_TYPE_UB, SIZE_1},
1389 {OPND_PRED, ISA_TYPE_UW, 0},
1390 {OPND_OTHER, ISA_TYPE_UB, 0}, /// Channel
1391 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_UD, SCALAR_REGION}, /// aoffimmi
1392 {OPND_SURFACE, ISA_TYPE_UB, 0}, /// Surface
1393 {OPND_RAW, ISA_TYPE_F | ISA_TYPE_UD | ISA_TYPE_D, 0}, /// Destination
1394 {OPND_OTHER, ISA_TYPE_UB, 0}, /// numberMsgSpecific Operands
1395 },
1396
1397 },
1398
1399 /// 111
1400 { ALL, ISA_3D_GATHER4, ISA_Inst_Sampler, "3d_gather4",
1401 9,
1402 0,
1403 {
1404 {OPND_OTHER, ISA_TYPE_UB, 0},
1405 {OPND_EXECSIZE, ISA_TYPE_UB, SIZE_1},
1406 {OPND_PRED, ISA_TYPE_UW, 0},
1407 {OPND_OTHER, ISA_TYPE_UB, 0}, /// Channel
1408 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_UD, SCALAR_REGION}, /// aoffimmi
1409 {OPND_SAMPLE, ISA_TYPE_UB, 0}, /// Sampler
1410 {OPND_SURFACE, ISA_TYPE_UB, 0}, /// Surface
1411 {OPND_RAW, ISA_TYPE_F | ISA_TYPE_UD | ISA_TYPE_D, 0}, /// Destination
1412 {OPND_OTHER, ISA_TYPE_UB, 0}, /// numberMsgSpecific Operands
1413 },
1414
1415 },
1416
1417 /// 112
1418 { ALL, ISA_3D_INFO, ISA_Inst_Sampler, "3d_info", 5, 0,
1419 {
1420 {OPND_OTHER, ISA_TYPE_UB, 0}, /// subOpcode
1421 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
1422 {OPND_OTHER, ISA_TYPE_UB, 0 },
1423 {OPND_SURFACE, ISA_TYPE_UB, 0}, /// Surface
1424 { OPND_RAW, ISA_TYPE_UD, 0 }, /// LOD
1425 //LOD is only for one of the opcodes, it will be handled in the builder interface, and operand number incremented.
1426 {OPND_RAW, ISA_TYPE_UD, 0} /// dst
1427 },
1428
1429 },
1430
1431 /// 113
1432 { ALL, ISA_3D_RT_WRITE, ISA_Inst_Sampler, "3d_rt_write", 4, 0,
1433 {
1434 {OPND_EXECSIZE, ISA_TYPE_UB, SIZE_1},
1435 {OPND_PRED, ISA_TYPE_UW, 0}, ///predicate
1436 {OPND_OTHER, ISA_TYPE_UW, 0}, /// mode
1437 {OPND_SURFACE, ISA_TYPE_UB, 0}, /// Surface
1438 },
1439
1440 },
1441
1442 /// 114
1443 { ALL, ISA_3D_URB_WRITE, ISA_Inst_Sampler, "3d_urb_write", 8, 0,
1444 {
1445 {OPND_EXECSIZE, ISA_TYPE_UB, SIZE_1},
1446 {OPND_PRED, ISA_TYPE_UW, 0},
1447 {OPND_OTHER, ISA_TYPE_UB, 0}, /// number of output parameters
1448 {OPND_RAW, ISA_TYPE_UD, 0}, /// channel mask
1449 {OPND_OTHER, ISA_TYPE_UW, 0}, /// global offset
1450 {OPND_RAW, ISA_TYPE_UD, 0}, /// URB Handle
1451 {OPND_RAW, ISA_TYPE_UD, 0}, /// per slot offset
1452 {OPND_RAW, ISA_TYPE_UD | ISA_TYPE_D | ISA_TYPE_F, 0} /// vertex data
1453 },
1454
1455 },
1456
1457 /// 115
1458 { ALL, ISA_3D_TYPED_ATOMIC, ISA_Inst_Data_Port, "typed_atomic", 11, 0,
1459 {
1460 {OPND_OTHER, ISA_TYPE_UB, 0}, /// sub opcode
1461 {OPND_EXECSIZE, ISA_TYPE_UB, SIZE_1},
1462 {OPND_PRED, ISA_TYPE_UW, 0},
1463 {OPND_SURFACE, ISA_TYPE_UB, 0}, /// Surface
1464 {OPND_RAW, ISA_TYPE_UD, 0}, /// U
1465 {OPND_RAW, ISA_TYPE_UD, 0}, /// V
1466 {OPND_RAW, ISA_TYPE_UD, 0}, /// R
1467 {OPND_RAW, ISA_TYPE_UD, 0}, /// LOD
1468 {OPND_RAW, ISA_TYPE_UD, 0}, /// Src0
1469 {OPND_RAW, ISA_TYPE_UD, 0}, /// Src1
1470 {OPND_RAW, ISA_TYPE_UD | ISA_TYPE_D, 0} /// dst
1471 },
1472
1473 },
1474
1475 /// 116
1476 {
1477 ALL, ISA_GATHER4_SCALED, ISA_Inst_Data_Port, "gather4_scaled", 8, 0,
1478 {
1479 {OPND_EXECSIZE, ISA_TYPE_UB, 0}, /// execution size
1480 {OPND_PRED, ISA_TYPE_UW, 0}, /// predicate
1481 {OPND_OTHER, ISA_TYPE_UB, 0}, /// channel mask
1482 {OPND_OTHER, ISA_TYPE_UW, 0}, /// scale
1483 {OPND_SURFACE, ISA_TYPE_UB, 0}, /// surface
1484 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UD, SCALAR_REGION}, /// global offset
1485 {OPND_RAW, ISA_TYPE_UD, GRF_ALIGNED}, /// offsets
1486 {OPND_RAW, ISA_TYPE_F |
1487 ISA_TYPE_D |
1488 ISA_TYPE_UD, GRF_ALIGNED} /// dst
1489 },
1490
1491 },
1492
1493 /// 117
1494 {
1495 ALL, ISA_SCATTER4_SCALED, ISA_Inst_Data_Port, "scatter4_scaled", 8, 0,
1496 {
1497 {OPND_EXECSIZE, ISA_TYPE_UB, 0}, /// execution size
1498 {OPND_PRED, ISA_TYPE_UW, 0}, /// predicate
1499 {OPND_OTHER, ISA_TYPE_UB, 0}, /// channel mask
1500 {OPND_OTHER, ISA_TYPE_UW, 0}, /// scale
1501 {OPND_SURFACE, ISA_TYPE_UB, 0}, /// surface
1502 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UD, SCALAR_REGION}, /// global offset
1503 {OPND_RAW, ISA_TYPE_UD, GRF_ALIGNED}, /// offsets
1504 {OPND_RAW, ISA_TYPE_F |
1505 ISA_TYPE_D |
1506 ISA_TYPE_UD, GRF_ALIGNED} /// dst
1507 },
1508
1509 },
1510
1511 /// 118
1512 { ALL, ISA_RESERVED_76, ISA_Inst_Reserved, "reserved_76", 0, 0,
1513 {
1514 },
1515
1516 },
1517
1518 /// 119
1519 { ALL, ISA_RESERVED_77, ISA_Inst_Reserved, "reserved_77", 0, 0,
1520 {
1521 },
1522
1523 },
1524
1525 /// 120 (0x78)
1526 {
1527 ALL, ISA_GATHER_SCALED, ISA_Inst_Data_Port, "gather_scaled", 9, 0,
1528 {
1529 {OPND_EXECSIZE, ISA_TYPE_UB, 0}, /// execution size
1530 {OPND_PRED, ISA_TYPE_UW, 0}, /// predicate
1531 {OPND_OTHER, ISA_TYPE_UB, 0}, /// block size
1532 {OPND_OTHER, ISA_TYPE_UB, 0}, /// num of blocks
1533 {OPND_OTHER, ISA_TYPE_UW, 0}, /// scale
1534 {OPND_SURFACE, ISA_TYPE_UB, 0}, /// surface
1535 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UD, SCALAR_REGION}, /// global offset
1536 {OPND_RAW, ISA_TYPE_UD, GRF_ALIGNED}, /// offsets
1537 {OPND_RAW, ISA_TYPE_F |
1538 ISA_TYPE_D |
1539 ISA_TYPE_UD, GRF_ALIGNED} /// dst
1540 },
1541
1542 },
1543
1544 /// 121 (0x79)
1545 {
1546 ALL, ISA_SCATTER_SCALED, ISA_Inst_Data_Port, "scatter_scaled", 9, 0,
1547 {
1548 {OPND_EXECSIZE, ISA_TYPE_UB, 0}, /// execution size
1549 {OPND_PRED, ISA_TYPE_UW, 0}, /// predicate
1550 {OPND_OTHER, ISA_TYPE_UB, 0}, /// block size
1551 {OPND_OTHER, ISA_TYPE_UB, 0}, /// num of blocks
1552 {OPND_OTHER, ISA_TYPE_UW, 0}, /// scale
1553 {OPND_SURFACE, ISA_TYPE_UB, 0}, /// surface
1554 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UD, SCALAR_REGION}, /// global offset
1555 {OPND_RAW, ISA_TYPE_UD, GRF_ALIGNED}, /// offsets
1556 {OPND_RAW, ISA_TYPE_F |
1557 ISA_TYPE_D |
1558 ISA_TYPE_UD, GRF_ALIGNED} /// dst
1559 },
1560
1561 },
1562
1563 /// 122
1564 { ALL, ISA_RAW_SENDS, ISA_Inst_Misc, "raw_sends", 12, 0,
1565 {
1566 {OPND_IMM, ISA_TYPE_UB, 0}, /// modifier
1567 {OPND_EXECSIZE, ISA_TYPE_UB, 0}, /// exec_size
1568 {OPND_PRED, ISA_TYPE_UW, 0}, /// predicate
1569 {OPND_IMM, ISA_TYPE_UB, 0}, /// numSrc0
1570 {OPND_IMM, ISA_TYPE_UB, 0}, /// numSrc1
1571 {OPND_IMM, ISA_TYPE_UB, 0}, /// numDst
1572 {OPND_IMM, ISA_TYPE_UB, 0}, /// FFID
1573 {OPND_IMM, ISA_TYPE_UD, 0}, /// exMsgDesc
1574 {OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UD, 0}, /// Desc
1575 {OPND_RAW, ISA_TYPE_UB, GRF_ALIGNED}, /// src0
1576 {OPND_RAW, ISA_TYPE_UB, GRF_ALIGNED}, /// src1
1577 {OPND_RAW, ISA_TYPE_UB, GRF_ALIGNED} /// dst
1578 },
1579
1580 },
1581
1582 /// 123 (0x7B)
1583 { ALL, ISA_LIFETIME, ISA_Inst_Misc, "lifetime", 2, 0,
1584 {
1585 {OPND_IMM, ISA_TYPE_UB, 0}, // properties
1586 {OPND_IMM, ISA_TYPE_UD, 0} // variable id
1587 },
1588 },
1589
1590
1591 /// 124 (0x7C)
1592 {
1593 ALL, ISA_SBARRIER, ISA_Inst_Sync, "sbarrier", 1, 0,
1594 {
1595 {OPND_IMM, ISA_TYPE_UB, 0}, // signal/wait
1596 },
1597
1598 },
1599
1600 /// 125 (0x7D)
1601 {
1602 ALL, ISA_DWORD_ATOMIC, ISA_Inst_Data_Port, "dword_atomic", 8, 0,
1603 {
1604 {OPND_ATOMIC_SUBOP, ISA_TYPE_UB, 0},
1605 {OPND_EXECSIZE, ISA_TYPE_UB, 0}, /// execution size
1606 {OPND_PRED, ISA_TYPE_UW, 0}, /// predicate
1607 {OPND_SURFACE, ISA_TYPE_UB, 0},
1608 {OPND_RAW, ISA_TYPE_UD, GRF_ALIGNED},
1609 {OPND_RAW, ISA_TYPE_D |
1610 ISA_TYPE_F |
1611 ISA_TYPE_UD, GRF_ALIGNED},
1612 {OPND_RAW, ISA_TYPE_D |
1613 ISA_TYPE_F |
1614 ISA_TYPE_UD, GRF_ALIGNED},
1615 {OPND_RAW, ISA_TYPE_D |
1616 ISA_TYPE_F |
1617 ISA_TYPE_UD, GRF_ALIGNED},
1618 },
1619
1620 },
1621
1622 /// 126 (0x7E)
1623 { ALL, ISA_SQRTM, ISA_Inst_Arith, "sqrtm", 4, SAME_DATA_TYPE,
1624 {
1625 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
1626 {OPND_PRED, ISA_TYPE_UW, 0},
1627 {OPND_VECTOR_DST_G_I, ISA_TYPE_DF, SAT_C},
1628 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_DF, 0},
1629 },
1630
1631 },
1632
1633 /// 127 (0x7F)
1634 { ALL, ISA_DIVM, ISA_Inst_Arith, "divm", 5, SAME_DATA_TYPE,
1635 {
1636 { OPND_EXECSIZE, ISA_TYPE_UB, 0 },
1637 { OPND_PRED, ISA_TYPE_UW, 0 },
1638 { OPND_VECTOR_DST_G_I, TYPE_FLOAT, SAT_FLOAT_ONLY },
1639 { OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT, 0 },
1640 { OPND_VECTOR_SRC_G_I_IMM_AO, TYPE_FLOAT, 0 },
1641 },
1642 },
1643
1644 /// 128 (0x80)
1645 { GENX_ICLLP, ISA_ROL, ISA_Inst_Logic, "rol", 5, SAME_DATA_TYPE,
1646 {
1647 { OPND_EXECSIZE, ISA_TYPE_UB, 0 },
1648 { OPND_PRED, ISA_TYPE_UW, 0 },
1649 { OPND_VECTOR_DST_G_I, ISA_TYPE_W|ISA_TYPE_UW|ISA_TYPE_D|ISA_TYPE_UD, 0 },
1650 { OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_W | ISA_TYPE_UW | ISA_TYPE_D | ISA_TYPE_UD, 0 },
1651 { OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_W | ISA_TYPE_UW | ISA_TYPE_D | ISA_TYPE_UD, 0 },
1652 },
1653 },
1654
1655 /// 129 (0x81)
1656 { GENX_ICLLP, ISA_ROR, ISA_Inst_Logic, "ror", 5, SAME_DATA_TYPE,
1657 {
1658 { OPND_EXECSIZE, ISA_TYPE_UB, 0 },
1659 { OPND_PRED, ISA_TYPE_UW, 0 },
1660 { OPND_VECTOR_DST_G_I, ISA_TYPE_W | ISA_TYPE_UW | ISA_TYPE_D | ISA_TYPE_UD, 0 },
1661 { OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_W | ISA_TYPE_UW | ISA_TYPE_D | ISA_TYPE_UD, 0 },
1662 { OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_W | ISA_TYPE_UW | ISA_TYPE_D | ISA_TYPE_UD, 0 },
1663 },
1664 },
1665
1666 /// 130 (0x82)
1667 { GENX_TGLLP, ISA_DP4A, ISA_Inst_Arith, "dp4a", 6, SAME_DATA_TYPE,
1668 {
1669 { OPND_EXECSIZE, ISA_TYPE_UB, 0 },
1670 { OPND_PRED, ISA_TYPE_UW, 0 },
1671 { OPND_VECTOR_DST_G_I, ISA_TYPE_D | ISA_TYPE_UD, 0 },
1672 { OPND_VECTOR_SRC_G_I, ISA_TYPE_D | ISA_TYPE_UD, 0 },
1673 { OPND_VECTOR_SRC_G_I, ISA_TYPE_D | ISA_TYPE_UD, 0 },
1674 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_D | ISA_TYPE_UD, 0 },
1675 },
1676 },
1677
1678 /// 131 (0x83)
1679 { XeHP_SDV, ISA_DPAS, ISA_Inst_Misc, "dpas", 6, SAME_DATA_TYPE,
1680 {
1681 { OPND_EXECSIZE, ISA_TYPE_UB, 0 },
1682 { OPND_DST_GEN, ISA_TYPE_D | ISA_TYPE_UD | ISA_TYPE_F, GRF_ALIGNED },
1683 { OPND_SRC_GEN, ISA_TYPE_D | ISA_TYPE_UD | ISA_TYPE_F, GRF_ALIGNED },
1684 { OPND_SRC_GEN, ISA_TYPE_D | ISA_TYPE_UD, GRF_ALIGNED },
1685 { OPND_SRC_GEN, ISA_TYPE_D | ISA_TYPE_UD, GRF_ALIGNED },
1686 { OPND_OTHER, ISA_TYPE_UD, 0}
1687 },
1688 },
1689
1690 /// 132 (0x84)
1691 { ALL, ISA_ADD3, ISA_Inst_Arith, "add3", 6, SAME_DATA_TYPE,
1692 {
1693 { OPND_EXECSIZE, ISA_TYPE_UB, 0 },
1694 { OPND_PRED, ISA_TYPE_UW, 0 },
1695 { OPND_VECTOR_DST_G_I, ISA_TYPE_W | ISA_TYPE_UW | ISA_TYPE_D | ISA_TYPE_UD, 0 },
1696 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_W | ISA_TYPE_UW | ISA_TYPE_D | ISA_TYPE_UD, 0 },
1697 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_W | ISA_TYPE_UW | ISA_TYPE_D | ISA_TYPE_UD, 0 },
1698 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_W | ISA_TYPE_UW | ISA_TYPE_D | ISA_TYPE_UD, 0 },
1699 },
1700 },
1701
1702 // 133 (0x85)
1703 { ALL, ISA_BFN, ISA_Inst_Logic, "bfn", 7, SAME_DATA_TYPE,
1704 {
1705 { OPND_EXECSIZE, ISA_TYPE_UB, 0 },
1706 { OPND_PRED, ISA_TYPE_UW, 0 },
1707 { OPND_VECTOR_DST_G_I, ISA_TYPE_W | ISA_TYPE_UW | ISA_TYPE_D | ISA_TYPE_UD, 0 }, // dst
1708 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_W | ISA_TYPE_UW | ISA_TYPE_D | ISA_TYPE_UD, 0 }, // src0: reg | imm16
1709 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_W | ISA_TYPE_UW | ISA_TYPE_D | ISA_TYPE_UD, 0 }, // src1: reg
1710 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_W | ISA_TYPE_UW | ISA_TYPE_D | ISA_TYPE_UD, 0 }, // src2: reg | imm16
1711 { OPND_OTHER, ISA_TYPE_UB, 0 } // BooleanFuncCtrl, must be the last opend
1712 },
1713 },
1714
1715 /// 134 (0x86)
1716 { XeHP_SDV, ISA_QW_GATHER, ISA_Inst_Data_Port, "qw_gather", 6, 0,
1717 {
1718 { OPND_EXECSIZE, ISA_TYPE_UB, 0 }, /// execution size
1719 { OPND_PRED, ISA_TYPE_UW, 0 }, /// predicate
1720 { OPND_OTHER, ISA_TYPE_UB, 0 }, /// numBlocks
1721 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// surface
1722 { OPND_RAW, ISA_TYPE_UD, GRF_ALIGNED }, /// offsets
1723 { OPND_RAW, ISA_TYPE_DF | ISA_TYPE_UQ, GRF_ALIGNED } /// dst
1724 },
1725 },
1726
1727 /// 135 (0x87)
1728 { XeHP_SDV, ISA_QW_SCATTER, ISA_Inst_Data_Port, "qw_scatter", 6, 0,
1729 {
1730 { OPND_EXECSIZE, ISA_TYPE_UB, 0 }, /// execution size
1731 { OPND_PRED, ISA_TYPE_UW, 0 }, /// predicate
1732 { OPND_OTHER, ISA_TYPE_UB, 0 }, /// numBlocks
1733 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// surface
1734 { OPND_RAW, ISA_TYPE_UD, GRF_ALIGNED }, /// offsets
1735 { OPND_RAW, ISA_TYPE_DF | ISA_TYPE_UQ, GRF_ALIGNED } /// src
1736 },
1737 },
1738
1739 /// 136 (0x88)
1740 { XeHP_SDV, ISA_BF_CVT, ISA_Inst_Mov, "bf_cvt", 3, SAME_SPECIAL_KIND,
1741 {
1742 { OPND_EXECSIZE, ISA_TYPE_UB, 0 },
1743 { OPND_DST_GEN, ISA_TYPE_F, 0 },
1744 { OPND_SRC_GEN, ISA_TYPE_HF, 0 },
1745 },
1746 },
1747 /// 137 (0x89)
1748 { GENX_DG2, ISA_LSC_UNTYPED, ISA_Inst_LSC, "lsc_untyped", 1, SAME_SPECIAL_KIND,
1749 {
1750 {OPND_SUBOPCODE, ISA_TYPE_UB, 0}
1751 },
1752 },
1753 /// 138 (0x8A)
1754 { GENX_DG2, ISA_LSC_TYPED, ISA_Inst_LSC, "lsc_typed", 1, SAME_SPECIAL_KIND,
1755 {
1756 {OPND_SUBOPCODE, ISA_TYPE_UB, 0}
1757 },
1758 },
1759 /// 139 (0x8B)
1760 { GENX_DG2, ISA_LSC_FENCE, ISA_Inst_LSC, "lsc_fence", 5, 0,
1761 {
1762 /* execution control */
1763 {OPND_EXECSIZE, ISA_TYPE_UB, 0}, /* execution size */
1764 {OPND_PRED, ISA_TYPE_UW, 0}, /* predicate */
1765 /* caching opts */
1766 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_SFID */
1767 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_FENCE_OP */
1768 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_SCOPE */
1769 }
1770 },
1771 /// 140 (0x8C)
1772 { ALL, ISA_RESERVED_8C, ISA_Inst_Reserved, "reserved_8c", 0, 0,
1773 {
1774 },
1775 },
1776
1777 /// 141 (0x8D)
1778 { ALL, ISA_RESERVED_8D, ISA_Inst_Reserved, "reserved_8d", 0, 0,
1779 {
1780 },
1781 },
1782
1783 /// 142 (0x8E)
1784 { ALL, ISA_RESERVED_8E, ISA_Inst_Reserved, "reserved_8e", 0, 0,
1785 {
1786 },
1787 },
1788 /// 143 (0x8F)
1789 { ALL, ISA_RESERVED_8F, ISA_Inst_Reserved, "reserved_8f", 0, 0,
1790 {
1791 },
1792 },
1793
1794 /// 144 (0x90)
1795 { ALL, ISA_RESERVED_90, ISA_Inst_Reserved, "reserved_90", 0, 0,
1796 {
1797 },
1798 },
1799
1800 /// 145 (0x91)
1801 { ALL, ISA_MADW, ISA_Inst_Arith, "madw", 6, SAME_DATA_TYPE,
1802 {
1803 {OPND_EXECSIZE, ISA_TYPE_UB, 0},
1804 {OPND_PRED, ISA_TYPE_UW, 0},
1805 {OPND_VECTOR_DST_G_I, ISA_TYPE_UD | ISA_TYPE_D, 0},
1806 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_UD | ISA_TYPE_D, 0},
1807 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_UD | ISA_TYPE_D, 0},
1808 {OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_UD | ISA_TYPE_D, 0},
1809 },
1810 },
1811
1812 /// 146 (0x92)
1813 { ALL, ISA_ADD3O, ISA_Inst_Arith, "add3.o", 6, SAME_DATA_TYPE,
1814 {
1815 { OPND_EXECSIZE, ISA_TYPE_UB, 0 },
1816 { OPND_PRED, ISA_TYPE_UW, 0 },
1817 { OPND_VECTOR_DST_G_I, ISA_TYPE_W | ISA_TYPE_UW | ISA_TYPE_D | ISA_TYPE_UD, 0 },
1818 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_W | ISA_TYPE_UW | ISA_TYPE_D | ISA_TYPE_UD, 0 },
1819 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_W | ISA_TYPE_UW | ISA_TYPE_D | ISA_TYPE_UD, 0 },
1820 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_W | ISA_TYPE_UW | ISA_TYPE_D | ISA_TYPE_UD, 0 },
1821 },
1822 },
1823 };
1824
1825 static const ISA_SubInst_Desc VASubOpcodeDesc[] =
1826 {
1827 {}, /// AVS subOpcode
1828 { Convolve_FOPCODE, ISA_Inst_Sampler, "va_convolve_2d", 6,
1829 {
1830 { OPND_SAMPLE, ISA_TYPE_UB, 0 }, /// Sampler
1831 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// Surface
1832 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //uOffset
1833 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //vOffset
1834 { OPND_OTHER, ISA_TYPE_UB, 0 }, //properties
1835 { OPND_RAW, ISA_TYPE_F, GRF_ALIGNED }, //dst
1836 }
1837 },
1838 { MINMAX_FOPCODE, ISA_Inst_Sampler, "va_minmax", 5,
1839 {
1840 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// Surface
1841 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //uOffset
1842 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //vOffset
1843 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UB, 0 }, //mmfMode
1844 { OPND_RAW, ISA_TYPE_F, GRF_ALIGNED }, //dst
1845 }
1846 },
1847 { MINMAXFILTER_FOPCODE, ISA_Inst_Sampler, "va_minmaxfilter", 8,
1848 {
1849 { OPND_SAMPLE, ISA_TYPE_UB, 0 }, /// Sampler
1850 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// Surface
1851 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //uOffset
1852 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //vOffset
1853 { OPND_OTHER, ISA_TYPE_UB, 0 }, //cntrl
1854 { OPND_OTHER, ISA_TYPE_UB, 0 }, //execMode
1855 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UB, 0 }, //mmfMode
1856 { OPND_RAW, ISA_TYPE_F, GRF_ALIGNED }, //dst
1857 }
1858 },
1859 { ERODE_FOPCODE, ISA_Inst_Sampler, "va_erode", 6,
1860 {
1861 { OPND_SAMPLE, ISA_TYPE_UB, 0 }, /// Sampler
1862 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// Surface
1863 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //uOffset
1864 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //vOffset
1865 { OPND_OTHER, ISA_TYPE_UB, 0 }, //execMode
1866 { OPND_RAW, ISA_TYPE_F, GRF_ALIGNED }, //dst
1867 }
1868 },
1869 { Dilate_FOPCODE, ISA_Inst_Sampler, "va_dilate", 6,
1870 {
1871 { OPND_SAMPLE, ISA_TYPE_UB, 0 }, /// Sampler
1872 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// Surface
1873 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //uOffset
1874 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //vOffset
1875 { OPND_OTHER, ISA_TYPE_UB, 0 }, //execMode
1876 { OPND_RAW, ISA_TYPE_F, GRF_ALIGNED }, //dst
1877 }
1878 },
1879 { BoolCentroid_FOPCODE, ISA_Inst_Sampler, "va_boolcentroid", 6,
1880 {
1881 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// Surface
1882 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //uOffset
1883 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //vOffset
1884 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UB, SCALAR_REGION }, //vSize
1885 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UB, SCALAR_REGION }, //hSize
1886 { OPND_RAW, ISA_TYPE_F, GRF_ALIGNED }, //dst
1887 }
1888 },
1889 { Centroid_FOPCODE, ISA_Inst_Sampler, "va_centroid", 5,
1890 {
1891 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// Surface
1892 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //uOffset
1893 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //vOffset
1894 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UB, SCALAR_REGION }, //vSize
1895 { OPND_RAW, ISA_TYPE_F, GRF_ALIGNED }, //dst
1896 }
1897 },
1898 };
1899
1900 static const ISA_SubInst_Desc VAPlusSubOpcodeDesc[] =
1901 {
1902 {}, /// AVS subOpcode
1903 {}, //convolve
1904 {}, //minmax
1905 {}, //minmaxfilter
1906 {}, //erode
1907 {}, //dilate
1908 {}, //boolCentroid
1909 {}, //centroid
1910 { VA_OP_CODE_1D_CONVOLVE_VERTICAL, ISA_Inst_Sampler, "va_convolve_1d_v", 6,
1911 {
1912 { OPND_SAMPLE, ISA_TYPE_UB, 0 }, /// Sampler
1913 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// Surface
1914 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //uOffset
1915 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //vOffset
1916 { OPND_OTHER, ISA_TYPE_UB, 0 }, //mode
1917 { OPND_RAW_DST, ISA_TYPE_W, GRF_ALIGNED }, //dst
1918 }
1919 },
1920 { VA_OP_CODE_1D_CONVOLVE_HORIZONTAL, ISA_Inst_Sampler, "va_convolve_1d_h", 6,
1921 {
1922 { OPND_SAMPLE, ISA_TYPE_UB, 0 }, /// Sampler
1923 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// Surface
1924 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //uOffset
1925 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //vOffset
1926 { OPND_OTHER, ISA_TYPE_UB, 0 }, //mode
1927 { OPND_RAW_DST, ISA_TYPE_W, GRF_ALIGNED }, //dst
1928 }
1929 },
1930 { VA_OP_CODE_1PIXEL_CONVOLVE, ISA_Inst_Sampler, "va_convolve_1pixel", 7,
1931 {
1932 { OPND_SAMPLE, ISA_TYPE_UB, 0 }, /// Sampler
1933 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// Surface
1934 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //uOffset
1935 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //vOffset
1936 { OPND_OTHER, ISA_TYPE_UB, 0 }, //mode
1937 { OPND_RAW_SRC, ISA_TYPE_W, GRF_ALIGNED }, //offset
1938 { OPND_RAW_DST, ISA_TYPE_W, GRF_ALIGNED }, //dst
1939 }
1940 },
1941 { VA_OP_CODE_FLOOD_FILL, ISA_Inst_Sampler, "va_floodfill", 6,
1942 {
1943 { OPND_OTHER, ISA_TYPE_UB, 0 }, //is8Connect
1944 { OPND_RAW_SRC, ISA_TYPE_W, GRF_ALIGNED }, //PixelMaskHDirection
1945 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //PixelMaskVDirectionLeft
1946 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //PixelMaskVDirectionRight
1947 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //LoopCount
1948 { OPND_RAW_DST, ISA_TYPE_W, GRF_ALIGNED }, //dst
1949 }
1950 },
1951 { VA_OP_CODE_LBP_CREATION, ISA_Inst_Sampler, "va_lbpcreation", 5,
1952 {
1953 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// Surface
1954 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //uOffset
1955 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //vOffset
1956 { OPND_OTHER, ISA_TYPE_UB, 0 }, //mode
1957 { OPND_RAW_DST, ISA_TYPE_UB, GRF_ALIGNED }, //dst
1958 }
1959 },
1960 { VA_OP_CODE_LBP_CORRELATION, ISA_Inst_Sampler, "va_lbpcorrelation", 5,
1961 {
1962 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// Surface
1963 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //uOffset
1964 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //vOffset
1965 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_W, SCALAR_REGION }, //disparity
1966 { OPND_RAW_DST, ISA_TYPE_W, GRF_ALIGNED }, //dst
1967 }
1968 },
1969 {}, //none
1970 { VA_OP_CODE_CORRELATION_SEARCH, ISA_Inst_Sampler, "va_correlationsearch", 10,
1971 {
1972 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// Surface
1973 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //uOffset
1974 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //vOffset
1975 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //verticalOrigin
1976 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //horizontalOrigin
1977 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UB, SCALAR_REGION }, //xDirectionSize
1978 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UB, SCALAR_REGION }, //yDirectionSize
1979 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UB, SCALAR_REGION }, //xDirectionSearchSize
1980 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UB, SCALAR_REGION }, //yDirectionSearchSize
1981 { OPND_RAW_DST, ISA_TYPE_UD, GRF_ALIGNED }, //dst
1982 }
1983 },
1984 { ISA_HDC_CONV, ISA_Inst_Sampler, "va_hdc_convolve_2d", 8,
1985 {
1986 { OPND_SAMPLE, ISA_TYPE_UB, 0 }, /// Sampler
1987 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// Surface
1988 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //uOffset
1989 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //vOffset
1990 { OPND_OTHER, ISA_TYPE_UB, 0 }, /// Properties
1991 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// dstSurface
1992 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UW, SCALAR_REGION }, //dstXOffset
1993 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UW, SCALAR_REGION }, //dstYOffset
1994 }
1995 },
1996 { ISA_HDC_MMF, ISA_Inst_Sampler, "va_hdc_minmaxfilter", 9,
1997 {
1998 { OPND_SAMPLE, ISA_TYPE_UB, 0 }, /// Sampler
1999 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// Surface
2000 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //uOffset
2001 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //vOffset
2002 { OPND_OTHER, ISA_TYPE_UB, 0 }, /// pixelSize
2003 { OPND_OTHER, ISA_TYPE_UB, 0 }, /// mmfMode
2004 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// dstSurface
2005 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UW, SCALAR_REGION }, //dstXOffset
2006 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UW, SCALAR_REGION }, //dstYOffset
2007 }
2008 },
2009 { ISA_HDC_ERODE, ISA_Inst_Sampler, "va_hdc_erode", 7,
2010 {
2011 { OPND_SAMPLE, ISA_TYPE_UB, 0 }, /// Sampler
2012 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// Surface
2013 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //uOffset
2014 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //vOffset
2015 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// dstSurface
2016 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UW, SCALAR_REGION }, //dstXOffset
2017 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UW, SCALAR_REGION }, //dstYOffset
2018 }
2019 },
2020 { ISA_HDC_DILATE, ISA_Inst_Sampler, "va_hdc_dilate", 7,
2021 {
2022 { OPND_SAMPLE, ISA_TYPE_UB, 0 }, /// Sampler
2023 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// Surface
2024 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //uOffset
2025 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //vOffset
2026 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// dstSurface
2027 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UW, SCALAR_REGION }, //dstXOffset
2028 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UW, SCALAR_REGION }, //dstYOffset
2029 }
2030 },
2031 { ISA_HDC_LBPCORRELATION, ISA_Inst_Sampler, "va_hdc_lbpcorrelation", 7,
2032 {
2033 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// Surface
2034 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //uOffset
2035 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //vOffset
2036 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_W, SCALAR_REGION }, //disparity
2037 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// dstSurface
2038 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UW, SCALAR_REGION }, //dstXOffset
2039 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UW, SCALAR_REGION }, //dstYOffset
2040 }
2041 },
2042 { ISA_HDC_LBPCREATION, ISA_Inst_Sampler, "va_hdc_lbpcreation", 7,
2043 {
2044 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// Surface
2045 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //uOffset
2046 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, //vOffset
2047 { OPND_OTHER, ISA_TYPE_UB, 0 }, /// mode
2048 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// dstSurface
2049 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UW, SCALAR_REGION }, //dstXOffset
2050 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UW, SCALAR_REGION }, //dstYOffset
2051 }
2052 },
2053 { ISA_HDC_1DCONV_H, ISA_Inst_Sampler, "va_hdc_convolve_1d_h", 8,
2054 {
2055 { OPND_SAMPLE, ISA_TYPE_UB, 0 }, /// Sampler
2056 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// Surface
2057 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, // uOffset
2058 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, // vOffset
2059 { OPND_OTHER, ISA_TYPE_UB, 0 }, /// pixelSize
2060 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// dstSurface
2061 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UW, SCALAR_REGION }, // dstXOffset
2062 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UW, SCALAR_REGION }, // dstYOffset
2063 }
2064 },
2065 { ISA_HDC_1DCONV_V, ISA_Inst_Sampler, "va_hdc_convolve_1d_v", 8,
2066 {
2067 { OPND_SAMPLE, ISA_TYPE_UB, 0 }, /// Sampler
2068 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// Surface
2069 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, // uOffset
2070 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, // vOffset
2071 { OPND_OTHER, ISA_TYPE_UB, 0 }, /// pixelSize
2072 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// dstSurface
2073 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UW, SCALAR_REGION }, // dstXOffset
2074 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UW, SCALAR_REGION }, // dstYOffset
2075 }
2076 },
2077 { ISA_HDC_1PIXELCONV, ISA_Inst_Sampler, "va_hdc_convolve_1pixel", 9,
2078 {
2079 { OPND_SAMPLE, ISA_TYPE_UB, 0 }, /// Sampler
2080 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// Surface
2081 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, // uOffset
2082 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_F, SCALAR_REGION }, // vOffset
2083 { OPND_OTHER, ISA_TYPE_UB, 0 }, /// pixelSize
2084 { OPND_RAW_SRC, ISA_TYPE_W, GRF_ALIGNED }, // offsets
2085 { OPND_SURFACE, ISA_TYPE_UB, 0 }, /// dstSurface
2086 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UW, SCALAR_REGION }, // dstXOffset
2087 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UW, SCALAR_REGION }, // dstYOffset
2088 }
2089 },
2090 };
2091
2092 static const ISA_SubInst_Desc SVMSubOpcodeDesc[] =
2093 {
2094 {}, /// 0th entry
2095 { SVM_BLOCK_LD, ISA_Inst_SVM, "svm_block_ld", 3,
2096 { { OPND_OTHER, ISA_TYPE_UB, 0 }, /// Properties
2097 { OPND_VECTOR_SRC, ISA_TYPE_UQ, GRF_ALIGNED }, /// Address
2098 { OPND_RAW, ISA_TYPE_UQ, 0 } /// src
2099 }
2100 },
2101
2102 { SVM_BLOCK_ST, ISA_Inst_SVM, "svm_block_st", 3,
2103 { { OPND_OTHER, ISA_TYPE_UB, 0 }, /// Properties
2104 { OPND_VECTOR_SRC, ISA_TYPE_UQ, GRF_ALIGNED }, /// Address
2105 { OPND_RAW, ISA_TYPE_UQ, 0 } /// src
2106 }
2107 },
2108
2109 { SVM_GATHER, ISA_Inst_SVM, "svm_gather", 6,
2110 { { OPND_EXECSIZE, ISA_TYPE_UB, 0 }, /// exec_size
2111 { OPND_PRED, ISA_TYPE_UW, 0 }, /// predicate
2112 { OPND_OTHER, ISA_TYPE_UB, 0 }, /// Block size
2113 { OPND_OTHER, ISA_TYPE_UB, 0 }, /// Num blocks
2114 { OPND_RAW, ISA_TYPE_UQ, 0 }, /// Addresses
2115 { OPND_RAW, ISA_TYPE_UQ, 0 } /// dst
2116 }
2117 },
2118
2119 { SVM_SCATTER, ISA_Inst_SVM, "svm_scatter", 6,
2120 { { OPND_EXECSIZE, ISA_TYPE_UB, 0 }, /// exec_size
2121 { OPND_PRED, ISA_TYPE_UW, 0 }, /// predicate
2122 { OPND_OTHER, ISA_TYPE_UB, 0 }, /// Block size
2123 { OPND_OTHER, ISA_TYPE_UB, 0 }, /// Num blocks
2124 { OPND_RAW, ISA_TYPE_UQ, 0 }, /// Addresses
2125 { OPND_RAW, ISA_TYPE_UQ, 0 } /// dst
2126 }
2127 },
2128
2129 { SVM_ATOMIC, ISA_Inst_SVM, "svm_atomic", 7,
2130 { { OPND_EXECSIZE, ISA_TYPE_UB, 0 }, /// exec_size
2131 { OPND_PRED, ISA_TYPE_UW, 0 }, /// predicate
2132 { OPND_OTHER, ISA_TYPE_UB, 0 }, /// Op
2133 { OPND_RAW, ISA_TYPE_UQ, 0 }, /// Addresses
2134 { OPND_RAW, ISA_TYPE_UQ, 0 }, /// src0
2135 { OPND_RAW, ISA_TYPE_UQ, 0 }, /// src1
2136 { OPND_RAW, ISA_TYPE_UQ, 0 } /// dst
2137 }
2138 },
2139
2140 {
2141 SVM_GATHER4SCALED, ISA_Inst_SVM, "svm_gather4scaled", 7,
2142 {
2143 { OPND_EXECSIZE, ISA_TYPE_UB, 0 }, /// exec_size
2144 { OPND_PRED, ISA_TYPE_UW, 0 }, /// predicate
2145 { OPND_OTHER, ISA_TYPE_UB, 0 }, /// channel mask
2146 { OPND_OTHER, ISA_TYPE_UW, 0 }, /// scale
2147 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UQ, SCALAR_REGION }, /// global offset
2148 { OPND_RAW, ISA_TYPE_UQ, GRF_ALIGNED }, /// offsets
2149 { OPND_RAW, ISA_TYPE_F |
2150 ISA_TYPE_D |
2151 ISA_TYPE_UD, GRF_ALIGNED } /// dst
2152 }
2153 },
2154
2155 {
2156 SVM_SCATTER4SCALED, ISA_Inst_SVM, "svm_scatter4scaled", 7,
2157 {
2158 { OPND_EXECSIZE, ISA_TYPE_UB, 0 }, /// exec_size
2159 { OPND_PRED, ISA_TYPE_UW, 0 }, /// predicate
2160 { OPND_OTHER, ISA_TYPE_UB, 0 }, /// channel mask
2161 { OPND_OTHER, ISA_TYPE_UW, 0 }, /// scale
2162 { OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UQ, SCALAR_REGION }, /// global offset
2163 { OPND_RAW, ISA_TYPE_UQ, GRF_ALIGNED }, /// offsets
2164 { OPND_RAW, ISA_TYPE_F |
2165 ISA_TYPE_D |
2166 ISA_TYPE_UD, GRF_ALIGNED } /// src
2167 }
2168 }
2169 };
2170
2171 ///////////////////////////////////////////////////////////////////////////
2172 // New LSC ops
2173 //
2174 #define LSC_UNTYPED_OP(ISA_OP, MNEMONIC) \
2175 {(ISA_OP), ISA_Inst_LSC, (MNEMONIC), 18, \
2176 { \
2177 /* execution control */\
2178 {OPND_EXECSIZE, ISA_TYPE_UB, 0}, /* execution size */ \
2179 {OPND_PRED, ISA_TYPE_UW, 0}, /* predicate */ \
2180 /* getPrimitiveOperand(0) */\
2181 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_SFID */ \
2182 /* caching opts */ \
2183 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_CACHE_OPTS::l1 */ \
2184 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_CACHE_OPTS::l3 */ \
2185 /* addr stuff */ \
2186 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_ADDR::type */ \
2187 {OPND_OTHER, ISA_TYPE_UW, 0}, /* LSC_ADDR::immScale */ \
2188 {OPND_OTHER, ISA_TYPE_D, 0}, /* LSC_ADDR::immOffset */ \
2189 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_ADDR::size */ \
2190 /* data shape stuff */ \
2191 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_DATA_SHAPE::size */ \
2192 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_DATA_SHAPE::order */ \
2193 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_DATA_SHAPE::elems */ \
2194 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_DATA_SHAPE::cmask */ \
2195 /* operands */ \
2196 {OPND_SRC_GEN|OPND_IMM|OPND_SRC_ADDR, ISA_TYPE_UB, 0}, /* Surface */ \
2197 {OPND_RAW, ISA_TYPE_UB, GRF_ALIGNED}, /* DstData */ \
2198 {OPND_RAW, ISA_TYPE_UB, GRF_ALIGNED}, /* Src0Addr */ \
2199 {OPND_RAW, ISA_TYPE_UB, GRF_ALIGNED}, /* Src1Data */ \
2200 {OPND_RAW, ISA_TYPE_UB, GRF_ALIGNED}, /* Src2Data */ \
2201 } \
2202 }
2203 #define LSC_UNTYPED_STRIDED_OP(ISA_OP, MNEMONIC) \
2204 {(ISA_OP), ISA_Inst_LSC, (MNEMONIC), 18, \
2205 { \
2206 /* execution control */\
2207 {OPND_EXECSIZE, ISA_TYPE_UB, 0}, /* execution size */ \
2208 {OPND_PRED, ISA_TYPE_UW, 0}, /* predicate */ \
2209 /* getPrimitiveOperand(0) */\
2210 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_SFID */ \
2211 /* caching opts */ \
2212 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_CACHE_OPTS::l1 */ \
2213 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_CACHE_OPTS::l3 */ \
2214 /* addr stuff */ \
2215 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_ADDR::type */ \
2216 {OPND_OTHER, ISA_TYPE_UW, 0}, /* LSC_ADDR::immScale */ \
2217 {OPND_OTHER, ISA_TYPE_D, 0}, /* LSC_ADDR::immOffset */ \
2218 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_ADDR::size */ \
2219 /* data shape stuff */ \
2220 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_DATA_SHAPE::size */ \
2221 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_DATA_SHAPE::order */ \
2222 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_DATA_SHAPE::elems */ \
2223 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_DATA_SHAPE::cmask */ \
2224 /* operands */ \
2225 {OPND_SRC_GEN|OPND_IMM|OPND_SRC_ADDR, ISA_TYPE_UB, 0}, /* Surface */ \
2226 {OPND_RAW, ISA_TYPE_UB, GRF_ALIGNED}, /* DstData */ \
2227 {OPND_RAW, ISA_TYPE_UB, GRF_ALIGNED}, /* Src0AddrBase */ \
2228 {OPND_SRC_GEN|OPND_IMM|OPND_SRC_ADDR, ISA_TYPE_UB, 0}, /* Src0AddrPitch */ \
2229 {OPND_RAW, ISA_TYPE_UB, GRF_ALIGNED}, /* Src1Data */ \
2230 } \
2231 }
2232 #define LSC_UNTYPED_BLOCK2D_OP(ISA_OP, MNEMONIC) \
2233 {(ISA_OP), ISA_Inst_LSC, (MNEMONIC), 19, \
2234 { \
2235 /* execution control */\
2236 {OPND_EXECSIZE, ISA_TYPE_UB, 0}, /* execution size */ \
2237 {OPND_PRED, ISA_TYPE_UW, 0}, /* predicate */ \
2238 /* getPrimitiveOperand(0) */\
2239 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_SFID */ \
2240 /* caching opts */ \
2241 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_CACHE_OPTS::l1 */ \
2242 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_CACHE_OPTS::l3 */ \
2243 /* block 2d data shape stuff */ \
2244 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_DATA_SHAPE_BLOCK2D::size */ \
2245 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_DATA_SHAPE_BLOCK2D::order */ \
2246 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_DATA_SHAPE_BLOCK2D::blocks */ \
2247 {OPND_OTHER, ISA_TYPE_UW, 0}, /* LSC_DATA_SHAPE_BLOCK2D::width */ \
2248 {OPND_OTHER, ISA_TYPE_UW, 0}, /* LSC_DATA_SHAPE_BLOCK2D::height */ \
2249 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_DATA_SHAPE_BLOCK2D::vnni */ \
2250 /* operands */ \
2251 {OPND_RAW, ISA_TYPE_UB, GRF_ALIGNED}, /* DstData */ \
2252 {OPND_SRC_GEN|OPND_IMM|OPND_SRC_ADDR, ISA_TYPE_UB, 0}, /* SurfBase */ \
2253 {OPND_SRC_GEN|OPND_IMM|OPND_SRC_ADDR, ISA_TYPE_UB, 0}, /* SurfWidth */ \
2254 {OPND_SRC_GEN|OPND_IMM|OPND_SRC_ADDR, ISA_TYPE_UB, 0}, /* SurfHeight */ \
2255 {OPND_SRC_GEN|OPND_IMM|OPND_SRC_ADDR, ISA_TYPE_UB, 0}, /* SurfPitch */ \
2256 {OPND_SRC_GEN|OPND_IMM|OPND_SRC_ADDR, ISA_TYPE_UB, 0}, /* SurfOffX */ \
2257 {OPND_SRC_GEN|OPND_IMM|OPND_SRC_ADDR, ISA_TYPE_UB, 0}, /* SurfOffY */ \
2258 {OPND_RAW, ISA_TYPE_UB, GRF_ALIGNED}, /* Src1Data */ \
2259 } \
2260 }
2261
2262
2263 // All LSC typed ops encode the same
2264 #define LSC_TYPED_OP(ISA_OP, MNEMONIC) \
2265 {(ISA_OP), ISA_Inst_LSC, (MNEMONIC), 18, \
2266 { \
2267 /* execution control */\
2268 {OPND_EXECSIZE, ISA_TYPE_UB, 0}, /* execution size */ \
2269 {OPND_PRED, ISA_TYPE_UW, 0}, /* predicate */ \
2270 /* caching opts */ \
2271 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_CACHE_OPTS::l1 */ \
2272 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_CACHE_OPTS::l3 */ \
2273 /* addr stuff */ \
2274 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_ADDR::type */ \
2275 /* confirmed with arch that immoff doesn't exist for typed */\
2276 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_ADDR::size */ \
2277 /* data shape stuff */ \
2278 /* we keep LSC_DATA_SHAPE::order due to lsc_load_status.tgm */ \
2279 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_DATA_SHAPE:size */ \
2280 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_DATA_SHAPE::order */ \
2281 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_DATA_SHAPE::elems */ \
2282 {OPND_OTHER, ISA_TYPE_UB, 0}, /* LSC_DATA_SHAPE::cmask */ \
2283 /* operands */ \
2284 {OPND_SRC_GEN|OPND_IMM|OPND_SRC_ADDR, ISA_TYPE_UB, 0}, /* surface reg or imm */ \
2285 {OPND_RAW, ISA_TYPE_UB, GRF_ALIGNED}, /* dst */ \
2286 {OPND_RAW, ISA_TYPE_UB, GRF_ALIGNED}, /* src0 addr Us */ \
2287 {OPND_RAW, ISA_TYPE_UB, GRF_ALIGNED}, /* src0 addr Vs */ \
2288 {OPND_RAW, ISA_TYPE_UB, GRF_ALIGNED}, /* src0 addr Rs */ \
2289 {OPND_RAW, ISA_TYPE_UB, GRF_ALIGNED}, /* src0 addr LODs */ \
2290 {OPND_RAW, ISA_TYPE_UB, GRF_ALIGNED}, /* src1 data */ \
2291 {OPND_RAW, ISA_TYPE_UB, GRF_ALIGNED}, /* src2 data */ \
2292 } \
2293 }
2294
2295 #define LSC_OP_INVALID { }
2296
2297 static const ISA_SubInst_Desc LscUntypedSubOpcodeDescs[] {
2298 LSC_UNTYPED_OP(LSC_LOAD, "lsc_load"),
2299 LSC_UNTYPED_OP(LSC_LOAD_STRIDED, "lsc_load_strided"),
2300 LSC_UNTYPED_OP(LSC_LOAD_QUAD, "lsc_load_quad"),
2301 LSC_UNTYPED_BLOCK2D_OP(LSC_LOAD_BLOCK2D, "lsc_load_block2d"),
2302 LSC_UNTYPED_OP(LSC_STORE, "lsc_store"),
2303 LSC_UNTYPED_OP(LSC_STORE_STRIDED, "lsc_store_strided"),
2304 LSC_UNTYPED_OP(LSC_STORE_QUAD, "lsc_store_quad"),
2305 LSC_UNTYPED_BLOCK2D_OP(LSC_STORE_BLOCK2D, "lsc_store_block2d"),
2306 //
2307 LSC_UNTYPED_OP(LSC_ATOMIC_IINC, "lsc_atomic_iinc"),
2308 LSC_UNTYPED_OP(LSC_ATOMIC_IDEC, "lsc_atomic_idec"),
2309 LSC_UNTYPED_OP(LSC_ATOMIC_LOAD, "lsc_atomic_load"),
2310 LSC_UNTYPED_OP(LSC_ATOMIC_STORE, "lsc_atomic_store"),
2311 LSC_UNTYPED_OP(LSC_ATOMIC_IADD, "lsc_atomic_iadd"),
2312 LSC_UNTYPED_OP(LSC_ATOMIC_ISUB, "lsc_atomic_isub"),
2313 LSC_UNTYPED_OP(LSC_ATOMIC_SMIN, "lsc_atomic_smin"),
2314 LSC_UNTYPED_OP(LSC_ATOMIC_SMAX, "lsc_atomic_smax"),
2315 LSC_UNTYPED_OP(LSC_ATOMIC_UMIN, "lsc_atomic_umin"),
2316 LSC_UNTYPED_OP(LSC_ATOMIC_UMAX, "lsc_atomic_umax"),
2317 LSC_UNTYPED_OP(LSC_ATOMIC_ICAS, "lsc_atomic_icas"),
2318 LSC_UNTYPED_OP(LSC_ATOMIC_FADD, "lsc_atomic_fadd"),
2319 LSC_UNTYPED_OP(LSC_ATOMIC_FSUB, "lsc_atomic_fsub"),
2320 LSC_UNTYPED_OP(LSC_ATOMIC_FMIN, "lsc_atomic_fmin"),
2321 LSC_UNTYPED_OP(LSC_ATOMIC_FMAX, "lsc_atomic_fmax"),
2322 LSC_UNTYPED_OP(LSC_ATOMIC_FCAS, "lsc_atomic_fcas"),
2323 LSC_UNTYPED_OP(LSC_ATOMIC_AND, "lsc_atomic_and"),
2324 LSC_UNTYPED_OP(LSC_ATOMIC_OR, "lsc_atomic_or"),
2325 LSC_UNTYPED_OP(LSC_ATOMIC_XOR, "lsc_atomic_xor"),
2326 //
2327 LSC_UNTYPED_OP(LSC_LOAD_STATUS, "lsc_load_status"),
2328 LSC_UNTYPED_OP(LSC_STORE_UNCOMPRESSED, "lsc_store_uncompressed"),
2329 LSC_UNTYPED_OP(LSC_CCS_UPDATE, "lsc_ccs_update"),
2330 LSC_OP_INVALID, // lsc_read_state_info only for typed
2331 LSC_OP_INVALID, // fence handled separately
2332
2333 };
2334
2335 static const ISA_SubInst_Desc LscTypedSubOpcodeDescs[] {
2336 LSC_OP_INVALID, // LSC_LOAD only untyped
2337 LSC_OP_INVALID, // LSC_LOAD_STRIDED only untyped
2338 LSC_TYPED_OP(LSC_LOAD_QUAD, "lsc_load_quad"),
2339 LSC_OP_INVALID, //reserved
2340 LSC_OP_INVALID, // LSC_STORE only untyped
2341 LSC_OP_INVALID, // LSC_STORE_STRIDED only untyped
2342 LSC_TYPED_OP(LSC_STORE_QUAD, "lsc_store_quad"),
2343 LSC_OP_INVALID, //reserved
2344 LSC_TYPED_OP(LSC_ATOMIC_IINC, "lsc_atomic_iinc"),
2345 LSC_TYPED_OP(LSC_ATOMIC_IDEC, "lsc_atomic_idec"),
2346 LSC_TYPED_OP(LSC_ATOMIC_LOAD, "lsc_atomic_load"),
2347 LSC_TYPED_OP(LSC_ATOMIC_STORE, "lsc_atomic_store"),
2348 LSC_TYPED_OP(LSC_ATOMIC_IADD, "lsc_atomic_iadd"),
2349 LSC_TYPED_OP(LSC_ATOMIC_ISUB, "lsc_atomic_isub"),
2350 LSC_TYPED_OP(LSC_ATOMIC_SMIN, "lsc_atomic_smin"),
2351 LSC_TYPED_OP(LSC_ATOMIC_SMAX, "lsc_atomic_smax"),
2352 LSC_TYPED_OP(LSC_ATOMIC_UMIN, "lsc_atomic_umin"),
2353 LSC_TYPED_OP(LSC_ATOMIC_UMAX, "lsc_atomic_umax"),
2354 LSC_TYPED_OP(LSC_ATOMIC_ICAS, "lsc_atomic_icas"),
2355 LSC_TYPED_OP(LSC_ATOMIC_FADD, "lsc_atomic_fadd"),
2356 LSC_TYPED_OP(LSC_ATOMIC_FSUB, "lsc_atomic_fsub"),
2357 LSC_TYPED_OP(LSC_ATOMIC_FMIN, "lsc_atomic_fmin"),
2358 LSC_TYPED_OP(LSC_ATOMIC_FMAX, "lsc_atomic_fmax"),
2359 LSC_TYPED_OP(LSC_ATOMIC_FCAS, "lsc_atomic_fcas"),
2360 LSC_TYPED_OP(LSC_ATOMIC_AND, "lsc_atomic_and"),
2361 LSC_TYPED_OP(LSC_ATOMIC_OR, "lsc_atomic_or"),
2362 LSC_TYPED_OP(LSC_ATOMIC_XOR, "lsc_atomic_xor"),
2363 //
2364 LSC_TYPED_OP(LSC_LOAD_STATUS, "lsc_load_status"),
2365 LSC_TYPED_OP(LSC_STORE_UNCOMPRESSED, "lsc_store_uncompressed"),
2366 LSC_TYPED_OP(LSC_CCS_UPDATE, "lsc_ccs_update"),
2367 LSC_TYPED_OP(LSC_READ_STATE_INFO, "lsc_read_state_info"),
2368 LSC_OP_INVALID, // fence handled separately
2369 };
2370
LscOpInfoGet(LSC_OP op)2371 LscOpInfo LscOpInfoGet(LSC_OP op)
2372 {
2373 LscOpInfo opInfo { };
2374 if (!LscOpInfoFind(op, opInfo)) {
2375 MUST_BE_TRUE(false, "invalid LSC opcode");
2376 }
2377 return opInfo;
2378 }
2379
LscOpInfoFind(LSC_OP op,LscOpInfo & opInfo)2380 bool LscOpInfoFind(LSC_OP op, LscOpInfo &opInfo)
2381 {
2382 opInfo.kind = LscOpInfo::OTHER;
2383 opInfo.encoding = 0xFFFFFFFF;
2384 opInfo.mnemonic = nullptr;
2385 opInfo.op = op;
2386
2387 auto loadOp = [&] (const char *mne, uint32_t bits) {
2388 opInfo.kind = LscOpInfo::LOAD;
2389 opInfo.encoding = bits;
2390 opInfo.mnemonic = mne;
2391 };
2392 auto storeOp = [&] (const char *mne, uint32_t bits) {
2393 opInfo.mnemonic = mne;
2394 opInfo.kind = LscOpInfo::STORE;
2395 opInfo.encoding = bits;
2396 };
2397 auto atomicOp = [&] (const char *mne, uint32_t bits, int extraOps) {
2398 opInfo.kind = LscOpInfo::ATOMIC;
2399 opInfo.encoding = bits;
2400 opInfo.mnemonic = mne;
2401 opInfo.extraOperands = extraOps;
2402 };
2403 auto otherOp = [&] (const char *mne, uint32_t bits) {
2404 opInfo.kind = LscOpInfo::OTHER;
2405 opInfo.encoding = bits;
2406 opInfo.mnemonic = mne;
2407 };
2408 switch (op) {
2409 case LSC_LOAD: loadOp("lsc_load", 0x00); break;
2410 case LSC_LOAD_STRIDED: loadOp("lsc_load_strided", 0x01); break;
2411 case LSC_LOAD_QUAD: loadOp("lsc_load_quad", 0x02); break;
2412 case LSC_LOAD_BLOCK2D: loadOp("lsc_load_block2d", 0x03); break;
2413 //
2414 case LSC_STORE: storeOp("lsc_store", 0x04); break;
2415 case LSC_STORE_STRIDED: storeOp("lsc_store_strided", 0x05); break;
2416 case LSC_STORE_QUAD: storeOp("lsc_store_quad", 0x06); break;
2417 case LSC_STORE_BLOCK2D: storeOp("lsc_store_block2d", 0x07); break;
2418 //
2419 case LSC_ATOMIC_IINC: atomicOp("lsc_atomic_iinc", 0x08, 0); break;
2420 case LSC_ATOMIC_IDEC: atomicOp("lsc_atomic_idec", 0x09, 0); break;
2421 case LSC_ATOMIC_LOAD: atomicOp("lsc_atomic_load", 0x0A, 0); break;
2422 case LSC_ATOMIC_STORE: atomicOp("lsc_atomic_store", 0x0B, 1); break;
2423 case LSC_ATOMIC_IADD: atomicOp("lsc_atomic_iadd", 0x0C, 1); break;
2424 case LSC_ATOMIC_ISUB: atomicOp("lsc_atomic_isub", 0x0D, 1); break;
2425 case LSC_ATOMIC_SMIN: atomicOp("lsc_atomic_smin", 0x0E, 1); break;
2426 case LSC_ATOMIC_SMAX: atomicOp("lsc_atomic_smax", 0x0F, 1); break;
2427 case LSC_ATOMIC_UMIN: atomicOp("lsc_atomic_umin", 0x10, 1); break;
2428 case LSC_ATOMIC_UMAX: atomicOp("lsc_atomic_umax", 0x11, 1); break;
2429 case LSC_ATOMIC_ICAS: atomicOp("lsc_atomic_icas", 0x12, 2); break;
2430 case LSC_ATOMIC_FADD: atomicOp("lsc_atomic_fadd", 0x13, 1); break;
2431 case LSC_ATOMIC_FSUB: atomicOp("lsc_atomic_fsub", 0x14, 1); break;
2432 case LSC_ATOMIC_FMIN: atomicOp("lsc_atomic_fmin", 0x15, 1); break;
2433 case LSC_ATOMIC_FMAX: atomicOp("lsc_atomic_fmax", 0x16, 1); break;
2434 case LSC_ATOMIC_FCAS: atomicOp("lsc_atomic_fcas", 0x17, 2); break;
2435 case LSC_ATOMIC_AND: atomicOp("lsc_atomic_and", 0x18, 1); break;
2436 case LSC_ATOMIC_OR: atomicOp("lsc_atomic_or", 0x19, 1); break;
2437 case LSC_ATOMIC_XOR: atomicOp("lsc_atomic_xor", 0x1A, 1); break;
2438 //
2439 case LSC_LOAD_STATUS: loadOp("lsc_load_status", 0x1B); break;
2440 case LSC_STORE_UNCOMPRESSED: storeOp("lsc_store_uncompressed", 0x1C); break;
2441 case LSC_CCS_UPDATE: otherOp("lsc_ccs_update", 0x1D); break;
2442 case LSC_READ_STATE_INFO: loadOp("lsc_read_state_info", 0x1E); break;
2443 case LSC_FENCE: otherOp("lsc_fence", 0x1F); break;
2444 //
2445 default:
2446 return false;
2447 }
2448 return true;
2449 }
2450
2451 // retuen the encoding value for descriptor bits[19:17]
LscTryEncodeCacheOptsBits17_19(const LscOpInfo & opInfo,LSC_CACHE_OPTS cacheOpts,uint32_t & cacheEnc)2452 bool LscTryEncodeCacheOptsBits17_19(
2453 const LscOpInfo &opInfo,
2454 LSC_CACHE_OPTS cacheOpts,
2455 uint32_t &cacheEnc)
2456 {
2457 auto matches =
2458 [&] (LSC_CACHE_OPT l1,LSC_CACHE_OPT l3) {
2459 return (cacheOpts.l1 == l1 && cacheOpts.l3 == l3);
2460 };
2461
2462 if (matches(LSC_CACHING_DEFAULT,LSC_CACHING_DEFAULT)) {
2463 // same for load/atomic/store
2464 cacheEnc = 0x0;
2465 } else if (matches(LSC_CACHING_UNCACHED,LSC_CACHING_UNCACHED)) {
2466 // same for load/atomic/store
2467 cacheEnc = 0x1;
2468 } else if (opInfo.isLoad()) {
2469 if (matches(LSC_CACHING_UNCACHED,LSC_CACHING_CACHED)) {
2470 cacheEnc = 0x2;
2471 } else if (matches(LSC_CACHING_CACHED,LSC_CACHING_UNCACHED)) {
2472 cacheEnc = 0x3;
2473 } else if (matches(LSC_CACHING_CACHED,LSC_CACHING_CACHED)) {
2474 cacheEnc = 0x4;
2475 } else if (matches(LSC_CACHING_STREAMING,LSC_CACHING_UNCACHED)) {
2476 cacheEnc = 0x5;
2477 } else if (matches(LSC_CACHING_STREAMING,LSC_CACHING_CACHED)) {
2478 cacheEnc = 0x6;
2479 } else if (matches(LSC_CACHING_READINVALIDATE,LSC_CACHING_CACHED)) {
2480 cacheEnc = 0x7;
2481 } else {
2482 return false;
2483 }
2484 } else if (opInfo.isAtomic()) {
2485 if (matches(LSC_CACHING_UNCACHED,LSC_CACHING_WRITEBACK)) {
2486 cacheEnc = 0x2;
2487 } else {
2488 return false;
2489 }
2490 } else {
2491 if (matches(LSC_CACHING_UNCACHED,LSC_CACHING_WRITEBACK)) {
2492 cacheEnc = 0x2;
2493 } else if (matches(LSC_CACHING_WRITETHROUGH,LSC_CACHING_UNCACHED)) {
2494 cacheEnc = 0x3;
2495 } else if (matches(LSC_CACHING_WRITETHROUGH,LSC_CACHING_WRITEBACK)) {
2496 cacheEnc = 0x4;
2497 } else if (matches(LSC_CACHING_STREAMING,LSC_CACHING_UNCACHED)) {
2498 cacheEnc = 0x5;
2499 } else if (matches(LSC_CACHING_STREAMING,LSC_CACHING_WRITEBACK)) {
2500 cacheEnc = 0x6;
2501 } else if (matches(LSC_CACHING_WRITEBACK,LSC_CACHING_WRITEBACK)) {
2502 cacheEnc = 0x7;
2503 } else {
2504 return false;
2505 }
2506 }
2507
2508 cacheEnc = cacheEnc << 17;
2509 return true;
2510 }
2511
LscTryEncodeCacheOpts(const LscOpInfo & opInfo,LSC_CACHE_OPTS cacheOpts,uint32_t & cacheEn,bool isBits17_19)2512 bool LscTryEncodeCacheOpts(
2513 const LscOpInfo &opInfo,
2514 LSC_CACHE_OPTS cacheOpts,
2515 uint32_t &cacheEn,
2516 bool isBits17_19)
2517 {
2518 return LscTryEncodeCacheOptsBits17_19(opInfo, cacheOpts, cacheEn);
2519 }
2520
2521
getSubInstTable(uint8_t opcode,int & size)2522 const ISA_SubInst_Desc *getSubInstTable(uint8_t opcode, int &size)
2523 {
2524 const ISA_SubInst_Desc *table = nullptr;
2525 switch (opcode)
2526 {
2527 case ISA_VA:
2528 table = VASubOpcodeDesc;
2529 size = sizeof(VASubOpcodeDesc)/sizeof(VASubOpcodeDesc[0]);
2530 break;
2531 case ISA_VA_SKL_PLUS:
2532 table = VAPlusSubOpcodeDesc;
2533 size = sizeof(VAPlusSubOpcodeDesc)/sizeof(VAPlusSubOpcodeDesc[0]);
2534 break;
2535 case ISA_SVM:
2536 table = SVMSubOpcodeDesc;
2537 size = sizeof(SVMSubOpcodeDesc)/sizeof(SVMSubOpcodeDesc[0]);
2538 break;
2539 case ISA_LSC_UNTYPED:
2540 table = LscUntypedSubOpcodeDescs;
2541 size = sizeof(LscUntypedSubOpcodeDescs)/sizeof(LscUntypedSubOpcodeDescs[0]);
2542 break;
2543 case ISA_LSC_TYPED:
2544 table = LscTypedSubOpcodeDescs;
2545 size = sizeof(LscTypedSubOpcodeDescs)/sizeof(LscTypedSubOpcodeDescs[0]);
2546 break;
2547 default:
2548 table = nullptr;
2549 size = 0;
2550 break;
2551 }
2552 return table;
2553 }
2554
2555
getSubInstDesc(uint8_t subOpcode) const2556 const ISA_SubInst_Desc& VISA_INST_Desc::getSubInstDesc(uint8_t subOpcode) const
2557 {
2558 int len;
2559 const ISA_SubInst_Desc *table = getSubInstTable(opcode, len);
2560 MUST_BE_TRUE((int)subOpcode < len, "subop out of bounds");
2561 return table[subOpcode];
2562 }
2563
getSubInstDescByName(const char * symbol) const2564 const ISA_SubInst_Desc& VISA_INST_Desc::getSubInstDescByName(
2565 const char *symbol) const
2566 {
2567 int len = 0;
2568 const ISA_SubInst_Desc *table = getSubInstTable(opcode, len);
2569 for (int i = 0; i < len; i++) {
2570 if (table[i].name && strcmp(table[i].name,symbol) == 0) {
2571 return table[i];
2572 }
2573 }
2574 MUST_BE_TRUE(false,"invalid subop");
2575 return table[0];
2576 }
2577