1#include "gen_ia32_regalloc_if.h" 2#include "irverify_t.h" 3#include "fourcc.h" 4 5static int cmp_attr_ia32_emms(const ir_node *a, const ir_node *b) { 6 (void) a; 7 (void) b; 8 return 1; 9} 10 11static int cmp_attr_ia32_fpushCopy(const ir_node *a, const ir_node *b) { 12 (void) a; 13 (void) b; 14 return 1; 15} 16 17static int cmp_attr_ia32_ffreep(const ir_node *a, const ir_node *b) { 18 (void) a; 19 (void) b; 20 return 1; 21} 22 23static int cmp_attr_ia32_fpush(const ir_node *a, const ir_node *b) { 24 (void) a; 25 (void) b; 26 return 1; 27} 28 29static int cmp_attr_ia32_fpop(const ir_node *a, const ir_node *b) { 30 (void) a; 31 (void) b; 32 return 1; 33} 34 35static int cmp_attr_ia32_ProduceVal(const ir_node *a, const ir_node *b) { 36 (void) a; 37 (void) b; 38 return 1; 39} 40 41static int cmp_attr_ia32_fxch(const ir_node *a, const ir_node *b) { 42 (void) a; 43 (void) b; 44 return 1; 45} 46 47static int cmp_attr_ia32_femms(const ir_node *a, const ir_node *b) { 48 (void) a; 49 (void) b; 50 return 1; 51} 52 53 54ir_op *op_ia32_xZero = NULL; 55ir_op *op_ia32_FldCW = NULL; 56ir_op *op_ia32_fadd = NULL; 57ir_op *op_ia32_ShrMem = NULL; 58ir_op *op_ia32_Immediate = NULL; 59ir_op *op_ia32_CvtSI2SS = NULL; 60ir_op *op_ia32_Bsf = NULL; 61ir_op *op_ia32_LdTls = NULL; 62ir_op *op_ia32_ShlD = NULL; 63ir_op *op_ia32_PopEbp = NULL; 64ir_op *op_ia32_Inc = NULL; 65ir_op *op_ia32_xStore = NULL; 66ir_op *op_ia32_xxLoad = NULL; 67ir_op *op_ia32_xAnd = NULL; 68ir_op *op_ia32_GetEIP = NULL; 69ir_op *op_ia32_xAdd = NULL; 70ir_op *op_ia32_xPsllq = NULL; 71ir_op *op_ia32_xxStore = NULL; 72ir_op *op_ia32_Call = NULL; 73ir_op *op_ia32_FnstCWNOP = NULL; 74ir_op *op_ia32_XorMem8Bit = NULL; 75ir_op *op_ia32_fldl2t = NULL; 76ir_op *op_ia32_fisttp = NULL; 77ir_op *op_ia32_DecMem = NULL; 78ir_op *op_ia32_emms = NULL; 79ir_op *op_ia32_xLoad = NULL; 80ir_op *op_ia32_l_FloattoLL = NULL; 81ir_op *op_ia32_CvtSI2SD = NULL; 82ir_op *op_ia32_XorMem = NULL; 83ir_op *op_ia32_CopyB = NULL; 84ir_op *op_ia32_Xor0 = NULL; 85ir_op *op_ia32_Sar = NULL; 86ir_op *op_ia32_Div = NULL; 87ir_op *op_ia32_fpushCopy = NULL; 88ir_op *op_ia32_Stc = NULL; 89ir_op *op_ia32_Fucomi = NULL; 90ir_op *op_ia32_fldl2e = NULL; 91ir_op *op_ia32_Enter = NULL; 92ir_op *op_ia32_fmul = NULL; 93ir_op *op_ia32_l_IMul = NULL; 94ir_op *op_ia32_NoReg_XMM = NULL; 95ir_op *op_ia32_xMax = NULL; 96ir_op *op_ia32_OrMem8Bit = NULL; 97ir_op *op_ia32_Prefetch1 = NULL; 98ir_op *op_ia32_fsub = NULL; 99ir_op *op_ia32_Lea = NULL; 100ir_op *op_ia32_FtstFnstsw = NULL; 101ir_op *op_ia32_NotMem = NULL; 102ir_op *op_ia32_Sbb0 = NULL; 103ir_op *op_ia32_Bt = NULL; 104ir_op *op_ia32_Or = NULL; 105ir_op *op_ia32_Xor = NULL; 106ir_op *op_ia32_CopyB_i = NULL; 107ir_op *op_ia32_IncMem = NULL; 108ir_op *op_ia32_xAllOnes = NULL; 109ir_op *op_ia32_Breakpoint = NULL; 110ir_op *op_ia32_ClimbFrame = NULL; 111ir_op *op_ia32_ffreep = NULL; 112ir_op *op_ia32_SubMem = NULL; 113ir_op *op_ia32_AddMem = NULL; 114ir_op *op_ia32_ShlMem = NULL; 115ir_op *op_ia32_fdiv = NULL; 116ir_op *op_ia32_Outport = NULL; 117ir_op *op_ia32_xMin = NULL; 118ir_op *op_ia32_fist = NULL; 119ir_op *op_ia32_xXor = NULL; 120ir_op *op_ia32_IJmp = NULL; 121ir_op *op_ia32_NegMem = NULL; 122ir_op *op_ia32_CMovcc = NULL; 123ir_op *op_ia32_Mul = NULL; 124ir_op *op_ia32_Sahf = NULL; 125ir_op *op_ia32_SubMem8Bit = NULL; 126ir_op *op_ia32_AddMem8Bit = NULL; 127ir_op *op_ia32_fst = NULL; 128ir_op *op_ia32_FucomppFnstsw = NULL; 129ir_op *op_ia32_RorMem = NULL; 130ir_op *op_ia32_fpush = NULL; 131ir_op *op_ia32_fild = NULL; 132ir_op *op_ia32_xOr = NULL; 133ir_op *op_ia32_Conv_I2I8Bit = NULL; 134ir_op *op_ia32_Store = NULL; 135ir_op *op_ia32_fldln2 = NULL; 136ir_op *op_ia32_SwitchJmp = NULL; 137ir_op *op_ia32_IMul = NULL; 138ir_op *op_ia32_Ucomi = NULL; 139ir_op *op_ia32_fldz = NULL; 140ir_op *op_ia32_Store8Bit = NULL; 141ir_op *op_ia32_fpop = NULL; 142ir_op *op_ia32_l_Sub = NULL; 143ir_op *op_ia32_Sbb = NULL; 144ir_op *op_ia32_FucomFnstsw = NULL; 145ir_op *op_ia32_xMul = NULL; 146ir_op *op_ia32_Push = NULL; 147ir_op *op_ia32_xPslld = NULL; 148ir_op *op_ia32_Cmp = NULL; 149ir_op *op_ia32_xSub = NULL; 150ir_op *op_ia32_xMovd = NULL; 151ir_op *op_ia32_Cltd = NULL; 152ir_op *op_ia32_xPsrld = NULL; 153ir_op *op_ia32_PushEax = NULL; 154ir_op *op_ia32_XorHighLow = NULL; 155ir_op *op_ia32_xPzero = NULL; 156ir_op *op_ia32_Rol = NULL; 157ir_op *op_ia32_Cmc = NULL; 158ir_op *op_ia32_Cmp8Bit = NULL; 159ir_op *op_ia32_xDiv = NULL; 160ir_op *op_ia32_xUnknown = NULL; 161ir_op *op_ia32_Test8Bit = NULL; 162ir_op *op_ia32_Sub = NULL; 163ir_op *op_ia32_PrefetchNTA = NULL; 164ir_op *op_ia32_Shr = NULL; 165ir_op *op_ia32_fprem = NULL; 166ir_op *op_ia32_IDiv = NULL; 167ir_op *op_ia32_l_Adc = NULL; 168ir_op *op_ia32_Setcc = NULL; 169ir_op *op_ia32_l_LLtoFloat = NULL; 170ir_op *op_ia32_ProduceVal = NULL; 171ir_op *op_ia32_Bswap = NULL; 172ir_op *op_ia32_SetccMem = NULL; 173ir_op *op_ia32_Test = NULL; 174ir_op *op_ia32_l_Add = NULL; 175ir_op *op_ia32_AddSP = NULL; 176ir_op *op_ia32_RolMem = NULL; 177ir_op *op_ia32_Conv_I2FP = NULL; 178ir_op *op_ia32_Conv_FP2FP = NULL; 179ir_op *op_ia32_ChangeCW = NULL; 180ir_op *op_ia32_Prefetch2 = NULL; 181ir_op *op_ia32_NoReg_GP = NULL; 182ir_op *op_ia32_Const = NULL; 183ir_op *op_ia32_Minus64Bit = NULL; 184ir_op *op_ia32_Jmp = NULL; 185ir_op *op_ia32_FnstCW = NULL; 186ir_op *op_ia32_Prefetch0 = NULL; 187ir_op *op_ia32_OrMem = NULL; 188ir_op *op_ia32_fldlg2 = NULL; 189ir_op *op_ia32_fld1 = NULL; 190ir_op *op_ia32_Conv_FP2I = NULL; 191ir_op *op_ia32_Popcnt = NULL; 192ir_op *op_ia32_Ror = NULL; 193ir_op *op_ia32_Shl = NULL; 194ir_op *op_ia32_AndMem8Bit = NULL; 195ir_op *op_ia32_Add = NULL; 196ir_op *op_ia32_SubSP = NULL; 197ir_op *op_ia32_PrefetchW = NULL; 198ir_op *op_ia32_Conv_I2I = NULL; 199ir_op *op_ia32_fxch = NULL; 200ir_op *op_ia32_fchs = NULL; 201ir_op *op_ia32_ShrD = NULL; 202ir_op *op_ia32_Unknown = NULL; 203ir_op *op_ia32_UD2 = NULL; 204ir_op *op_ia32_Cwtl = NULL; 205ir_op *op_ia32_fabs = NULL; 206ir_op *op_ia32_fldpi = NULL; 207ir_op *op_ia32_Leave = NULL; 208ir_op *op_ia32_Neg = NULL; 209ir_op *op_ia32_IMul1OP = NULL; 210ir_op *op_ia32_PopMem = NULL; 211ir_op *op_ia32_fld = NULL; 212ir_op *op_ia32_Dec = NULL; 213ir_op *op_ia32_Pop = NULL; 214ir_op *op_ia32_CopyEbpEsp = NULL; 215ir_op *op_ia32_Not = NULL; 216ir_op *op_ia32_NoReg_FP = NULL; 217ir_op *op_ia32_AndMem = NULL; 218ir_op *op_ia32_femms = NULL; 219ir_op *op_ia32_xStoreSimple = NULL; 220ir_op *op_ia32_And = NULL; 221ir_op *op_ia32_Jcc = NULL; 222ir_op *op_ia32_Asm = NULL; 223ir_op *op_ia32_l_Sbb = NULL; 224ir_op *op_ia32_Bsr = NULL; 225ir_op *op_ia32_Bswap16 = NULL; 226ir_op *op_ia32_Inport = NULL; 227ir_op *op_ia32_SarMem = NULL; 228ir_op *op_ia32_RepPrefix = NULL; 229ir_op *op_ia32_Adc = NULL; 230ir_op *op_ia32_l_Mul = NULL; 231ir_op *op_ia32_xAndNot = NULL; 232ir_op *op_ia32_Load = NULL; 233ir_op *op_ia32_Prefetch = NULL; 234 235ir_op *get_op_ia32_xZero(void) { return op_ia32_xZero; } 236int is_ia32_xZero(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_xZero; } 237 238ir_op *get_op_ia32_FldCW(void) { return op_ia32_FldCW; } 239int is_ia32_FldCW(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_FldCW; } 240 241ir_op *get_op_ia32_fadd(void) { return op_ia32_fadd; } 242int is_ia32_fadd(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_fadd; } 243 244ir_op *get_op_ia32_ShrMem(void) { return op_ia32_ShrMem; } 245int is_ia32_ShrMem(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_ShrMem; } 246 247ir_op *get_op_ia32_Immediate(void) { return op_ia32_Immediate; } 248int is_ia32_Immediate(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Immediate; } 249 250ir_op *get_op_ia32_CvtSI2SS(void) { return op_ia32_CvtSI2SS; } 251int is_ia32_CvtSI2SS(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_CvtSI2SS; } 252 253ir_op *get_op_ia32_Bsf(void) { return op_ia32_Bsf; } 254int is_ia32_Bsf(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Bsf; } 255 256ir_op *get_op_ia32_LdTls(void) { return op_ia32_LdTls; } 257int is_ia32_LdTls(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_LdTls; } 258 259ir_op *get_op_ia32_ShlD(void) { return op_ia32_ShlD; } 260int is_ia32_ShlD(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_ShlD; } 261 262ir_op *get_op_ia32_PopEbp(void) { return op_ia32_PopEbp; } 263int is_ia32_PopEbp(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_PopEbp; } 264 265ir_op *get_op_ia32_Inc(void) { return op_ia32_Inc; } 266int is_ia32_Inc(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Inc; } 267 268ir_op *get_op_ia32_xStore(void) { return op_ia32_xStore; } 269int is_ia32_xStore(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_xStore; } 270 271ir_op *get_op_ia32_xxLoad(void) { return op_ia32_xxLoad; } 272int is_ia32_xxLoad(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_xxLoad; } 273 274ir_op *get_op_ia32_xAnd(void) { return op_ia32_xAnd; } 275int is_ia32_xAnd(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_xAnd; } 276 277ir_op *get_op_ia32_GetEIP(void) { return op_ia32_GetEIP; } 278int is_ia32_GetEIP(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_GetEIP; } 279 280ir_op *get_op_ia32_xAdd(void) { return op_ia32_xAdd; } 281int is_ia32_xAdd(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_xAdd; } 282 283ir_op *get_op_ia32_xPsllq(void) { return op_ia32_xPsllq; } 284int is_ia32_xPsllq(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_xPsllq; } 285 286ir_op *get_op_ia32_xxStore(void) { return op_ia32_xxStore; } 287int is_ia32_xxStore(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_xxStore; } 288 289ir_op *get_op_ia32_Call(void) { return op_ia32_Call; } 290int is_ia32_Call(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Call; } 291 292ir_op *get_op_ia32_FnstCWNOP(void) { return op_ia32_FnstCWNOP; } 293int is_ia32_FnstCWNOP(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_FnstCWNOP; } 294 295ir_op *get_op_ia32_XorMem8Bit(void) { return op_ia32_XorMem8Bit; } 296int is_ia32_XorMem8Bit(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_XorMem8Bit; } 297 298ir_op *get_op_ia32_fldl2t(void) { return op_ia32_fldl2t; } 299int is_ia32_fldl2t(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_fldl2t; } 300 301ir_op *get_op_ia32_fisttp(void) { return op_ia32_fisttp; } 302int is_ia32_fisttp(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_fisttp; } 303 304ir_op *get_op_ia32_DecMem(void) { return op_ia32_DecMem; } 305int is_ia32_DecMem(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_DecMem; } 306 307ir_op *get_op_ia32_emms(void) { return op_ia32_emms; } 308int is_ia32_emms(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_emms; } 309 310ir_op *get_op_ia32_xLoad(void) { return op_ia32_xLoad; } 311int is_ia32_xLoad(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_xLoad; } 312 313ir_op *get_op_ia32_l_FloattoLL(void) { return op_ia32_l_FloattoLL; } 314int is_ia32_l_FloattoLL(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_l_FloattoLL; } 315 316ir_op *get_op_ia32_CvtSI2SD(void) { return op_ia32_CvtSI2SD; } 317int is_ia32_CvtSI2SD(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_CvtSI2SD; } 318 319ir_op *get_op_ia32_XorMem(void) { return op_ia32_XorMem; } 320int is_ia32_XorMem(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_XorMem; } 321 322ir_op *get_op_ia32_CopyB(void) { return op_ia32_CopyB; } 323int is_ia32_CopyB(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_CopyB; } 324 325ir_op *get_op_ia32_Xor0(void) { return op_ia32_Xor0; } 326int is_ia32_Xor0(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Xor0; } 327 328ir_op *get_op_ia32_Sar(void) { return op_ia32_Sar; } 329int is_ia32_Sar(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Sar; } 330 331ir_op *get_op_ia32_Div(void) { return op_ia32_Div; } 332int is_ia32_Div(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Div; } 333 334ir_op *get_op_ia32_fpushCopy(void) { return op_ia32_fpushCopy; } 335int is_ia32_fpushCopy(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_fpushCopy; } 336 337ir_op *get_op_ia32_Stc(void) { return op_ia32_Stc; } 338int is_ia32_Stc(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Stc; } 339 340ir_op *get_op_ia32_Fucomi(void) { return op_ia32_Fucomi; } 341int is_ia32_Fucomi(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Fucomi; } 342 343ir_op *get_op_ia32_fldl2e(void) { return op_ia32_fldl2e; } 344int is_ia32_fldl2e(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_fldl2e; } 345 346ir_op *get_op_ia32_Enter(void) { return op_ia32_Enter; } 347int is_ia32_Enter(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Enter; } 348 349ir_op *get_op_ia32_fmul(void) { return op_ia32_fmul; } 350int is_ia32_fmul(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_fmul; } 351 352ir_op *get_op_ia32_l_IMul(void) { return op_ia32_l_IMul; } 353int is_ia32_l_IMul(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_l_IMul; } 354 355ir_op *get_op_ia32_NoReg_XMM(void) { return op_ia32_NoReg_XMM; } 356int is_ia32_NoReg_XMM(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_NoReg_XMM; } 357 358ir_op *get_op_ia32_xMax(void) { return op_ia32_xMax; } 359int is_ia32_xMax(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_xMax; } 360 361ir_op *get_op_ia32_OrMem8Bit(void) { return op_ia32_OrMem8Bit; } 362int is_ia32_OrMem8Bit(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_OrMem8Bit; } 363 364ir_op *get_op_ia32_Prefetch1(void) { return op_ia32_Prefetch1; } 365int is_ia32_Prefetch1(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Prefetch1; } 366 367ir_op *get_op_ia32_fsub(void) { return op_ia32_fsub; } 368int is_ia32_fsub(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_fsub; } 369 370ir_op *get_op_ia32_Lea(void) { return op_ia32_Lea; } 371int is_ia32_Lea(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Lea; } 372 373ir_op *get_op_ia32_FtstFnstsw(void) { return op_ia32_FtstFnstsw; } 374int is_ia32_FtstFnstsw(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_FtstFnstsw; } 375 376ir_op *get_op_ia32_NotMem(void) { return op_ia32_NotMem; } 377int is_ia32_NotMem(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_NotMem; } 378 379ir_op *get_op_ia32_Sbb0(void) { return op_ia32_Sbb0; } 380int is_ia32_Sbb0(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Sbb0; } 381 382ir_op *get_op_ia32_Bt(void) { return op_ia32_Bt; } 383int is_ia32_Bt(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Bt; } 384 385ir_op *get_op_ia32_Or(void) { return op_ia32_Or; } 386int is_ia32_Or(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Or; } 387 388ir_op *get_op_ia32_Xor(void) { return op_ia32_Xor; } 389int is_ia32_Xor(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Xor; } 390 391ir_op *get_op_ia32_CopyB_i(void) { return op_ia32_CopyB_i; } 392int is_ia32_CopyB_i(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_CopyB_i; } 393 394ir_op *get_op_ia32_IncMem(void) { return op_ia32_IncMem; } 395int is_ia32_IncMem(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_IncMem; } 396 397ir_op *get_op_ia32_xAllOnes(void) { return op_ia32_xAllOnes; } 398int is_ia32_xAllOnes(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_xAllOnes; } 399 400ir_op *get_op_ia32_Breakpoint(void) { return op_ia32_Breakpoint; } 401int is_ia32_Breakpoint(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Breakpoint; } 402 403ir_op *get_op_ia32_ClimbFrame(void) { return op_ia32_ClimbFrame; } 404int is_ia32_ClimbFrame(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_ClimbFrame; } 405 406ir_op *get_op_ia32_ffreep(void) { return op_ia32_ffreep; } 407int is_ia32_ffreep(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_ffreep; } 408 409ir_op *get_op_ia32_SubMem(void) { return op_ia32_SubMem; } 410int is_ia32_SubMem(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_SubMem; } 411 412ir_op *get_op_ia32_AddMem(void) { return op_ia32_AddMem; } 413int is_ia32_AddMem(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_AddMem; } 414 415ir_op *get_op_ia32_ShlMem(void) { return op_ia32_ShlMem; } 416int is_ia32_ShlMem(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_ShlMem; } 417 418ir_op *get_op_ia32_fdiv(void) { return op_ia32_fdiv; } 419int is_ia32_fdiv(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_fdiv; } 420 421ir_op *get_op_ia32_Outport(void) { return op_ia32_Outport; } 422int is_ia32_Outport(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Outport; } 423 424ir_op *get_op_ia32_xMin(void) { return op_ia32_xMin; } 425int is_ia32_xMin(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_xMin; } 426 427ir_op *get_op_ia32_fist(void) { return op_ia32_fist; } 428int is_ia32_fist(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_fist; } 429 430ir_op *get_op_ia32_xXor(void) { return op_ia32_xXor; } 431int is_ia32_xXor(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_xXor; } 432 433ir_op *get_op_ia32_IJmp(void) { return op_ia32_IJmp; } 434int is_ia32_IJmp(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_IJmp; } 435 436ir_op *get_op_ia32_NegMem(void) { return op_ia32_NegMem; } 437int is_ia32_NegMem(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_NegMem; } 438 439ir_op *get_op_ia32_CMovcc(void) { return op_ia32_CMovcc; } 440int is_ia32_CMovcc(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_CMovcc; } 441 442ir_op *get_op_ia32_Mul(void) { return op_ia32_Mul; } 443int is_ia32_Mul(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Mul; } 444 445ir_op *get_op_ia32_Sahf(void) { return op_ia32_Sahf; } 446int is_ia32_Sahf(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Sahf; } 447 448ir_op *get_op_ia32_SubMem8Bit(void) { return op_ia32_SubMem8Bit; } 449int is_ia32_SubMem8Bit(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_SubMem8Bit; } 450 451ir_op *get_op_ia32_AddMem8Bit(void) { return op_ia32_AddMem8Bit; } 452int is_ia32_AddMem8Bit(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_AddMem8Bit; } 453 454ir_op *get_op_ia32_fst(void) { return op_ia32_fst; } 455int is_ia32_fst(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_fst; } 456 457ir_op *get_op_ia32_FucomppFnstsw(void) { return op_ia32_FucomppFnstsw; } 458int is_ia32_FucomppFnstsw(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_FucomppFnstsw; } 459 460ir_op *get_op_ia32_RorMem(void) { return op_ia32_RorMem; } 461int is_ia32_RorMem(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_RorMem; } 462 463ir_op *get_op_ia32_fpush(void) { return op_ia32_fpush; } 464int is_ia32_fpush(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_fpush; } 465 466ir_op *get_op_ia32_fild(void) { return op_ia32_fild; } 467int is_ia32_fild(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_fild; } 468 469ir_op *get_op_ia32_xOr(void) { return op_ia32_xOr; } 470int is_ia32_xOr(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_xOr; } 471 472ir_op *get_op_ia32_Conv_I2I8Bit(void) { return op_ia32_Conv_I2I8Bit; } 473int is_ia32_Conv_I2I8Bit(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Conv_I2I8Bit; } 474 475ir_op *get_op_ia32_Store(void) { return op_ia32_Store; } 476int is_ia32_Store(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Store; } 477 478ir_op *get_op_ia32_fldln2(void) { return op_ia32_fldln2; } 479int is_ia32_fldln2(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_fldln2; } 480 481ir_op *get_op_ia32_SwitchJmp(void) { return op_ia32_SwitchJmp; } 482int is_ia32_SwitchJmp(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_SwitchJmp; } 483 484ir_op *get_op_ia32_IMul(void) { return op_ia32_IMul; } 485int is_ia32_IMul(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_IMul; } 486 487ir_op *get_op_ia32_Ucomi(void) { return op_ia32_Ucomi; } 488int is_ia32_Ucomi(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Ucomi; } 489 490ir_op *get_op_ia32_fldz(void) { return op_ia32_fldz; } 491int is_ia32_fldz(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_fldz; } 492 493ir_op *get_op_ia32_Store8Bit(void) { return op_ia32_Store8Bit; } 494int is_ia32_Store8Bit(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Store8Bit; } 495 496ir_op *get_op_ia32_fpop(void) { return op_ia32_fpop; } 497int is_ia32_fpop(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_fpop; } 498 499ir_op *get_op_ia32_l_Sub(void) { return op_ia32_l_Sub; } 500int is_ia32_l_Sub(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_l_Sub; } 501 502ir_op *get_op_ia32_Sbb(void) { return op_ia32_Sbb; } 503int is_ia32_Sbb(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Sbb; } 504 505ir_op *get_op_ia32_FucomFnstsw(void) { return op_ia32_FucomFnstsw; } 506int is_ia32_FucomFnstsw(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_FucomFnstsw; } 507 508ir_op *get_op_ia32_xMul(void) { return op_ia32_xMul; } 509int is_ia32_xMul(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_xMul; } 510 511ir_op *get_op_ia32_Push(void) { return op_ia32_Push; } 512int is_ia32_Push(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Push; } 513 514ir_op *get_op_ia32_xPslld(void) { return op_ia32_xPslld; } 515int is_ia32_xPslld(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_xPslld; } 516 517ir_op *get_op_ia32_Cmp(void) { return op_ia32_Cmp; } 518int is_ia32_Cmp(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Cmp; } 519 520ir_op *get_op_ia32_xSub(void) { return op_ia32_xSub; } 521int is_ia32_xSub(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_xSub; } 522 523ir_op *get_op_ia32_xMovd(void) { return op_ia32_xMovd; } 524int is_ia32_xMovd(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_xMovd; } 525 526ir_op *get_op_ia32_Cltd(void) { return op_ia32_Cltd; } 527int is_ia32_Cltd(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Cltd; } 528 529ir_op *get_op_ia32_xPsrld(void) { return op_ia32_xPsrld; } 530int is_ia32_xPsrld(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_xPsrld; } 531 532ir_op *get_op_ia32_PushEax(void) { return op_ia32_PushEax; } 533int is_ia32_PushEax(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_PushEax; } 534 535ir_op *get_op_ia32_XorHighLow(void) { return op_ia32_XorHighLow; } 536int is_ia32_XorHighLow(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_XorHighLow; } 537 538ir_op *get_op_ia32_xPzero(void) { return op_ia32_xPzero; } 539int is_ia32_xPzero(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_xPzero; } 540 541ir_op *get_op_ia32_Rol(void) { return op_ia32_Rol; } 542int is_ia32_Rol(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Rol; } 543 544ir_op *get_op_ia32_Cmc(void) { return op_ia32_Cmc; } 545int is_ia32_Cmc(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Cmc; } 546 547ir_op *get_op_ia32_Cmp8Bit(void) { return op_ia32_Cmp8Bit; } 548int is_ia32_Cmp8Bit(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Cmp8Bit; } 549 550ir_op *get_op_ia32_xDiv(void) { return op_ia32_xDiv; } 551int is_ia32_xDiv(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_xDiv; } 552 553ir_op *get_op_ia32_xUnknown(void) { return op_ia32_xUnknown; } 554int is_ia32_xUnknown(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_xUnknown; } 555 556ir_op *get_op_ia32_Test8Bit(void) { return op_ia32_Test8Bit; } 557int is_ia32_Test8Bit(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Test8Bit; } 558 559ir_op *get_op_ia32_Sub(void) { return op_ia32_Sub; } 560int is_ia32_Sub(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Sub; } 561 562ir_op *get_op_ia32_PrefetchNTA(void) { return op_ia32_PrefetchNTA; } 563int is_ia32_PrefetchNTA(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_PrefetchNTA; } 564 565ir_op *get_op_ia32_Shr(void) { return op_ia32_Shr; } 566int is_ia32_Shr(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Shr; } 567 568ir_op *get_op_ia32_fprem(void) { return op_ia32_fprem; } 569int is_ia32_fprem(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_fprem; } 570 571ir_op *get_op_ia32_IDiv(void) { return op_ia32_IDiv; } 572int is_ia32_IDiv(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_IDiv; } 573 574ir_op *get_op_ia32_l_Adc(void) { return op_ia32_l_Adc; } 575int is_ia32_l_Adc(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_l_Adc; } 576 577ir_op *get_op_ia32_Setcc(void) { return op_ia32_Setcc; } 578int is_ia32_Setcc(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Setcc; } 579 580ir_op *get_op_ia32_l_LLtoFloat(void) { return op_ia32_l_LLtoFloat; } 581int is_ia32_l_LLtoFloat(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_l_LLtoFloat; } 582 583ir_op *get_op_ia32_ProduceVal(void) { return op_ia32_ProduceVal; } 584int is_ia32_ProduceVal(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_ProduceVal; } 585 586ir_op *get_op_ia32_Bswap(void) { return op_ia32_Bswap; } 587int is_ia32_Bswap(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Bswap; } 588 589ir_op *get_op_ia32_SetccMem(void) { return op_ia32_SetccMem; } 590int is_ia32_SetccMem(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_SetccMem; } 591 592ir_op *get_op_ia32_Test(void) { return op_ia32_Test; } 593int is_ia32_Test(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Test; } 594 595ir_op *get_op_ia32_l_Add(void) { return op_ia32_l_Add; } 596int is_ia32_l_Add(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_l_Add; } 597 598ir_op *get_op_ia32_AddSP(void) { return op_ia32_AddSP; } 599int is_ia32_AddSP(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_AddSP; } 600 601ir_op *get_op_ia32_RolMem(void) { return op_ia32_RolMem; } 602int is_ia32_RolMem(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_RolMem; } 603 604ir_op *get_op_ia32_Conv_I2FP(void) { return op_ia32_Conv_I2FP; } 605int is_ia32_Conv_I2FP(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Conv_I2FP; } 606 607ir_op *get_op_ia32_Conv_FP2FP(void) { return op_ia32_Conv_FP2FP; } 608int is_ia32_Conv_FP2FP(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Conv_FP2FP; } 609 610ir_op *get_op_ia32_ChangeCW(void) { return op_ia32_ChangeCW; } 611int is_ia32_ChangeCW(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_ChangeCW; } 612 613ir_op *get_op_ia32_Prefetch2(void) { return op_ia32_Prefetch2; } 614int is_ia32_Prefetch2(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Prefetch2; } 615 616ir_op *get_op_ia32_NoReg_GP(void) { return op_ia32_NoReg_GP; } 617int is_ia32_NoReg_GP(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_NoReg_GP; } 618 619ir_op *get_op_ia32_Const(void) { return op_ia32_Const; } 620int is_ia32_Const(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Const; } 621 622ir_op *get_op_ia32_Minus64Bit(void) { return op_ia32_Minus64Bit; } 623int is_ia32_Minus64Bit(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Minus64Bit; } 624 625ir_op *get_op_ia32_Jmp(void) { return op_ia32_Jmp; } 626int is_ia32_Jmp(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Jmp; } 627 628ir_op *get_op_ia32_FnstCW(void) { return op_ia32_FnstCW; } 629int is_ia32_FnstCW(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_FnstCW; } 630 631ir_op *get_op_ia32_Prefetch0(void) { return op_ia32_Prefetch0; } 632int is_ia32_Prefetch0(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Prefetch0; } 633 634ir_op *get_op_ia32_OrMem(void) { return op_ia32_OrMem; } 635int is_ia32_OrMem(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_OrMem; } 636 637ir_op *get_op_ia32_fldlg2(void) { return op_ia32_fldlg2; } 638int is_ia32_fldlg2(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_fldlg2; } 639 640ir_op *get_op_ia32_fld1(void) { return op_ia32_fld1; } 641int is_ia32_fld1(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_fld1; } 642 643ir_op *get_op_ia32_Conv_FP2I(void) { return op_ia32_Conv_FP2I; } 644int is_ia32_Conv_FP2I(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Conv_FP2I; } 645 646ir_op *get_op_ia32_Popcnt(void) { return op_ia32_Popcnt; } 647int is_ia32_Popcnt(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Popcnt; } 648 649ir_op *get_op_ia32_Ror(void) { return op_ia32_Ror; } 650int is_ia32_Ror(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Ror; } 651 652ir_op *get_op_ia32_Shl(void) { return op_ia32_Shl; } 653int is_ia32_Shl(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Shl; } 654 655ir_op *get_op_ia32_AndMem8Bit(void) { return op_ia32_AndMem8Bit; } 656int is_ia32_AndMem8Bit(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_AndMem8Bit; } 657 658ir_op *get_op_ia32_Add(void) { return op_ia32_Add; } 659int is_ia32_Add(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Add; } 660 661ir_op *get_op_ia32_SubSP(void) { return op_ia32_SubSP; } 662int is_ia32_SubSP(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_SubSP; } 663 664ir_op *get_op_ia32_PrefetchW(void) { return op_ia32_PrefetchW; } 665int is_ia32_PrefetchW(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_PrefetchW; } 666 667ir_op *get_op_ia32_Conv_I2I(void) { return op_ia32_Conv_I2I; } 668int is_ia32_Conv_I2I(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Conv_I2I; } 669 670ir_op *get_op_ia32_fxch(void) { return op_ia32_fxch; } 671int is_ia32_fxch(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_fxch; } 672 673ir_op *get_op_ia32_fchs(void) { return op_ia32_fchs; } 674int is_ia32_fchs(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_fchs; } 675 676ir_op *get_op_ia32_ShrD(void) { return op_ia32_ShrD; } 677int is_ia32_ShrD(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_ShrD; } 678 679ir_op *get_op_ia32_Unknown(void) { return op_ia32_Unknown; } 680int is_ia32_Unknown(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Unknown; } 681 682ir_op *get_op_ia32_UD2(void) { return op_ia32_UD2; } 683int is_ia32_UD2(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_UD2; } 684 685ir_op *get_op_ia32_Cwtl(void) { return op_ia32_Cwtl; } 686int is_ia32_Cwtl(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Cwtl; } 687 688ir_op *get_op_ia32_fabs(void) { return op_ia32_fabs; } 689int is_ia32_fabs(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_fabs; } 690 691ir_op *get_op_ia32_fldpi(void) { return op_ia32_fldpi; } 692int is_ia32_fldpi(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_fldpi; } 693 694ir_op *get_op_ia32_Leave(void) { return op_ia32_Leave; } 695int is_ia32_Leave(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Leave; } 696 697ir_op *get_op_ia32_Neg(void) { return op_ia32_Neg; } 698int is_ia32_Neg(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Neg; } 699 700ir_op *get_op_ia32_IMul1OP(void) { return op_ia32_IMul1OP; } 701int is_ia32_IMul1OP(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_IMul1OP; } 702 703ir_op *get_op_ia32_PopMem(void) { return op_ia32_PopMem; } 704int is_ia32_PopMem(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_PopMem; } 705 706ir_op *get_op_ia32_fld(void) { return op_ia32_fld; } 707int is_ia32_fld(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_fld; } 708 709ir_op *get_op_ia32_Dec(void) { return op_ia32_Dec; } 710int is_ia32_Dec(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Dec; } 711 712ir_op *get_op_ia32_Pop(void) { return op_ia32_Pop; } 713int is_ia32_Pop(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Pop; } 714 715ir_op *get_op_ia32_CopyEbpEsp(void) { return op_ia32_CopyEbpEsp; } 716int is_ia32_CopyEbpEsp(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_CopyEbpEsp; } 717 718ir_op *get_op_ia32_Not(void) { return op_ia32_Not; } 719int is_ia32_Not(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Not; } 720 721ir_op *get_op_ia32_NoReg_FP(void) { return op_ia32_NoReg_FP; } 722int is_ia32_NoReg_FP(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_NoReg_FP; } 723 724ir_op *get_op_ia32_AndMem(void) { return op_ia32_AndMem; } 725int is_ia32_AndMem(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_AndMem; } 726 727ir_op *get_op_ia32_femms(void) { return op_ia32_femms; } 728int is_ia32_femms(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_femms; } 729 730ir_op *get_op_ia32_xStoreSimple(void) { return op_ia32_xStoreSimple; } 731int is_ia32_xStoreSimple(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_xStoreSimple; } 732 733ir_op *get_op_ia32_And(void) { return op_ia32_And; } 734int is_ia32_And(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_And; } 735 736ir_op *get_op_ia32_Jcc(void) { return op_ia32_Jcc; } 737int is_ia32_Jcc(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Jcc; } 738 739ir_op *get_op_ia32_Asm(void) { return op_ia32_Asm; } 740int is_ia32_Asm(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Asm; } 741 742ir_op *get_op_ia32_l_Sbb(void) { return op_ia32_l_Sbb; } 743int is_ia32_l_Sbb(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_l_Sbb; } 744 745ir_op *get_op_ia32_Bsr(void) { return op_ia32_Bsr; } 746int is_ia32_Bsr(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Bsr; } 747 748ir_op *get_op_ia32_Bswap16(void) { return op_ia32_Bswap16; } 749int is_ia32_Bswap16(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Bswap16; } 750 751ir_op *get_op_ia32_Inport(void) { return op_ia32_Inport; } 752int is_ia32_Inport(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Inport; } 753 754ir_op *get_op_ia32_SarMem(void) { return op_ia32_SarMem; } 755int is_ia32_SarMem(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_SarMem; } 756 757ir_op *get_op_ia32_RepPrefix(void) { return op_ia32_RepPrefix; } 758int is_ia32_RepPrefix(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_RepPrefix; } 759 760ir_op *get_op_ia32_Adc(void) { return op_ia32_Adc; } 761int is_ia32_Adc(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Adc; } 762 763ir_op *get_op_ia32_l_Mul(void) { return op_ia32_l_Mul; } 764int is_ia32_l_Mul(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_l_Mul; } 765 766ir_op *get_op_ia32_xAndNot(void) { return op_ia32_xAndNot; } 767int is_ia32_xAndNot(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_xAndNot; } 768 769ir_op *get_op_ia32_Load(void) { return op_ia32_Load; } 770int is_ia32_Load(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Load; } 771 772ir_op *get_op_ia32_Prefetch(void) { return op_ia32_Prefetch; } 773int is_ia32_Prefetch(const ir_node *n) { return get_ia32_irn_opcode(n) == iro_ia32_Prefetch; } 774 775 776 777static int ia32_opcode_start = -1; 778static int ia32_opcode_end = -1; 779 780 781/** A tag for the ia32 opcodes. Note that the address is used as a tag value, NOT the FOURCC code. */ 782#define ia32_op_tag FOURCC('I', 'A', '3', '2') 783 784/** Return the opcode number of the first ia32 opcode. */ 785int get_ia32_opcode_first(void) { 786 return ia32_opcode_start; 787} 788 789/** Return the opcode number of the last ia32 opcode + 1. */ 790int get_ia32_opcode_last(void) { 791 return ia32_opcode_end; 792} 793 794/** Return 1 if the given opcode is a ia32 machine op, 0 otherwise */ 795int is_ia32_op(const ir_op *op) { 796 return get_op_tag(op) == ia32_op_tag; 797} 798 799/** Return 1 if the given node is a ia32 machine node, 0 otherwise */ 800int is_ia32_irn(const ir_node *node) { 801 return is_ia32_op(get_irn_op(node)); 802} 803 804int get_ia32_irn_opcode(const ir_node *node) { 805 if (is_ia32_irn(node)) 806 return get_irn_opcode(node) - ia32_opcode_start; 807 return -1; 808} 809 810#ifdef BIT 811#undef BIT 812#endif 813#define BIT(x) (1 << (x)) 814 815static const unsigned ia32_limit_fp_cw_fpcw[] = { BIT(REG_FP_CW_FPCW) }; 816static const unsigned ia32_limit_gp_ecx[] = { BIT(REG_GP_ECX), 0 }; 817static const unsigned ia32_limit_gp_gp_NOREG[] = { BIT(REG_GP_GP_NOREG), 0 }; 818static const unsigned ia32_limit_gp_ebp[] = { BIT(REG_GP_EBP), 0 }; 819static const unsigned ia32_limit_gp_esp[] = { BIT(REG_GP_ESP), 0 }; 820static const unsigned ia32_limit_gp_eax[] = { BIT(REG_GP_EAX), 0 }; 821static const unsigned ia32_limit_gp_edx[] = { BIT(REG_GP_EDX), 0 }; 822static const unsigned ia32_limit_fp_st0[] = { BIT(REG_FP_ST0), 0 }; 823static const unsigned ia32_limit_fp_st1[] = { BIT(REG_FP_ST1), 0 }; 824static const unsigned ia32_limit_fp_st2[] = { BIT(REG_FP_ST2), 0 }; 825static const unsigned ia32_limit_fp_st3[] = { BIT(REG_FP_ST3), 0 }; 826static const unsigned ia32_limit_fp_st4[] = { BIT(REG_FP_ST4), 0 }; 827static const unsigned ia32_limit_fp_st5[] = { BIT(REG_FP_ST5), 0 }; 828static const unsigned ia32_limit_fp_st6[] = { BIT(REG_FP_ST6), 0 }; 829static const unsigned ia32_limit_fp_st7[] = { BIT(REG_FP_ST7), 0 }; 830static const unsigned ia32_limit_xmm_xmm0[] = { BIT(REG_XMM_XMM0), 0 }; 831static const unsigned ia32_limit_xmm_xmm1[] = { BIT(REG_XMM_XMM1), 0 }; 832static const unsigned ia32_limit_xmm_xmm2[] = { BIT(REG_XMM_XMM2), 0 }; 833static const unsigned ia32_limit_xmm_xmm3[] = { BIT(REG_XMM_XMM3), 0 }; 834static const unsigned ia32_limit_xmm_xmm4[] = { BIT(REG_XMM_XMM4), 0 }; 835static const unsigned ia32_limit_xmm_xmm5[] = { BIT(REG_XMM_XMM5), 0 }; 836static const unsigned ia32_limit_xmm_xmm6[] = { BIT(REG_XMM_XMM6), 0 }; 837static const unsigned ia32_limit_xmm_xmm7[] = { BIT(REG_XMM_XMM7), 0 }; 838static const unsigned ia32_limit_gp_eax_ebx_ecx_edx[] = { BIT(REG_GP_EAX) | BIT(REG_GP_EBX) | BIT(REG_GP_ECX) | BIT(REG_GP_EDX), 0 }; 839static const unsigned ia32_limit_gp_edi[] = { BIT(REG_GP_EDI), 0 }; 840static const unsigned ia32_limit_gp_esi[] = { BIT(REG_GP_ESI), 0 }; 841static const unsigned ia32_limit_flags_eflags[] = { BIT(REG_FLAGS_EFLAGS) }; 842static const unsigned ia32_limit_xmm_xmm_NOREG[] = { BIT(REG_XMM_XMM_NOREG), 0 }; 843static const unsigned ia32_limit_fp_fp_NOREG[] = { BIT(REG_FP_FP_NOREG), 0 }; 844 845static const arch_register_req_t ia32_requirements_xmm_xmm = { 846 arch_register_req_type_normal, 847 & ia32_reg_classes[CLASS_ia32_xmm], 848 NULL, /* limit bitset */ 849 0, /* same pos */ 850 0, /* different pos */ 851 1 /* width */ 852}; 853 854 855static const arch_register_req_t ia32_requirements_gp_gp = { 856 arch_register_req_type_normal, 857 & ia32_reg_classes[CLASS_ia32_gp], 858 NULL, /* limit bitset */ 859 0, /* same pos */ 860 0, /* different pos */ 861 1 /* width */ 862}; 863 864 865static const arch_register_req_t ia32_requirements__none = { 866 arch_register_req_type_none, 867 NULL, /* regclass */ 868 NULL, /* limit bitset */ 869 0, /* same pos */ 870 0, /* different pos */ 871 0 /* width */ 872}; 873 874 875static const arch_register_req_t ia32_requirements_fp_cw_fpcw_I = { 876 arch_register_req_type_ignore | arch_register_req_type_limited, 877 & ia32_reg_classes[CLASS_ia32_fp_cw], 878 ia32_limit_fp_cw_fpcw, 879 0, /* same pos */ 880 0, /* different pos */ 881 1 /* width */ 882}; 883 884 885static const arch_register_req_t ia32_requirements_fp_fp = { 886 arch_register_req_type_normal, 887 & ia32_reg_classes[CLASS_ia32_fp], 888 NULL, /* limit bitset */ 889 0, /* same pos */ 890 0, /* different pos */ 891 1 /* width */ 892}; 893 894 895static const arch_register_req_t ia32_requirements_fp_cw_fpcw = { 896 arch_register_req_type_limited, 897 & ia32_reg_classes[CLASS_ia32_fp_cw], 898 ia32_limit_fp_cw_fpcw, 899 0, /* same pos */ 900 0, /* different pos */ 901 1 /* width */ 902}; 903 904 905static const arch_register_req_t ia32_requirements_gp_ecx = { 906 arch_register_req_type_limited, 907 & ia32_reg_classes[CLASS_ia32_gp], 908 ia32_limit_gp_ecx, 909 0, /* same pos */ 910 0, /* different pos */ 911 1 /* width */ 912}; 913 914 915static const arch_register_req_t ia32_requirements_gp_gp_NOREG_I = { 916 arch_register_req_type_ignore | arch_register_req_type_limited, 917 & ia32_reg_classes[CLASS_ia32_gp], 918 ia32_limit_gp_gp_NOREG, 919 0, /* same pos */ 920 0, /* different pos */ 921 1 /* width */ 922}; 923 924 925static const arch_register_req_t ia32_requirements_flags_flags = { 926 arch_register_req_type_normal, 927 & ia32_reg_classes[CLASS_ia32_flags], 928 NULL, /* limit bitset */ 929 0, /* same pos */ 930 0, /* different pos */ 931 1 /* width */ 932}; 933 934 935static const arch_register_req_t ia32_requirements_gp_in_r1_not_in_r2_not_in_r3 = { 936 arch_register_req_type_should_be_same | arch_register_req_type_must_be_different, 937 & ia32_reg_classes[CLASS_ia32_gp], 938 NULL, 939 1, /* same pos */ 940 6, /* different pos */ 941 1 /* width */ 942}; 943 944 945static const arch_register_req_t ia32_requirements_gp_ebp_I = { 946 arch_register_req_type_ignore | arch_register_req_type_limited, 947 & ia32_reg_classes[CLASS_ia32_gp], 948 ia32_limit_gp_ebp, 949 0, /* same pos */ 950 0, /* different pos */ 951 1 /* width */ 952}; 953 954 955static const arch_register_req_t ia32_requirements_gp_esp = { 956 arch_register_req_type_limited, 957 & ia32_reg_classes[CLASS_ia32_gp], 958 ia32_limit_gp_esp, 959 0, /* same pos */ 960 0, /* different pos */ 961 1 /* width */ 962}; 963 964 965static const arch_register_req_t ia32_requirements_gp_esp_I_S = { 966 arch_register_req_type_ignore | arch_register_req_type_produces_sp | arch_register_req_type_limited, 967 & ia32_reg_classes[CLASS_ia32_gp], 968 ia32_limit_gp_esp, 969 0, /* same pos */ 970 0, /* different pos */ 971 1 /* width */ 972}; 973 974 975static const arch_register_req_t ia32_requirements_gp_in_r1 = { 976 arch_register_req_type_should_be_same, 977 & ia32_reg_classes[CLASS_ia32_gp], 978 NULL, 979 1, /* same pos */ 980 0, /* different pos */ 981 1 /* width */ 982}; 983 984 985static const arch_register_req_t ia32_requirements_xmm_in_r4_in_r5 = { 986 arch_register_req_type_should_be_same, 987 & ia32_reg_classes[CLASS_ia32_xmm], 988 NULL, 989 24, /* same pos */ 990 0, /* different pos */ 991 1 /* width */ 992}; 993 994 995static const arch_register_req_t ia32_requirements_xmm_in_r1_not_in_r2 = { 996 arch_register_req_type_should_be_same | arch_register_req_type_must_be_different, 997 & ia32_reg_classes[CLASS_ia32_xmm], 998 NULL, 999 1, /* same pos */ 1000 2, /* different pos */ 1001 1 /* width */ 1002}; 1003 1004 1005static const arch_register_req_t ia32_requirements_gp_eax = { 1006 arch_register_req_type_limited, 1007 & ia32_reg_classes[CLASS_ia32_gp], 1008 ia32_limit_gp_eax, 1009 0, /* same pos */ 1010 0, /* different pos */ 1011 1 /* width */ 1012}; 1013 1014 1015static const arch_register_req_t ia32_requirements_gp_edx = { 1016 arch_register_req_type_limited, 1017 & ia32_reg_classes[CLASS_ia32_gp], 1018 ia32_limit_gp_edx, 1019 0, /* same pos */ 1020 0, /* different pos */ 1021 1 /* width */ 1022}; 1023 1024 1025static const arch_register_req_t ia32_requirements_fp_st0 = { 1026 arch_register_req_type_limited, 1027 & ia32_reg_classes[CLASS_ia32_fp], 1028 ia32_limit_fp_st0, 1029 0, /* same pos */ 1030 0, /* different pos */ 1031 1 /* width */ 1032}; 1033 1034 1035static const arch_register_req_t ia32_requirements_fp_st1 = { 1036 arch_register_req_type_limited, 1037 & ia32_reg_classes[CLASS_ia32_fp], 1038 ia32_limit_fp_st1, 1039 0, /* same pos */ 1040 0, /* different pos */ 1041 1 /* width */ 1042}; 1043 1044 1045static const arch_register_req_t ia32_requirements_fp_st2 = { 1046 arch_register_req_type_limited, 1047 & ia32_reg_classes[CLASS_ia32_fp], 1048 ia32_limit_fp_st2, 1049 0, /* same pos */ 1050 0, /* different pos */ 1051 1 /* width */ 1052}; 1053 1054 1055static const arch_register_req_t ia32_requirements_fp_st3 = { 1056 arch_register_req_type_limited, 1057 & ia32_reg_classes[CLASS_ia32_fp], 1058 ia32_limit_fp_st3, 1059 0, /* same pos */ 1060 0, /* different pos */ 1061 1 /* width */ 1062}; 1063 1064 1065static const arch_register_req_t ia32_requirements_fp_st4 = { 1066 arch_register_req_type_limited, 1067 & ia32_reg_classes[CLASS_ia32_fp], 1068 ia32_limit_fp_st4, 1069 0, /* same pos */ 1070 0, /* different pos */ 1071 1 /* width */ 1072}; 1073 1074 1075static const arch_register_req_t ia32_requirements_fp_st5 = { 1076 arch_register_req_type_limited, 1077 & ia32_reg_classes[CLASS_ia32_fp], 1078 ia32_limit_fp_st5, 1079 0, /* same pos */ 1080 0, /* different pos */ 1081 1 /* width */ 1082}; 1083 1084 1085static const arch_register_req_t ia32_requirements_fp_st6 = { 1086 arch_register_req_type_limited, 1087 & ia32_reg_classes[CLASS_ia32_fp], 1088 ia32_limit_fp_st6, 1089 0, /* same pos */ 1090 0, /* different pos */ 1091 1 /* width */ 1092}; 1093 1094 1095static const arch_register_req_t ia32_requirements_fp_st7 = { 1096 arch_register_req_type_limited, 1097 & ia32_reg_classes[CLASS_ia32_fp], 1098 ia32_limit_fp_st7, 1099 0, /* same pos */ 1100 0, /* different pos */ 1101 1 /* width */ 1102}; 1103 1104 1105static const arch_register_req_t ia32_requirements_xmm_xmm0 = { 1106 arch_register_req_type_limited, 1107 & ia32_reg_classes[CLASS_ia32_xmm], 1108 ia32_limit_xmm_xmm0, 1109 0, /* same pos */ 1110 0, /* different pos */ 1111 1 /* width */ 1112}; 1113 1114 1115static const arch_register_req_t ia32_requirements_xmm_xmm1 = { 1116 arch_register_req_type_limited, 1117 & ia32_reg_classes[CLASS_ia32_xmm], 1118 ia32_limit_xmm_xmm1, 1119 0, /* same pos */ 1120 0, /* different pos */ 1121 1 /* width */ 1122}; 1123 1124 1125static const arch_register_req_t ia32_requirements_xmm_xmm2 = { 1126 arch_register_req_type_limited, 1127 & ia32_reg_classes[CLASS_ia32_xmm], 1128 ia32_limit_xmm_xmm2, 1129 0, /* same pos */ 1130 0, /* different pos */ 1131 1 /* width */ 1132}; 1133 1134 1135static const arch_register_req_t ia32_requirements_xmm_xmm3 = { 1136 arch_register_req_type_limited, 1137 & ia32_reg_classes[CLASS_ia32_xmm], 1138 ia32_limit_xmm_xmm3, 1139 0, /* same pos */ 1140 0, /* different pos */ 1141 1 /* width */ 1142}; 1143 1144 1145static const arch_register_req_t ia32_requirements_xmm_xmm4 = { 1146 arch_register_req_type_limited, 1147 & ia32_reg_classes[CLASS_ia32_xmm], 1148 ia32_limit_xmm_xmm4, 1149 0, /* same pos */ 1150 0, /* different pos */ 1151 1 /* width */ 1152}; 1153 1154 1155static const arch_register_req_t ia32_requirements_xmm_xmm5 = { 1156 arch_register_req_type_limited, 1157 & ia32_reg_classes[CLASS_ia32_xmm], 1158 ia32_limit_xmm_xmm5, 1159 0, /* same pos */ 1160 0, /* different pos */ 1161 1 /* width */ 1162}; 1163 1164 1165static const arch_register_req_t ia32_requirements_xmm_xmm6 = { 1166 arch_register_req_type_limited, 1167 & ia32_reg_classes[CLASS_ia32_xmm], 1168 ia32_limit_xmm_xmm6, 1169 0, /* same pos */ 1170 0, /* different pos */ 1171 1 /* width */ 1172}; 1173 1174 1175static const arch_register_req_t ia32_requirements_xmm_xmm7 = { 1176 arch_register_req_type_limited, 1177 & ia32_reg_classes[CLASS_ia32_xmm], 1178 ia32_limit_xmm_xmm7, 1179 0, /* same pos */ 1180 0, /* different pos */ 1181 1 /* width */ 1182}; 1183 1184 1185static const arch_register_req_t ia32_requirements_fp_cw_fp_cw = { 1186 arch_register_req_type_normal, 1187 & ia32_reg_classes[CLASS_ia32_fp_cw], 1188 NULL, /* limit bitset */ 1189 0, /* same pos */ 1190 0, /* different pos */ 1191 1 /* width */ 1192}; 1193 1194 1195static const arch_register_req_t ia32_requirements_gp_eax_ebx_ecx_edx = { 1196 arch_register_req_type_limited, 1197 & ia32_reg_classes[CLASS_ia32_gp], 1198 ia32_limit_gp_eax_ebx_ecx_edx, 1199 0, /* same pos */ 1200 0, /* different pos */ 1201 1 /* width */ 1202}; 1203 1204 1205static const arch_register_req_t ia32_requirements_fp_in_r4 = { 1206 arch_register_req_type_should_be_same, 1207 & ia32_reg_classes[CLASS_ia32_fp], 1208 NULL, 1209 8, /* same pos */ 1210 0, /* different pos */ 1211 1 /* width */ 1212}; 1213 1214 1215static const arch_register_req_t ia32_requirements_gp_edi = { 1216 arch_register_req_type_limited, 1217 & ia32_reg_classes[CLASS_ia32_gp], 1218 ia32_limit_gp_edi, 1219 0, /* same pos */ 1220 0, /* different pos */ 1221 1 /* width */ 1222}; 1223 1224 1225static const arch_register_req_t ia32_requirements_gp_esi = { 1226 arch_register_req_type_limited, 1227 & ia32_reg_classes[CLASS_ia32_gp], 1228 ia32_limit_gp_esi, 1229 0, /* same pos */ 1230 0, /* different pos */ 1231 1 /* width */ 1232}; 1233 1234 1235static const arch_register_req_t ia32_requirements_gp_in_r1_not_in_r2 = { 1236 arch_register_req_type_should_be_same | arch_register_req_type_must_be_different, 1237 & ia32_reg_classes[CLASS_ia32_gp], 1238 NULL, 1239 1, /* same pos */ 1240 2, /* different pos */ 1241 1 /* width */ 1242}; 1243 1244 1245static const arch_register_req_t ia32_requirements_flags_eflags = { 1246 arch_register_req_type_limited, 1247 & ia32_reg_classes[CLASS_ia32_flags], 1248 ia32_limit_flags_eflags, 1249 0, /* same pos */ 1250 0, /* different pos */ 1251 1 /* width */ 1252}; 1253 1254 1255static const arch_register_req_t ia32_requirements_gp_ebp = { 1256 arch_register_req_type_limited, 1257 & ia32_reg_classes[CLASS_ia32_gp], 1258 ia32_limit_gp_ebp, 1259 0, /* same pos */ 1260 0, /* different pos */ 1261 1 /* width */ 1262}; 1263 1264 1265static const arch_register_req_t ia32_requirements_xmm_xmm_NOREG_I = { 1266 arch_register_req_type_ignore | arch_register_req_type_limited, 1267 & ia32_reg_classes[CLASS_ia32_xmm], 1268 ia32_limit_xmm_xmm_NOREG, 1269 0, /* same pos */ 1270 0, /* different pos */ 1271 1 /* width */ 1272}; 1273 1274 1275static const arch_register_req_t ia32_requirements_gp_in_r4_in_r5 = { 1276 arch_register_req_type_should_be_same, 1277 & ia32_reg_classes[CLASS_ia32_gp], 1278 NULL, 1279 24, /* same pos */ 1280 0, /* different pos */ 1281 1 /* width */ 1282}; 1283 1284 1285static const arch_register_req_t ia32_requirements_gp_in_r3 = { 1286 arch_register_req_type_should_be_same, 1287 & ia32_reg_classes[CLASS_ia32_gp], 1288 NULL, 1289 4, /* same pos */ 1290 0, /* different pos */ 1291 1 /* width */ 1292}; 1293 1294 1295static const arch_register_req_t ia32_requirements_gp_in_r4 = { 1296 arch_register_req_type_should_be_same, 1297 & ia32_reg_classes[CLASS_ia32_gp], 1298 NULL, 1299 8, /* same pos */ 1300 0, /* different pos */ 1301 1 /* width */ 1302}; 1303 1304 1305static const arch_register_req_t ia32_requirements_xmm_in_r4 = { 1306 arch_register_req_type_should_be_same, 1307 & ia32_reg_classes[CLASS_ia32_xmm], 1308 NULL, 1309 8, /* same pos */ 1310 0, /* different pos */ 1311 1 /* width */ 1312}; 1313 1314 1315static const arch_register_req_t ia32_requirements_xmm_in_r4_not_in_r5 = { 1316 arch_register_req_type_should_be_same | arch_register_req_type_must_be_different, 1317 & ia32_reg_classes[CLASS_ia32_xmm], 1318 NULL, 1319 8, /* same pos */ 1320 16, /* different pos */ 1321 1 /* width */ 1322}; 1323 1324 1325static const arch_register_req_t ia32_requirements_gp_in_r2 = { 1326 arch_register_req_type_should_be_same, 1327 & ia32_reg_classes[CLASS_ia32_gp], 1328 NULL, 1329 2, /* same pos */ 1330 0, /* different pos */ 1331 1 /* width */ 1332}; 1333 1334 1335static const arch_register_req_t ia32_requirements_fp_fp_NOREG_I = { 1336 arch_register_req_type_ignore | arch_register_req_type_limited, 1337 & ia32_reg_classes[CLASS_ia32_fp], 1338 ia32_limit_fp_fp_NOREG, 1339 0, /* same pos */ 1340 0, /* different pos */ 1341 1 /* width */ 1342}; 1343 1344 1345 1346/** 1347 * construct xZero node 1348 */ 1349ir_node *new_bd_ia32_xZero(dbg_info *dbgi, ir_node *block) 1350{ 1351 ir_graph *irg = get_irn_irg(block); 1352 ir_op *op = op_ia32_xZero; 1353 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 1354 ir_node *res; 1355 backend_info_t *info; 1356 int arity = 0; 1357 ir_node **in = NULL; 1358 int n_res = 1; 1359 ir_mode *mode = mode_D; 1360 static const arch_register_req_t **in_reqs = NULL; 1361 1362 /* flags */ 1363 irn_flags_ |= arch_irn_flags_rematerializable; 1364 1365 /* create node */ 1366 assert(op != NULL); 1367 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 1368 1369 /* init node attributes */ 1370 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 1371 1372 info = be_get_info(res); 1373 (void) info; /* avoid potential warning */ 1374 info->out_infos[0].req = &ia32_requirements_xmm_xmm; 1375 1376 1377 /* optimize node */ 1378 res = optimize_node(res); 1379 irn_verify_irg(res, irg); 1380 1381 return res; 1382} 1383 1384/** 1385 * construct FldCW node 1386 */ 1387ir_node *new_bd_ia32_FldCW(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem) 1388{ 1389 ir_graph *irg = get_irn_irg(block); 1390 ir_op *op = op_ia32_FldCW; 1391 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 1392 ir_node *res; 1393 backend_info_t *info; 1394 int arity = 3; 1395 ir_node *in[3]; 1396 int n_res = 1; 1397 ir_mode *mode = ia32_mode_fpcw; 1398 static const arch_register_req_t *in_reqs[] = 1399 { 1400 & ia32_requirements_gp_gp, 1401 & ia32_requirements_gp_gp, 1402 & ia32_requirements__none, 1403 }; 1404 1405 /* construct in array */ 1406 in[0] = base; 1407 in[1] = index; 1408 in[2] = mem; 1409 1410 /* create node */ 1411 assert(op != NULL); 1412 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 1413 1414 /* init node attributes */ 1415 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 1416 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 1417 1418 info = be_get_info(res); 1419 (void) info; /* avoid potential warning */ 1420 info->out_infos[0].req = &ia32_requirements_fp_cw_fpcw_I; 1421 1422 1423 /* optimize node */ 1424 res = optimize_node(res); 1425 irn_verify_irg(res, irg); 1426 1427 return res; 1428} 1429 1430/** 1431 * construct fadd node 1432 */ 1433ir_node *new_bd_ia32_fadd(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *fpcw) 1434{ 1435 ir_graph *irg = get_irn_irg(block); 1436 ir_op *op = op_ia32_fadd; 1437 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 1438 ir_node *res; 1439 backend_info_t *info; 1440 int arity = 6; 1441 ir_node *in[6]; 1442 int n_res = 3; 1443 ir_mode *mode = ia32_mode_E; 1444 static const arch_register_req_t *in_reqs[] = 1445 { 1446 & ia32_requirements_gp_gp, 1447 & ia32_requirements_gp_gp, 1448 & ia32_requirements__none, 1449 & ia32_requirements_fp_fp, 1450 & ia32_requirements_fp_fp, 1451 & ia32_requirements_fp_cw_fpcw, 1452 }; 1453 1454 /* construct in array */ 1455 in[0] = base; 1456 in[1] = index; 1457 in[2] = mem; 1458 in[3] = left; 1459 in[4] = right; 1460 in[5] = fpcw; 1461 1462 /* create node */ 1463 assert(op != NULL); 1464 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 1465 1466 /* init node attributes */ 1467 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 1468 init_ia32_x87_attributes(res); 1469 set_ia32_am_support(res, ia32_am_binary); 1470 info = be_get_info(res); 1471 (void) info; /* avoid potential warning */ 1472 info->out_infos[0].req = &ia32_requirements_fp_fp; 1473 info->out_infos[1].req = &ia32_requirements__none; 1474 info->out_infos[2].req = &ia32_requirements__none; 1475 1476 1477 /* optimize node */ 1478 res = optimize_node(res); 1479 irn_verify_irg(res, irg); 1480 1481 return res; 1482} 1483 1484/** 1485 * construct ShrMem node 1486 */ 1487ir_node *new_bd_ia32_ShrMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count) 1488{ 1489 ir_graph *irg = get_irn_irg(block); 1490 ir_op *op = op_ia32_ShrMem; 1491 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 1492 ir_node *res; 1493 backend_info_t *info; 1494 int arity = 4; 1495 ir_node *in[4]; 1496 int n_res = 1; 1497 ir_mode *mode = mode_M; 1498 static const arch_register_req_t *in_reqs[] = 1499 { 1500 & ia32_requirements_gp_gp, 1501 & ia32_requirements_gp_gp, 1502 & ia32_requirements__none, 1503 & ia32_requirements_gp_ecx, 1504 }; 1505 1506 /* construct in array */ 1507 in[0] = base; 1508 in[1] = index; 1509 in[2] = mem; 1510 in[3] = count; 1511 1512 /* flags */ 1513 irn_flags_ |= arch_irn_flags_rematerializable; 1514 1515 /* create node */ 1516 assert(op != NULL); 1517 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 1518 1519 /* init node attributes */ 1520 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 1521 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 1522 1523 info = be_get_info(res); 1524 (void) info; /* avoid potential warning */ 1525 info->out_infos[0].req = &ia32_requirements__none; 1526 1527 1528 /* optimize node */ 1529 res = optimize_node(res); 1530 irn_verify_irg(res, irg); 1531 1532 return res; 1533} 1534 1535/** 1536 * construct Immediate node 1537 */ 1538ir_node *new_bd_ia32_Immediate(dbg_info *dbgi, ir_node *block, ir_entity *symconst, int symconst_sign, int no_pic_adjust, long offset) 1539{ 1540 ir_graph *irg = get_irn_irg(block); 1541 ir_op *op = op_ia32_Immediate; 1542 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 1543 ir_node *res; 1544 backend_info_t *info; 1545 int arity = 0; 1546 ir_node **in = NULL; 1547 int n_res = 1; 1548 ir_mode *mode = mode_Iu; 1549 static const arch_register_req_t **in_reqs = NULL; 1550 1551 /* flags */ 1552 irn_flags_ |= arch_irn_flags_not_scheduled; 1553 1554 /* create node */ 1555 assert(op != NULL); 1556 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 1557 1558 /* init node attributes */ 1559 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 1560 init_ia32_immediate_attributes(res, symconst, symconst_sign, no_pic_adjust, offset); 1561 1562 info = be_get_info(res); 1563 (void) info; /* avoid potential warning */ 1564 info->out_infos[0].req = &ia32_requirements_gp_gp_NOREG_I; 1565 1566 1567 /* optimize node */ 1568 res = optimize_node(res); 1569 irn_verify_irg(res, irg); 1570 1571 return res; 1572} 1573 1574/** 1575 * construct CvtSI2SS node 1576 */ 1577ir_node *new_bd_ia32_CvtSI2SS(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val) 1578{ 1579 ir_graph *irg = get_irn_irg(block); 1580 ir_op *op = op_ia32_CvtSI2SS; 1581 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 1582 ir_node *res; 1583 backend_info_t *info; 1584 int arity = 4; 1585 ir_node *in[4]; 1586 int n_res = 1; 1587 ir_mode *mode = mode_D; 1588 static const arch_register_req_t *in_reqs[] = 1589 { 1590 & ia32_requirements_gp_gp, 1591 & ia32_requirements_gp_gp, 1592 & ia32_requirements__none, 1593 & ia32_requirements_gp_gp, 1594 }; 1595 1596 /* construct in array */ 1597 in[0] = base; 1598 in[1] = index; 1599 in[2] = mem; 1600 in[3] = val; 1601 1602 /* create node */ 1603 assert(op != NULL); 1604 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 1605 1606 /* init node attributes */ 1607 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 1608 set_ia32_am_support(res, ia32_am_unary); 1609 info = be_get_info(res); 1610 (void) info; /* avoid potential warning */ 1611 info->out_infos[0].req = &ia32_requirements_xmm_xmm; 1612 1613 1614 /* optimize node */ 1615 res = optimize_node(res); 1616 irn_verify_irg(res, irg); 1617 1618 return res; 1619} 1620 1621/** 1622 * construct Bsf node 1623 */ 1624ir_node *new_bd_ia32_Bsf(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *operand) 1625{ 1626 ir_graph *irg = get_irn_irg(block); 1627 ir_op *op = op_ia32_Bsf; 1628 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 1629 ir_node *res; 1630 backend_info_t *info; 1631 int arity = 4; 1632 ir_node *in[4]; 1633 int n_res = 3; 1634 ir_mode *mode = mode_Iu; 1635 static const arch_register_req_t *in_reqs[] = 1636 { 1637 & ia32_requirements_gp_gp, 1638 & ia32_requirements_gp_gp, 1639 & ia32_requirements__none, 1640 & ia32_requirements_gp_gp, 1641 }; 1642 1643 /* construct in array */ 1644 in[0] = base; 1645 in[1] = index; 1646 in[2] = mem; 1647 in[3] = operand; 1648 1649 /* flags */ 1650 irn_flags_ |= arch_irn_flags_rematerializable; 1651 1652 /* create node */ 1653 assert(op != NULL); 1654 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 1655 1656 /* init node attributes */ 1657 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 1658 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 1659 set_ia32_am_support(res, ia32_am_binary); 1660 info = be_get_info(res); 1661 (void) info; /* avoid potential warning */ 1662 info->out_infos[0].req = &ia32_requirements_gp_gp; 1663 info->out_infos[1].req = &ia32_requirements_flags_flags; 1664 info->out_infos[2].req = &ia32_requirements__none; 1665 1666 1667 /* optimize node */ 1668 res = optimize_node(res); 1669 irn_verify_irg(res, irg); 1670 1671 return res; 1672} 1673 1674/** 1675 * construct LdTls node 1676 */ 1677ir_node *new_bd_ia32_LdTls(dbg_info *dbgi, ir_node *block) 1678{ 1679 ir_graph *irg = get_irn_irg(block); 1680 ir_op *op = op_ia32_LdTls; 1681 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 1682 ir_node *res; 1683 backend_info_t *info; 1684 int arity = 0; 1685 ir_node **in = NULL; 1686 int n_res = 1; 1687 ir_mode *mode = mode_Iu; 1688 static const arch_register_req_t **in_reqs = NULL; 1689 1690 /* flags */ 1691 irn_flags_ |= arch_irn_flags_rematerializable; 1692 1693 /* create node */ 1694 assert(op != NULL); 1695 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 1696 1697 /* init node attributes */ 1698 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 1699 1700 info = be_get_info(res); 1701 (void) info; /* avoid potential warning */ 1702 info->out_infos[0].req = &ia32_requirements_gp_gp; 1703 1704 1705 /* optimize node */ 1706 res = optimize_node(res); 1707 irn_verify_irg(res, irg); 1708 1709 return res; 1710} 1711 1712/** 1713 * construct ShlD node 1714 */ 1715ir_node *new_bd_ia32_ShlD(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_node *count) 1716{ 1717 ir_graph *irg = get_irn_irg(block); 1718 ir_op *op = op_ia32_ShlD; 1719 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 1720 ir_node *res; 1721 backend_info_t *info; 1722 int arity = 3; 1723 ir_node *in[3]; 1724 int n_res = 2; 1725 ir_mode *mode = mode_Iu; 1726 static const arch_register_req_t *in_reqs[] = 1727 { 1728 & ia32_requirements_gp_gp, 1729 & ia32_requirements_gp_gp, 1730 & ia32_requirements_gp_ecx, 1731 }; 1732 1733 /* construct in array */ 1734 in[0] = val_high; 1735 in[1] = val_low; 1736 in[2] = count; 1737 1738 /* flags */ 1739 irn_flags_ |= arch_irn_flags_rematerializable; 1740 1741 /* create node */ 1742 assert(op != NULL); 1743 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 1744 1745 /* init node attributes */ 1746 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 1747 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 1748 1749 info = be_get_info(res); 1750 (void) info; /* avoid potential warning */ 1751 info->out_infos[0].req = &ia32_requirements_gp_in_r1_not_in_r2_not_in_r3; 1752 info->out_infos[1].req = &ia32_requirements_flags_flags; 1753 1754 1755 /* optimize node */ 1756 res = optimize_node(res); 1757 irn_verify_irg(res, irg); 1758 1759 return res; 1760} 1761 1762/** 1763 * construct PopEbp node 1764 */ 1765ir_node *new_bd_ia32_PopEbp(dbg_info *dbgi, ir_node *block, ir_node *mem, ir_node *stack) 1766{ 1767 ir_graph *irg = get_irn_irg(block); 1768 ir_op *op = op_ia32_PopEbp; 1769 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 1770 ir_node *res; 1771 backend_info_t *info; 1772 int arity = 2; 1773 ir_node *in[2]; 1774 int n_res = 4; 1775 ir_mode *mode = mode_T; 1776 static const arch_register_req_t *in_reqs[] = 1777 { 1778 & ia32_requirements__none, 1779 & ia32_requirements_gp_esp, 1780 }; 1781 1782 /* construct in array */ 1783 in[0] = mem; 1784 in[1] = stack; 1785 1786 /* create node */ 1787 assert(op != NULL); 1788 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 1789 1790 /* init node attributes */ 1791 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 1792 1793 info = be_get_info(res); 1794 (void) info; /* avoid potential warning */ 1795 info->out_infos[0].req = &ia32_requirements_gp_ebp_I; 1796 info->out_infos[1].req = &ia32_requirements__none; 1797 info->out_infos[2].req = &ia32_requirements__none; 1798 info->out_infos[3].req = &ia32_requirements_gp_esp_I_S; 1799 1800 1801 /* optimize node */ 1802 res = optimize_node(res); 1803 irn_verify_irg(res, irg); 1804 1805 return res; 1806} 1807 1808/** 1809 * construct Inc node 1810 */ 1811ir_node *new_bd_ia32_Inc(dbg_info *dbgi, ir_node *block, ir_node *val) 1812{ 1813 ir_graph *irg = get_irn_irg(block); 1814 ir_op *op = op_ia32_Inc; 1815 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 1816 ir_node *res; 1817 backend_info_t *info; 1818 int arity = 1; 1819 ir_node *in[1]; 1820 int n_res = 2; 1821 ir_mode *mode = mode_Iu; 1822 static const arch_register_req_t *in_reqs[] = 1823 { 1824 & ia32_requirements_gp_gp, 1825 }; 1826 1827 /* construct in array */ 1828 in[0] = val; 1829 1830 /* flags */ 1831 irn_flags_ |= arch_irn_flags_rematerializable; 1832 1833 /* create node */ 1834 assert(op != NULL); 1835 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 1836 1837 /* init node attributes */ 1838 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 1839 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 1840 1841 info = be_get_info(res); 1842 (void) info; /* avoid potential warning */ 1843 info->out_infos[0].req = &ia32_requirements_gp_in_r1; 1844 info->out_infos[1].req = &ia32_requirements_flags_flags; 1845 1846 1847 /* optimize node */ 1848 res = optimize_node(res); 1849 irn_verify_irg(res, irg); 1850 1851 return res; 1852} 1853 1854/** 1855 * construct xStore node 1856 */ 1857ir_node *new_bd_ia32_xStore(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val) 1858{ 1859 ir_graph *irg = get_irn_irg(block); 1860 ir_op *op = op_ia32_xStore; 1861 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 1862 ir_node *res; 1863 backend_info_t *info; 1864 int arity = 4; 1865 ir_node *in[4]; 1866 int n_res = 3; 1867 ir_mode *mode = mode_T; 1868 static const arch_register_req_t *in_reqs[] = 1869 { 1870 & ia32_requirements_gp_gp, 1871 & ia32_requirements_gp_gp, 1872 & ia32_requirements__none, 1873 & ia32_requirements_xmm_xmm, 1874 }; 1875 1876 /* construct in array */ 1877 in[0] = base; 1878 in[1] = index; 1879 in[2] = mem; 1880 in[3] = val; 1881 1882 /* create node */ 1883 assert(op != NULL); 1884 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 1885 1886 /* init node attributes */ 1887 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 1888 1889 info = be_get_info(res); 1890 (void) info; /* avoid potential warning */ 1891 info->out_infos[0].req = &ia32_requirements__none; 1892 info->out_infos[1].req = &ia32_requirements__none; 1893 info->out_infos[2].req = &ia32_requirements__none; 1894 1895 1896 /* optimize node */ 1897 res = optimize_node(res); 1898 irn_verify_irg(res, irg); 1899 1900 return res; 1901} 1902 1903/** 1904 * construct xxLoad node 1905 */ 1906ir_node *new_bd_ia32_xxLoad(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem) 1907{ 1908 ir_graph *irg = get_irn_irg(block); 1909 ir_op *op = op_ia32_xxLoad; 1910 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 1911 ir_node *res; 1912 backend_info_t *info; 1913 int arity = 3; 1914 ir_node *in[3]; 1915 int n_res = 4; 1916 ir_mode *mode = mode_T; 1917 static const arch_register_req_t *in_reqs[] = 1918 { 1919 & ia32_requirements_gp_gp, 1920 & ia32_requirements_gp_gp, 1921 & ia32_requirements__none, 1922 }; 1923 1924 /* construct in array */ 1925 in[0] = base; 1926 in[1] = index; 1927 in[2] = mem; 1928 1929 /* create node */ 1930 assert(op != NULL); 1931 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 1932 1933 /* init node attributes */ 1934 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 1935 1936 info = be_get_info(res); 1937 (void) info; /* avoid potential warning */ 1938 info->out_infos[0].req = &ia32_requirements_xmm_xmm; 1939 info->out_infos[1].req = &ia32_requirements__none; 1940 info->out_infos[2].req = &ia32_requirements__none; 1941 info->out_infos[3].req = &ia32_requirements__none; 1942 1943 1944 /* optimize node */ 1945 res = optimize_node(res); 1946 irn_verify_irg(res, irg); 1947 1948 return res; 1949} 1950 1951/** 1952 * construct xAnd node 1953 */ 1954ir_node *new_bd_ia32_xAnd(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right) 1955{ 1956 ir_graph *irg = get_irn_irg(block); 1957 ir_op *op = op_ia32_xAnd; 1958 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 1959 ir_node *res; 1960 backend_info_t *info; 1961 int arity = 5; 1962 ir_node *in[5]; 1963 int n_res = 3; 1964 ir_mode *mode = mode_D; 1965 static const arch_register_req_t *in_reqs[] = 1966 { 1967 & ia32_requirements_gp_gp, 1968 & ia32_requirements_gp_gp, 1969 & ia32_requirements__none, 1970 & ia32_requirements_xmm_xmm, 1971 & ia32_requirements_xmm_xmm, 1972 }; 1973 1974 /* construct in array */ 1975 in[0] = base; 1976 in[1] = index; 1977 in[2] = mem; 1978 in[3] = left; 1979 in[4] = right; 1980 1981 /* flags */ 1982 irn_flags_ |= arch_irn_flags_rematerializable; 1983 1984 /* create node */ 1985 assert(op != NULL); 1986 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 1987 1988 /* init node attributes */ 1989 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 1990 set_ia32_am_support(res, ia32_am_binary); 1991 info = be_get_info(res); 1992 (void) info; /* avoid potential warning */ 1993 info->out_infos[0].req = &ia32_requirements_xmm_in_r4_in_r5; 1994 info->out_infos[1].req = &ia32_requirements_flags_flags; 1995 info->out_infos[2].req = &ia32_requirements__none; 1996 1997 1998 /* optimize node */ 1999 res = optimize_node(res); 2000 irn_verify_irg(res, irg); 2001 2002 return res; 2003} 2004 2005/** 2006 * construct GetEIP node 2007 */ 2008ir_node *new_bd_ia32_GetEIP(dbg_info *dbgi, ir_node *block) 2009{ 2010 ir_graph *irg = get_irn_irg(block); 2011 ir_op *op = op_ia32_GetEIP; 2012 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 2013 ir_node *res; 2014 backend_info_t *info; 2015 int arity = 0; 2016 ir_node **in = NULL; 2017 int n_res = 1; 2018 ir_mode *mode = mode_Iu; 2019 static const arch_register_req_t **in_reqs = NULL; 2020 2021 /* create node */ 2022 assert(op != NULL); 2023 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 2024 2025 /* init node attributes */ 2026 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 2027 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 2028 2029 info = be_get_info(res); 2030 (void) info; /* avoid potential warning */ 2031 info->out_infos[0].req = &ia32_requirements_gp_gp; 2032 2033 2034 /* optimize node */ 2035 res = optimize_node(res); 2036 irn_verify_irg(res, irg); 2037 2038 return res; 2039} 2040 2041/** 2042 * construct xAdd node 2043 */ 2044ir_node *new_bd_ia32_xAdd(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right) 2045{ 2046 ir_graph *irg = get_irn_irg(block); 2047 ir_op *op = op_ia32_xAdd; 2048 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 2049 ir_node *res; 2050 backend_info_t *info; 2051 int arity = 5; 2052 ir_node *in[5]; 2053 int n_res = 3; 2054 ir_mode *mode = mode_D; 2055 static const arch_register_req_t *in_reqs[] = 2056 { 2057 & ia32_requirements_gp_gp, 2058 & ia32_requirements_gp_gp, 2059 & ia32_requirements__none, 2060 & ia32_requirements_xmm_xmm, 2061 & ia32_requirements_xmm_xmm, 2062 }; 2063 2064 /* construct in array */ 2065 in[0] = base; 2066 in[1] = index; 2067 in[2] = mem; 2068 in[3] = left; 2069 in[4] = right; 2070 2071 /* flags */ 2072 irn_flags_ |= arch_irn_flags_rematerializable; 2073 2074 /* create node */ 2075 assert(op != NULL); 2076 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 2077 2078 /* init node attributes */ 2079 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 2080 set_ia32_am_support(res, ia32_am_binary); 2081 info = be_get_info(res); 2082 (void) info; /* avoid potential warning */ 2083 info->out_infos[0].req = &ia32_requirements_xmm_in_r4_in_r5; 2084 info->out_infos[1].req = &ia32_requirements_flags_flags; 2085 info->out_infos[2].req = &ia32_requirements__none; 2086 2087 2088 /* optimize node */ 2089 res = optimize_node(res); 2090 irn_verify_irg(res, irg); 2091 2092 return res; 2093} 2094 2095/** 2096 * construct xPsllq node 2097 */ 2098ir_node *new_bd_ia32_xPsllq(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_node *op1) 2099{ 2100 ir_graph *irg = get_irn_irg(block); 2101 ir_op *op = op_ia32_xPsllq; 2102 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 2103 ir_node *res; 2104 backend_info_t *info; 2105 int arity = 2; 2106 ir_node *in[2]; 2107 int n_res = 1; 2108 ir_mode *mode = mode_D; 2109 static const arch_register_req_t *in_reqs[] = 2110 { 2111 & ia32_requirements_xmm_xmm, 2112 & ia32_requirements_xmm_xmm, 2113 }; 2114 2115 /* construct in array */ 2116 in[0] = op0; 2117 in[1] = op1; 2118 2119 /* flags */ 2120 irn_flags_ |= arch_irn_flags_rematerializable; 2121 2122 /* create node */ 2123 assert(op != NULL); 2124 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 2125 2126 /* init node attributes */ 2127 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 2128 2129 info = be_get_info(res); 2130 (void) info; /* avoid potential warning */ 2131 info->out_infos[0].req = &ia32_requirements_xmm_in_r1_not_in_r2; 2132 2133 2134 /* optimize node */ 2135 res = optimize_node(res); 2136 irn_verify_irg(res, irg); 2137 2138 return res; 2139} 2140 2141/** 2142 * construct xxStore node 2143 */ 2144ir_node *new_bd_ia32_xxStore(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val) 2145{ 2146 ir_graph *irg = get_irn_irg(block); 2147 ir_op *op = op_ia32_xxStore; 2148 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 2149 ir_node *res; 2150 backend_info_t *info; 2151 int arity = 4; 2152 ir_node *in[4]; 2153 int n_res = 3; 2154 ir_mode *mode = mode_T; 2155 static const arch_register_req_t *in_reqs[] = 2156 { 2157 & ia32_requirements_gp_gp, 2158 & ia32_requirements_gp_gp, 2159 & ia32_requirements__none, 2160 & ia32_requirements_xmm_xmm, 2161 }; 2162 2163 /* construct in array */ 2164 in[0] = base; 2165 in[1] = index; 2166 in[2] = mem; 2167 in[3] = val; 2168 2169 /* create node */ 2170 assert(op != NULL); 2171 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 2172 2173 /* init node attributes */ 2174 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 2175 2176 info = be_get_info(res); 2177 (void) info; /* avoid potential warning */ 2178 info->out_infos[0].req = &ia32_requirements__none; 2179 info->out_infos[1].req = &ia32_requirements__none; 2180 info->out_infos[2].req = &ia32_requirements__none; 2181 2182 2183 /* optimize node */ 2184 res = optimize_node(res); 2185 irn_verify_irg(res, irg); 2186 2187 return res; 2188} 2189 2190/** 2191 * construct Call node 2192 */ 2193ir_node *new_bd_ia32_Call(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *addr, ir_node *stack, ir_node *fpcw, ir_node *eax, ir_node *ecx, ir_node *edx, unsigned pop, ir_type *call_tp) 2194{ 2195 ir_graph *irg = get_irn_irg(block); 2196 ir_op *op = op_ia32_Call; 2197 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 2198 ir_node *res; 2199 backend_info_t *info; 2200 int arity = 9; 2201 ir_node *in[9]; 2202 int n_res = 24; 2203 ir_mode *mode = mode_T; 2204 static const arch_register_req_t *in_reqs[] = 2205 { 2206 & ia32_requirements_gp_gp, 2207 & ia32_requirements_gp_gp, 2208 & ia32_requirements__none, 2209 & ia32_requirements_gp_gp, 2210 & ia32_requirements_gp_esp, 2211 & ia32_requirements_fp_cw_fpcw, 2212 & ia32_requirements_gp_eax, 2213 & ia32_requirements_gp_ecx, 2214 & ia32_requirements_gp_edx, 2215 }; 2216 2217 /* construct in array */ 2218 in[0] = base; 2219 in[1] = index; 2220 in[2] = mem; 2221 in[3] = addr; 2222 in[4] = stack; 2223 in[5] = fpcw; 2224 in[6] = eax; 2225 in[7] = ecx; 2226 in[8] = edx; 2227 2228 /* create node */ 2229 assert(op != NULL); 2230 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 2231 2232 /* init node attributes */ 2233 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 2234 init_ia32_call_attributes(res, pop, call_tp); 2235 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 2236 set_ia32_am_support(res, ia32_am_unary); 2237 info = be_get_info(res); 2238 (void) info; /* avoid potential warning */ 2239 info->out_infos[0].req = &ia32_requirements_gp_esp_I_S; 2240 info->out_infos[1].req = &ia32_requirements_fp_cw_fpcw_I; 2241 info->out_infos[2].req = &ia32_requirements__none; 2242 info->out_infos[3].req = &ia32_requirements_gp_eax; 2243 info->out_infos[4].req = &ia32_requirements_gp_ecx; 2244 info->out_infos[5].req = &ia32_requirements_gp_edx; 2245 info->out_infos[6].req = &ia32_requirements_fp_st0; 2246 info->out_infos[7].req = &ia32_requirements_fp_st1; 2247 info->out_infos[8].req = &ia32_requirements_fp_st2; 2248 info->out_infos[9].req = &ia32_requirements_fp_st3; 2249 info->out_infos[10].req = &ia32_requirements_fp_st4; 2250 info->out_infos[11].req = &ia32_requirements_fp_st5; 2251 info->out_infos[12].req = &ia32_requirements_fp_st6; 2252 info->out_infos[13].req = &ia32_requirements_fp_st7; 2253 info->out_infos[14].req = &ia32_requirements_xmm_xmm0; 2254 info->out_infos[15].req = &ia32_requirements_xmm_xmm1; 2255 info->out_infos[16].req = &ia32_requirements_xmm_xmm2; 2256 info->out_infos[17].req = &ia32_requirements_xmm_xmm3; 2257 info->out_infos[18].req = &ia32_requirements_xmm_xmm4; 2258 info->out_infos[19].req = &ia32_requirements_xmm_xmm5; 2259 info->out_infos[20].req = &ia32_requirements_xmm_xmm6; 2260 info->out_infos[21].req = &ia32_requirements_xmm_xmm7; 2261 info->out_infos[22].req = &ia32_requirements__none; 2262 info->out_infos[23].req = &ia32_requirements__none; 2263 2264 2265 /* optimize node */ 2266 res = optimize_node(res); 2267 irn_verify_irg(res, irg); 2268 2269 return res; 2270} 2271 2272/** 2273 * construct FnstCWNOP node 2274 */ 2275ir_node *new_bd_ia32_FnstCWNOP(dbg_info *dbgi, ir_node *block, ir_node *fpcw) 2276{ 2277 ir_graph *irg = get_irn_irg(block); 2278 ir_op *op = op_ia32_FnstCWNOP; 2279 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 2280 ir_node *res; 2281 backend_info_t *info; 2282 int arity = 1; 2283 ir_node *in[1]; 2284 int n_res = 1; 2285 ir_mode *mode = mode_M; 2286 static const arch_register_req_t *in_reqs[] = 2287 { 2288 & ia32_requirements_fp_cw_fp_cw, 2289 }; 2290 2291 /* construct in array */ 2292 in[0] = fpcw; 2293 2294 /* create node */ 2295 assert(op != NULL); 2296 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 2297 2298 /* init node attributes */ 2299 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 2300 2301 info = be_get_info(res); 2302 (void) info; /* avoid potential warning */ 2303 info->out_infos[0].req = &ia32_requirements__none; 2304 2305 2306 /* optimize node */ 2307 res = optimize_node(res); 2308 irn_verify_irg(res, irg); 2309 2310 return res; 2311} 2312 2313/** 2314 * construct XorMem8Bit node 2315 */ 2316ir_node *new_bd_ia32_XorMem8Bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val) 2317{ 2318 ir_graph *irg = get_irn_irg(block); 2319 ir_op *op = op_ia32_XorMem8Bit; 2320 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 2321 ir_node *res; 2322 backend_info_t *info; 2323 int arity = 4; 2324 ir_node *in[4]; 2325 int n_res = 1; 2326 ir_mode *mode = mode_M; 2327 static const arch_register_req_t *in_reqs[] = 2328 { 2329 & ia32_requirements_gp_gp, 2330 & ia32_requirements_gp_gp, 2331 & ia32_requirements__none, 2332 & ia32_requirements_gp_eax_ebx_ecx_edx, 2333 }; 2334 2335 /* construct in array */ 2336 in[0] = base; 2337 in[1] = index; 2338 in[2] = mem; 2339 in[3] = val; 2340 2341 /* flags */ 2342 irn_flags_ |= arch_irn_flags_rematerializable; 2343 2344 /* create node */ 2345 assert(op != NULL); 2346 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 2347 2348 /* init node attributes */ 2349 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 2350 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 2351 2352 info = be_get_info(res); 2353 (void) info; /* avoid potential warning */ 2354 info->out_infos[0].req = &ia32_requirements__none; 2355 2356 2357 /* optimize node */ 2358 res = optimize_node(res); 2359 irn_verify_irg(res, irg); 2360 2361 return res; 2362} 2363 2364/** 2365 * construct fldl2t node 2366 */ 2367ir_node *new_bd_ia32_fldl2t(dbg_info *dbgi, ir_node *block) 2368{ 2369 ir_graph *irg = get_irn_irg(block); 2370 ir_op *op = op_ia32_fldl2t; 2371 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 2372 ir_node *res; 2373 backend_info_t *info; 2374 int arity = 0; 2375 ir_node **in = NULL; 2376 int n_res = 1; 2377 ir_mode *mode = ia32_mode_E; 2378 static const arch_register_req_t **in_reqs = NULL; 2379 2380 /* flags */ 2381 irn_flags_ |= arch_irn_flags_rematerializable; 2382 2383 /* create node */ 2384 assert(op != NULL); 2385 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 2386 2387 /* init node attributes */ 2388 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 2389 init_ia32_x87_attributes(res); 2390 2391 info = be_get_info(res); 2392 (void) info; /* avoid potential warning */ 2393 info->out_infos[0].req = &ia32_requirements_fp_fp; 2394 2395 2396 /* optimize node */ 2397 res = optimize_node(res); 2398 irn_verify_irg(res, irg); 2399 2400 return res; 2401} 2402 2403/** 2404 * construct fisttp node 2405 */ 2406ir_node *new_bd_ia32_fisttp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val) 2407{ 2408 ir_graph *irg = get_irn_irg(block); 2409 ir_op *op = op_ia32_fisttp; 2410 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 2411 ir_node *res; 2412 backend_info_t *info; 2413 int arity = 4; 2414 ir_node *in[4]; 2415 int n_res = 4; 2416 ir_mode *mode = mode_T; 2417 static const arch_register_req_t *in_reqs[] = 2418 { 2419 & ia32_requirements_gp_gp, 2420 & ia32_requirements_gp_gp, 2421 & ia32_requirements__none, 2422 & ia32_requirements_fp_fp, 2423 }; 2424 2425 /* construct in array */ 2426 in[0] = base; 2427 in[1] = index; 2428 in[2] = mem; 2429 in[3] = val; 2430 2431 /* create node */ 2432 assert(op != NULL); 2433 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 2434 2435 /* init node attributes */ 2436 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 2437 init_ia32_x87_attributes(res); 2438 2439 info = be_get_info(res); 2440 (void) info; /* avoid potential warning */ 2441 info->out_infos[0].req = &ia32_requirements_fp_in_r4; 2442 info->out_infos[1].req = &ia32_requirements__none; 2443 info->out_infos[2].req = &ia32_requirements__none; 2444 info->out_infos[3].req = &ia32_requirements__none; 2445 2446 2447 /* optimize node */ 2448 res = optimize_node(res); 2449 irn_verify_irg(res, irg); 2450 2451 return res; 2452} 2453 2454/** 2455 * construct DecMem node 2456 */ 2457ir_node *new_bd_ia32_DecMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem) 2458{ 2459 ir_graph *irg = get_irn_irg(block); 2460 ir_op *op = op_ia32_DecMem; 2461 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 2462 ir_node *res; 2463 backend_info_t *info; 2464 int arity = 3; 2465 ir_node *in[3]; 2466 int n_res = 1; 2467 ir_mode *mode = mode_M; 2468 static const arch_register_req_t *in_reqs[] = 2469 { 2470 & ia32_requirements_gp_gp, 2471 & ia32_requirements_gp_gp, 2472 & ia32_requirements__none, 2473 }; 2474 2475 /* construct in array */ 2476 in[0] = base; 2477 in[1] = index; 2478 in[2] = mem; 2479 2480 /* flags */ 2481 irn_flags_ |= arch_irn_flags_rematerializable; 2482 2483 /* create node */ 2484 assert(op != NULL); 2485 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 2486 2487 /* init node attributes */ 2488 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 2489 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 2490 2491 info = be_get_info(res); 2492 (void) info; /* avoid potential warning */ 2493 info->out_infos[0].req = &ia32_requirements__none; 2494 2495 2496 /* optimize node */ 2497 res = optimize_node(res); 2498 irn_verify_irg(res, irg); 2499 2500 return res; 2501} 2502 2503/** 2504 * construct emms node 2505 */ 2506ir_node *new_bd_ia32_emms(dbg_info *dbgi, ir_node *block) 2507{ 2508 ir_graph *irg = get_irn_irg(block); 2509 ir_op *op = op_ia32_emms; 2510 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 2511 ir_node *res; 2512 backend_info_t *info; 2513 int arity = 0; 2514 ir_node **in = NULL; 2515 int n_res = 1; 2516 ir_mode *mode = mode_ANY; 2517 static const arch_register_req_t **in_reqs = NULL; 2518 2519 /* create node */ 2520 assert(op != NULL); 2521 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 2522 2523 /* init node attributes */ 2524 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 2525 init_ia32_x87_attributes(res); 2526 2527 info = be_get_info(res); 2528 (void) info; /* avoid potential warning */ 2529 info->out_infos[0].req = &ia32_requirements__none; 2530 2531 2532 /* optimize node */ 2533 res = optimize_node(res); 2534 irn_verify_irg(res, irg); 2535 2536 return res; 2537} 2538 2539/** 2540 * construct xLoad node 2541 */ 2542ir_node *new_bd_ia32_xLoad(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_mode *load_mode) 2543{ 2544 ir_graph *irg = get_irn_irg(block); 2545 ir_op *op = op_ia32_xLoad; 2546 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 2547 ir_node *res; 2548 backend_info_t *info; 2549 int arity = 3; 2550 ir_node *in[3]; 2551 int n_res = 5; 2552 ir_mode *mode = mode_T; 2553 static const arch_register_req_t *in_reqs[] = 2554 { 2555 & ia32_requirements_gp_gp, 2556 & ia32_requirements_gp_gp, 2557 & ia32_requirements__none, 2558 }; 2559 ia32_attr_t *attr; 2560 2561 /* construct in array */ 2562 in[0] = base; 2563 in[1] = index; 2564 in[2] = mem; 2565 2566 /* create node */ 2567 assert(op != NULL); 2568 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 2569 2570 /* init node attributes */ 2571 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 2572 2573 info = be_get_info(res); 2574 (void) info; /* avoid potential warning */ 2575 info->out_infos[0].req = &ia32_requirements_xmm_xmm; 2576 info->out_infos[1].req = &ia32_requirements__none; 2577 info->out_infos[2].req = &ia32_requirements__none; 2578 info->out_infos[3].req = &ia32_requirements__none; 2579 info->out_infos[4].req = &ia32_requirements__none; 2580 2581 2582 attr = (ia32_attr_t*)get_irn_generic_attr(res); 2583 (void) attr; /* avoid potential warning */ 2584 attr->ls_mode = load_mode; 2585 /* optimize node */ 2586 res = optimize_node(res); 2587 irn_verify_irg(res, irg); 2588 2589 return res; 2590} 2591 2592/** 2593 * construct l_FloattoLL node 2594 */ 2595ir_node *new_bd_ia32_l_FloattoLL(dbg_info *dbgi, ir_node *block, ir_node *val) 2596{ 2597 ir_graph *irg = get_irn_irg(block); 2598 ir_op *op = op_ia32_l_FloattoLL; 2599 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 2600 ir_node *res; 2601 backend_info_t *info; 2602 int arity = 1; 2603 ir_node *in[1]; 2604 int n_res = 2; 2605 ir_mode *mode = mode_T; 2606 static const arch_register_req_t **in_reqs = NULL; 2607 2608 /* construct in array */ 2609 in[0] = val; 2610 2611 /* create node */ 2612 assert(op != NULL); 2613 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 2614 2615 /* init node attributes */ 2616 (void)in;(void)irn_flags_;(void)in_reqs;(void)n_res; 2617 2618 info = be_get_info(res); 2619 (void) info; /* avoid potential warning */ 2620 2621 2622 /* optimize node */ 2623 res = optimize_node(res); 2624 irn_verify_irg(res, irg); 2625 2626 return res; 2627} 2628 2629/** 2630 * construct CvtSI2SD node 2631 */ 2632ir_node *new_bd_ia32_CvtSI2SD(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val) 2633{ 2634 ir_graph *irg = get_irn_irg(block); 2635 ir_op *op = op_ia32_CvtSI2SD; 2636 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 2637 ir_node *res; 2638 backend_info_t *info; 2639 int arity = 4; 2640 ir_node *in[4]; 2641 int n_res = 1; 2642 ir_mode *mode = mode_D; 2643 static const arch_register_req_t *in_reqs[] = 2644 { 2645 & ia32_requirements_gp_gp, 2646 & ia32_requirements_gp_gp, 2647 & ia32_requirements__none, 2648 & ia32_requirements_gp_gp, 2649 }; 2650 2651 /* construct in array */ 2652 in[0] = base; 2653 in[1] = index; 2654 in[2] = mem; 2655 in[3] = val; 2656 2657 /* create node */ 2658 assert(op != NULL); 2659 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 2660 2661 /* init node attributes */ 2662 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 2663 set_ia32_am_support(res, ia32_am_unary); 2664 info = be_get_info(res); 2665 (void) info; /* avoid potential warning */ 2666 info->out_infos[0].req = &ia32_requirements_xmm_xmm; 2667 2668 2669 /* optimize node */ 2670 res = optimize_node(res); 2671 irn_verify_irg(res, irg); 2672 2673 return res; 2674} 2675 2676/** 2677 * construct XorMem node 2678 */ 2679ir_node *new_bd_ia32_XorMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val) 2680{ 2681 ir_graph *irg = get_irn_irg(block); 2682 ir_op *op = op_ia32_XorMem; 2683 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 2684 ir_node *res; 2685 backend_info_t *info; 2686 int arity = 4; 2687 ir_node *in[4]; 2688 int n_res = 1; 2689 ir_mode *mode = mode_M; 2690 static const arch_register_req_t *in_reqs[] = 2691 { 2692 & ia32_requirements_gp_gp, 2693 & ia32_requirements_gp_gp, 2694 & ia32_requirements__none, 2695 & ia32_requirements_gp_gp, 2696 }; 2697 2698 /* construct in array */ 2699 in[0] = base; 2700 in[1] = index; 2701 in[2] = mem; 2702 in[3] = val; 2703 2704 /* flags */ 2705 irn_flags_ |= arch_irn_flags_rematerializable; 2706 2707 /* create node */ 2708 assert(op != NULL); 2709 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 2710 2711 /* init node attributes */ 2712 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 2713 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 2714 2715 info = be_get_info(res); 2716 (void) info; /* avoid potential warning */ 2717 info->out_infos[0].req = &ia32_requirements__none; 2718 2719 2720 /* optimize node */ 2721 res = optimize_node(res); 2722 irn_verify_irg(res, irg); 2723 2724 return res; 2725} 2726 2727/** 2728 * construct CopyB node 2729 */ 2730ir_node *new_bd_ia32_CopyB(dbg_info *dbgi, ir_node *block, ir_node *dest, ir_node *source, ir_node *count, ir_node *mem, unsigned size) 2731{ 2732 ir_graph *irg = get_irn_irg(block); 2733 ir_op *op = op_ia32_CopyB; 2734 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 2735 ir_node *res; 2736 backend_info_t *info; 2737 int arity = 4; 2738 ir_node *in[4]; 2739 int n_res = 6; 2740 ir_mode *mode = mode_T; 2741 static const arch_register_req_t *in_reqs[] = 2742 { 2743 & ia32_requirements_gp_edi, 2744 & ia32_requirements_gp_esi, 2745 & ia32_requirements_gp_ecx, 2746 & ia32_requirements__none, 2747 }; 2748 2749 /* construct in array */ 2750 in[0] = dest; 2751 in[1] = source; 2752 in[2] = count; 2753 in[3] = mem; 2754 2755 /* create node */ 2756 assert(op != NULL); 2757 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 2758 2759 /* init node attributes */ 2760 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 2761 init_ia32_copyb_attributes(res, size); 2762 2763 info = be_get_info(res); 2764 (void) info; /* avoid potential warning */ 2765 info->out_infos[0].req = &ia32_requirements_gp_edi; 2766 info->out_infos[1].req = &ia32_requirements_gp_esi; 2767 info->out_infos[2].req = &ia32_requirements_gp_ecx; 2768 info->out_infos[3].req = &ia32_requirements__none; 2769 info->out_infos[4].req = &ia32_requirements__none; 2770 info->out_infos[5].req = &ia32_requirements__none; 2771 2772 2773 /* optimize node */ 2774 res = optimize_node(res); 2775 irn_verify_irg(res, irg); 2776 2777 return res; 2778} 2779 2780/** 2781 * construct Xor0 node 2782 */ 2783ir_node *new_bd_ia32_Xor0(dbg_info *dbgi, ir_node *block) 2784{ 2785 ir_graph *irg = get_irn_irg(block); 2786 ir_op *op = op_ia32_Xor0; 2787 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 2788 ir_node *res; 2789 backend_info_t *info; 2790 int arity = 0; 2791 ir_node **in = NULL; 2792 int n_res = 2; 2793 ir_mode *mode = mode_Iu; 2794 static const arch_register_req_t **in_reqs = NULL; 2795 2796 /* flags */ 2797 irn_flags_ |= arch_irn_flags_rematerializable; 2798 2799 /* create node */ 2800 assert(op != NULL); 2801 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 2802 2803 /* init node attributes */ 2804 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 2805 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 2806 2807 info = be_get_info(res); 2808 (void) info; /* avoid potential warning */ 2809 info->out_infos[0].req = &ia32_requirements_gp_gp; 2810 info->out_infos[1].req = &ia32_requirements_flags_flags; 2811 2812 2813 /* optimize node */ 2814 res = optimize_node(res); 2815 irn_verify_irg(res, irg); 2816 2817 return res; 2818} 2819 2820/** 2821 * construct Sar node 2822 */ 2823ir_node *new_bd_ia32_Sar(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count) 2824{ 2825 ir_graph *irg = get_irn_irg(block); 2826 ir_op *op = op_ia32_Sar; 2827 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 2828 ir_node *res; 2829 backend_info_t *info; 2830 int arity = 2; 2831 ir_node *in[2]; 2832 int n_res = 2; 2833 ir_mode *mode = mode_Iu; 2834 static const arch_register_req_t *in_reqs[] = 2835 { 2836 & ia32_requirements_gp_gp, 2837 & ia32_requirements_gp_ecx, 2838 }; 2839 2840 /* construct in array */ 2841 in[0] = val; 2842 in[1] = count; 2843 2844 /* flags */ 2845 irn_flags_ |= arch_irn_flags_rematerializable; 2846 2847 /* create node */ 2848 assert(op != NULL); 2849 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 2850 2851 /* init node attributes */ 2852 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 2853 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 2854 2855 info = be_get_info(res); 2856 (void) info; /* avoid potential warning */ 2857 info->out_infos[0].req = &ia32_requirements_gp_in_r1_not_in_r2; 2858 info->out_infos[1].req = &ia32_requirements_flags_flags; 2859 2860 2861 /* optimize node */ 2862 res = optimize_node(res); 2863 irn_verify_irg(res, irg); 2864 2865 return res; 2866} 2867 2868/** 2869 * construct Div node 2870 */ 2871ir_node *new_bd_ia32_Div(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *divisor, ir_node *dividend_low, ir_node *dividend_high) 2872{ 2873 ir_graph *irg = get_irn_irg(block); 2874 ir_op *op = op_ia32_Div; 2875 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 2876 ir_node *res; 2877 backend_info_t *info; 2878 int arity = 6; 2879 ir_node *in[6]; 2880 int n_res = 6; 2881 ir_mode *mode = mode_T; 2882 static const arch_register_req_t *in_reqs[] = 2883 { 2884 & ia32_requirements_gp_gp, 2885 & ia32_requirements_gp_gp, 2886 & ia32_requirements__none, 2887 & ia32_requirements_gp_gp, 2888 & ia32_requirements_gp_eax, 2889 & ia32_requirements_gp_edx, 2890 }; 2891 2892 /* construct in array */ 2893 in[0] = base; 2894 in[1] = index; 2895 in[2] = mem; 2896 in[3] = divisor; 2897 in[4] = dividend_low; 2898 in[5] = dividend_high; 2899 2900 /* create node */ 2901 assert(op != NULL); 2902 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 2903 2904 /* init node attributes */ 2905 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 2906 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 2907 set_ia32_am_support(res, ia32_am_unary); 2908 info = be_get_info(res); 2909 (void) info; /* avoid potential warning */ 2910 info->out_infos[0].req = &ia32_requirements_gp_eax; 2911 info->out_infos[1].req = &ia32_requirements_flags_flags; 2912 info->out_infos[2].req = &ia32_requirements__none; 2913 info->out_infos[3].req = &ia32_requirements_gp_edx; 2914 info->out_infos[4].req = &ia32_requirements__none; 2915 info->out_infos[5].req = &ia32_requirements__none; 2916 2917 2918 /* optimize node */ 2919 res = optimize_node(res); 2920 irn_verify_irg(res, irg); 2921 2922 return res; 2923} 2924 2925/** 2926 * construct fpushCopy node 2927 */ 2928ir_node *new_bd_ia32_fpushCopy(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_mode *mode) 2929{ 2930 ir_graph *irg = get_irn_irg(block); 2931 ir_op *op = op_ia32_fpushCopy; 2932 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 2933 ir_node *res; 2934 backend_info_t *info; 2935 int arity = 1; 2936 ir_node *in[1]; 2937 int n_res = 1; 2938 static const arch_register_req_t *in_reqs[] = 2939 { 2940 & ia32_requirements_fp_fp, 2941 }; 2942 2943 /* construct in array */ 2944 in[0] = op0; 2945 2946 /* create node */ 2947 assert(op != NULL); 2948 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 2949 2950 /* init node attributes */ 2951 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 2952 init_ia32_x87_attributes(res); 2953 2954 info = be_get_info(res); 2955 (void) info; /* avoid potential warning */ 2956 info->out_infos[0].req = &ia32_requirements_fp_fp; 2957 2958 2959 /* optimize node */ 2960 res = optimize_node(res); 2961 irn_verify_irg(res, irg); 2962 2963 return res; 2964} 2965 2966/** 2967 * construct Stc node 2968 */ 2969ir_node *new_bd_ia32_Stc(dbg_info *dbgi, ir_node *block) 2970{ 2971 ir_graph *irg = get_irn_irg(block); 2972 ir_op *op = op_ia32_Stc; 2973 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 2974 ir_node *res; 2975 backend_info_t *info; 2976 int arity = 0; 2977 ir_node **in = NULL; 2978 int n_res = 1; 2979 ir_mode *mode = mode_Iu; 2980 static const arch_register_req_t **in_reqs = NULL; 2981 2982 /* create node */ 2983 assert(op != NULL); 2984 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 2985 2986 /* init node attributes */ 2987 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 2988 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 2989 2990 info = be_get_info(res); 2991 (void) info; /* avoid potential warning */ 2992 info->out_infos[0].req = &ia32_requirements_flags_flags; 2993 2994 2995 /* optimize node */ 2996 res = optimize_node(res); 2997 irn_verify_irg(res, irg); 2998 2999 return res; 3000} 3001 3002/** 3003 * construct Fucomi node 3004 */ 3005ir_node *new_bd_ia32_Fucomi(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, bool ins_permuted) 3006{ 3007 ir_graph *irg = get_irn_irg(block); 3008 ir_op *op = op_ia32_Fucomi; 3009 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 3010 ir_node *res; 3011 backend_info_t *info; 3012 int arity = 2; 3013 ir_node *in[2]; 3014 int n_res = 1; 3015 ir_mode *mode = mode_Iu; 3016 static const arch_register_req_t *in_reqs[] = 3017 { 3018 & ia32_requirements_fp_fp, 3019 & ia32_requirements_fp_fp, 3020 }; 3021 ia32_x87_attr_t *attr; 3022 3023 /* construct in array */ 3024 in[0] = left; 3025 in[1] = right; 3026 3027 /* flags */ 3028 irn_flags_ |= arch_irn_flags_rematerializable; 3029 3030 /* create node */ 3031 assert(op != NULL); 3032 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 3033 3034 /* init node attributes */ 3035 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 3036 init_ia32_x87_attributes(res); 3037 3038 info = be_get_info(res); 3039 (void) info; /* avoid potential warning */ 3040 info->out_infos[0].req = &ia32_requirements_flags_eflags; 3041 3042 3043 attr = (ia32_x87_attr_t*)get_irn_generic_attr(res); 3044 (void) attr; /* avoid potential warning */ 3045 attr->attr.data.ins_permuted = ins_permuted; 3046 /* optimize node */ 3047 res = optimize_node(res); 3048 irn_verify_irg(res, irg); 3049 3050 return res; 3051} 3052 3053/** 3054 * construct fldl2e node 3055 */ 3056ir_node *new_bd_ia32_fldl2e(dbg_info *dbgi, ir_node *block) 3057{ 3058 ir_graph *irg = get_irn_irg(block); 3059 ir_op *op = op_ia32_fldl2e; 3060 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 3061 ir_node *res; 3062 backend_info_t *info; 3063 int arity = 0; 3064 ir_node **in = NULL; 3065 int n_res = 1; 3066 ir_mode *mode = ia32_mode_E; 3067 static const arch_register_req_t **in_reqs = NULL; 3068 3069 /* flags */ 3070 irn_flags_ |= arch_irn_flags_rematerializable; 3071 3072 /* create node */ 3073 assert(op != NULL); 3074 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 3075 3076 /* init node attributes */ 3077 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 3078 init_ia32_x87_attributes(res); 3079 3080 info = be_get_info(res); 3081 (void) info; /* avoid potential warning */ 3082 info->out_infos[0].req = &ia32_requirements_fp_fp; 3083 3084 3085 /* optimize node */ 3086 res = optimize_node(res); 3087 irn_verify_irg(res, irg); 3088 3089 return res; 3090} 3091 3092/** 3093 * construct Enter node 3094 */ 3095ir_node *new_bd_ia32_Enter(dbg_info *dbgi, ir_node *block, ir_node *op0) 3096{ 3097 ir_graph *irg = get_irn_irg(block); 3098 ir_op *op = op_ia32_Enter; 3099 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 3100 ir_node *res; 3101 backend_info_t *info; 3102 int arity = 1; 3103 ir_node *in[1]; 3104 int n_res = 3; 3105 ir_mode *mode = mode_T; 3106 static const arch_register_req_t *in_reqs[] = 3107 { 3108 & ia32_requirements_gp_esp, 3109 }; 3110 3111 /* construct in array */ 3112 in[0] = op0; 3113 3114 /* create node */ 3115 assert(op != NULL); 3116 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 3117 3118 /* init node attributes */ 3119 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 3120 3121 info = be_get_info(res); 3122 (void) info; /* avoid potential warning */ 3123 info->out_infos[0].req = &ia32_requirements_gp_ebp; 3124 info->out_infos[1].req = &ia32_requirements_gp_esp_I_S; 3125 info->out_infos[2].req = &ia32_requirements__none; 3126 3127 3128 /* optimize node */ 3129 res = optimize_node(res); 3130 irn_verify_irg(res, irg); 3131 3132 return res; 3133} 3134 3135/** 3136 * construct fmul node 3137 */ 3138ir_node *new_bd_ia32_fmul(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *fpcw) 3139{ 3140 ir_graph *irg = get_irn_irg(block); 3141 ir_op *op = op_ia32_fmul; 3142 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 3143 ir_node *res; 3144 backend_info_t *info; 3145 int arity = 6; 3146 ir_node *in[6]; 3147 int n_res = 3; 3148 ir_mode *mode = ia32_mode_E; 3149 static const arch_register_req_t *in_reqs[] = 3150 { 3151 & ia32_requirements_gp_gp, 3152 & ia32_requirements_gp_gp, 3153 & ia32_requirements__none, 3154 & ia32_requirements_fp_fp, 3155 & ia32_requirements_fp_fp, 3156 & ia32_requirements_fp_cw_fpcw, 3157 }; 3158 3159 /* construct in array */ 3160 in[0] = base; 3161 in[1] = index; 3162 in[2] = mem; 3163 in[3] = left; 3164 in[4] = right; 3165 in[5] = fpcw; 3166 3167 /* create node */ 3168 assert(op != NULL); 3169 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 3170 3171 /* init node attributes */ 3172 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 3173 init_ia32_x87_attributes(res); 3174 set_ia32_am_support(res, ia32_am_binary); 3175 info = be_get_info(res); 3176 (void) info; /* avoid potential warning */ 3177 info->out_infos[0].req = &ia32_requirements_fp_fp; 3178 info->out_infos[1].req = &ia32_requirements__none; 3179 info->out_infos[2].req = &ia32_requirements__none; 3180 3181 3182 /* optimize node */ 3183 res = optimize_node(res); 3184 irn_verify_irg(res, irg); 3185 3186 return res; 3187} 3188 3189/** 3190 * construct l_IMul node 3191 */ 3192ir_node *new_bd_ia32_l_IMul(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right) 3193{ 3194 ir_graph *irg = get_irn_irg(block); 3195 ir_op *op = op_ia32_l_IMul; 3196 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 3197 ir_node *res; 3198 backend_info_t *info; 3199 int arity = 2; 3200 ir_node *in[2]; 3201 int n_res = 4; 3202 ir_mode *mode = mode_T; 3203 static const arch_register_req_t **in_reqs = NULL; 3204 3205 /* construct in array */ 3206 in[0] = left; 3207 in[1] = right; 3208 3209 /* create node */ 3210 assert(op != NULL); 3211 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 3212 3213 /* init node attributes */ 3214 (void)in;(void)irn_flags_;(void)in_reqs;(void)n_res; 3215 3216 info = be_get_info(res); 3217 (void) info; /* avoid potential warning */ 3218 3219 3220 /* optimize node */ 3221 res = optimize_node(res); 3222 irn_verify_irg(res, irg); 3223 3224 return res; 3225} 3226 3227/** 3228 * construct NoReg_XMM node 3229 */ 3230ir_node *new_bd_ia32_NoReg_XMM(dbg_info *dbgi, ir_node *block) 3231{ 3232 ir_graph *irg = get_irn_irg(block); 3233 ir_op *op = op_ia32_NoReg_XMM; 3234 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 3235 ir_node *res; 3236 backend_info_t *info; 3237 int arity = 0; 3238 ir_node **in = NULL; 3239 int n_res = 1; 3240 ir_mode *mode = mode_D; 3241 static const arch_register_req_t **in_reqs = NULL; 3242 3243 /* flags */ 3244 irn_flags_ |= arch_irn_flags_not_scheduled; 3245 3246 /* create node */ 3247 assert(op != NULL); 3248 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 3249 3250 /* init node attributes */ 3251 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 3252 3253 info = be_get_info(res); 3254 (void) info; /* avoid potential warning */ 3255 info->out_infos[0].req = &ia32_requirements_xmm_xmm_NOREG_I; 3256 3257 3258 /* optimize node */ 3259 res = optimize_node(res); 3260 irn_verify_irg(res, irg); 3261 3262 return res; 3263} 3264 3265/** 3266 * construct xMax node 3267 */ 3268ir_node *new_bd_ia32_xMax(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right) 3269{ 3270 ir_graph *irg = get_irn_irg(block); 3271 ir_op *op = op_ia32_xMax; 3272 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 3273 ir_node *res; 3274 backend_info_t *info; 3275 int arity = 5; 3276 ir_node *in[5]; 3277 int n_res = 3; 3278 ir_mode *mode = mode_D; 3279 static const arch_register_req_t *in_reqs[] = 3280 { 3281 & ia32_requirements_gp_gp, 3282 & ia32_requirements_gp_gp, 3283 & ia32_requirements__none, 3284 & ia32_requirements_xmm_xmm, 3285 & ia32_requirements_xmm_xmm, 3286 }; 3287 3288 /* construct in array */ 3289 in[0] = base; 3290 in[1] = index; 3291 in[2] = mem; 3292 in[3] = left; 3293 in[4] = right; 3294 3295 /* flags */ 3296 irn_flags_ |= arch_irn_flags_rematerializable; 3297 3298 /* create node */ 3299 assert(op != NULL); 3300 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 3301 3302 /* init node attributes */ 3303 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 3304 set_ia32_am_support(res, ia32_am_binary); 3305 info = be_get_info(res); 3306 (void) info; /* avoid potential warning */ 3307 info->out_infos[0].req = &ia32_requirements_xmm_in_r4_in_r5; 3308 info->out_infos[1].req = &ia32_requirements_flags_flags; 3309 info->out_infos[2].req = &ia32_requirements__none; 3310 3311 3312 /* optimize node */ 3313 res = optimize_node(res); 3314 irn_verify_irg(res, irg); 3315 3316 return res; 3317} 3318 3319/** 3320 * construct OrMem8Bit node 3321 */ 3322ir_node *new_bd_ia32_OrMem8Bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val) 3323{ 3324 ir_graph *irg = get_irn_irg(block); 3325 ir_op *op = op_ia32_OrMem8Bit; 3326 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 3327 ir_node *res; 3328 backend_info_t *info; 3329 int arity = 4; 3330 ir_node *in[4]; 3331 int n_res = 1; 3332 ir_mode *mode = mode_M; 3333 static const arch_register_req_t *in_reqs[] = 3334 { 3335 & ia32_requirements_gp_gp, 3336 & ia32_requirements_gp_gp, 3337 & ia32_requirements__none, 3338 & ia32_requirements_gp_eax_ebx_ecx_edx, 3339 }; 3340 3341 /* construct in array */ 3342 in[0] = base; 3343 in[1] = index; 3344 in[2] = mem; 3345 in[3] = val; 3346 3347 /* flags */ 3348 irn_flags_ |= arch_irn_flags_rematerializable; 3349 3350 /* create node */ 3351 assert(op != NULL); 3352 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 3353 3354 /* init node attributes */ 3355 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 3356 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 3357 3358 info = be_get_info(res); 3359 (void) info; /* avoid potential warning */ 3360 info->out_infos[0].req = &ia32_requirements__none; 3361 3362 3363 /* optimize node */ 3364 res = optimize_node(res); 3365 irn_verify_irg(res, irg); 3366 3367 return res; 3368} 3369 3370/** 3371 * construct Prefetch1 node 3372 */ 3373ir_node *new_bd_ia32_Prefetch1(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem) 3374{ 3375 ir_graph *irg = get_irn_irg(block); 3376 ir_op *op = op_ia32_Prefetch1; 3377 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 3378 ir_node *res; 3379 backend_info_t *info; 3380 int arity = 3; 3381 ir_node *in[3]; 3382 int n_res = 1; 3383 ir_mode *mode = mode_T; 3384 static const arch_register_req_t *in_reqs[] = 3385 { 3386 & ia32_requirements_gp_gp, 3387 & ia32_requirements_gp_gp, 3388 & ia32_requirements__none, 3389 }; 3390 3391 /* construct in array */ 3392 in[0] = base; 3393 in[1] = index; 3394 in[2] = mem; 3395 3396 /* create node */ 3397 assert(op != NULL); 3398 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 3399 3400 /* init node attributes */ 3401 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 3402 3403 info = be_get_info(res); 3404 (void) info; /* avoid potential warning */ 3405 info->out_infos[0].req = &ia32_requirements__none; 3406 3407 3408 /* optimize node */ 3409 res = optimize_node(res); 3410 irn_verify_irg(res, irg); 3411 3412 return res; 3413} 3414 3415/** 3416 * construct fsub node 3417 */ 3418ir_node *new_bd_ia32_fsub(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *minuend, ir_node *subtrahend, ir_node *fpcw) 3419{ 3420 ir_graph *irg = get_irn_irg(block); 3421 ir_op *op = op_ia32_fsub; 3422 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 3423 ir_node *res; 3424 backend_info_t *info; 3425 int arity = 6; 3426 ir_node *in[6]; 3427 int n_res = 3; 3428 ir_mode *mode = ia32_mode_E; 3429 static const arch_register_req_t *in_reqs[] = 3430 { 3431 & ia32_requirements_gp_gp, 3432 & ia32_requirements_gp_gp, 3433 & ia32_requirements__none, 3434 & ia32_requirements_fp_fp, 3435 & ia32_requirements_fp_fp, 3436 & ia32_requirements_fp_cw_fpcw, 3437 }; 3438 3439 /* construct in array */ 3440 in[0] = base; 3441 in[1] = index; 3442 in[2] = mem; 3443 in[3] = minuend; 3444 in[4] = subtrahend; 3445 in[5] = fpcw; 3446 3447 /* create node */ 3448 assert(op != NULL); 3449 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 3450 3451 /* init node attributes */ 3452 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 3453 init_ia32_x87_attributes(res); 3454 set_ia32_am_support(res, ia32_am_binary); 3455 info = be_get_info(res); 3456 (void) info; /* avoid potential warning */ 3457 info->out_infos[0].req = &ia32_requirements_fp_fp; 3458 info->out_infos[1].req = &ia32_requirements__none; 3459 info->out_infos[2].req = &ia32_requirements__none; 3460 3461 3462 /* optimize node */ 3463 res = optimize_node(res); 3464 irn_verify_irg(res, irg); 3465 3466 return res; 3467} 3468 3469/** 3470 * construct Lea node 3471 */ 3472ir_node *new_bd_ia32_Lea(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index) 3473{ 3474 ir_graph *irg = get_irn_irg(block); 3475 ir_op *op = op_ia32_Lea; 3476 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 3477 ir_node *res; 3478 backend_info_t *info; 3479 int arity = 2; 3480 ir_node *in[2]; 3481 int n_res = 1; 3482 ir_mode *mode = mode_Iu; 3483 static const arch_register_req_t *in_reqs[] = 3484 { 3485 & ia32_requirements_gp_gp, 3486 & ia32_requirements_gp_gp, 3487 }; 3488 3489 /* construct in array */ 3490 in[0] = base; 3491 in[1] = index; 3492 3493 /* flags */ 3494 irn_flags_ |= arch_irn_flags_rematerializable; 3495 3496 /* create node */ 3497 assert(op != NULL); 3498 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 3499 3500 /* init node attributes */ 3501 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 3502 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 3503 3504 info = be_get_info(res); 3505 (void) info; /* avoid potential warning */ 3506 info->out_infos[0].req = &ia32_requirements_gp_gp; 3507 3508 3509 /* optimize node */ 3510 res = optimize_node(res); 3511 irn_verify_irg(res, irg); 3512 3513 return res; 3514} 3515 3516/** 3517 * construct FtstFnstsw node 3518 */ 3519ir_node *new_bd_ia32_FtstFnstsw(dbg_info *dbgi, ir_node *block, ir_node *left, bool ins_permuted) 3520{ 3521 ir_graph *irg = get_irn_irg(block); 3522 ir_op *op = op_ia32_FtstFnstsw; 3523 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 3524 ir_node *res; 3525 backend_info_t *info; 3526 int arity = 1; 3527 ir_node *in[1]; 3528 int n_res = 1; 3529 ir_mode *mode = mode_Iu; 3530 static const arch_register_req_t *in_reqs[] = 3531 { 3532 & ia32_requirements_fp_fp, 3533 }; 3534 ia32_x87_attr_t *attr; 3535 3536 /* construct in array */ 3537 in[0] = left; 3538 3539 /* create node */ 3540 assert(op != NULL); 3541 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 3542 3543 /* init node attributes */ 3544 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 3545 init_ia32_x87_attributes(res); 3546 3547 info = be_get_info(res); 3548 (void) info; /* avoid potential warning */ 3549 info->out_infos[0].req = &ia32_requirements_gp_eax; 3550 3551 3552 attr = (ia32_x87_attr_t*)get_irn_generic_attr(res); 3553 (void) attr; /* avoid potential warning */ 3554 attr->attr.data.ins_permuted = ins_permuted; 3555 /* optimize node */ 3556 res = optimize_node(res); 3557 irn_verify_irg(res, irg); 3558 3559 return res; 3560} 3561 3562/** 3563 * construct NotMem node 3564 */ 3565ir_node *new_bd_ia32_NotMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem) 3566{ 3567 ir_graph *irg = get_irn_irg(block); 3568 ir_op *op = op_ia32_NotMem; 3569 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 3570 ir_node *res; 3571 backend_info_t *info; 3572 int arity = 3; 3573 ir_node *in[3]; 3574 int n_res = 1; 3575 ir_mode *mode = mode_M; 3576 static const arch_register_req_t *in_reqs[] = 3577 { 3578 & ia32_requirements_gp_gp, 3579 & ia32_requirements_gp_gp, 3580 & ia32_requirements__none, 3581 }; 3582 3583 /* construct in array */ 3584 in[0] = base; 3585 in[1] = index; 3586 in[2] = mem; 3587 3588 /* flags */ 3589 irn_flags_ |= arch_irn_flags_rematerializable; 3590 3591 /* create node */ 3592 assert(op != NULL); 3593 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 3594 3595 /* init node attributes */ 3596 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 3597 3598 info = be_get_info(res); 3599 (void) info; /* avoid potential warning */ 3600 info->out_infos[0].req = &ia32_requirements__none; 3601 3602 3603 /* optimize node */ 3604 res = optimize_node(res); 3605 irn_verify_irg(res, irg); 3606 3607 return res; 3608} 3609 3610/** 3611 * construct Sbb0 node 3612 */ 3613ir_node *new_bd_ia32_Sbb0(dbg_info *dbgi, ir_node *block, ir_node *op0) 3614{ 3615 ir_graph *irg = get_irn_irg(block); 3616 ir_op *op = op_ia32_Sbb0; 3617 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 3618 ir_node *res; 3619 backend_info_t *info; 3620 int arity = 1; 3621 ir_node *in[1]; 3622 int n_res = 2; 3623 ir_mode *mode = mode_Iu; 3624 static const arch_register_req_t *in_reqs[] = 3625 { 3626 & ia32_requirements_flags_flags, 3627 }; 3628 3629 /* construct in array */ 3630 in[0] = op0; 3631 3632 /* create node */ 3633 assert(op != NULL); 3634 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 3635 3636 /* init node attributes */ 3637 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 3638 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 3639 3640 info = be_get_info(res); 3641 (void) info; /* avoid potential warning */ 3642 info->out_infos[0].req = &ia32_requirements_gp_gp; 3643 info->out_infos[1].req = &ia32_requirements_flags_flags; 3644 3645 3646 /* optimize node */ 3647 res = optimize_node(res); 3648 irn_verify_irg(res, irg); 3649 3650 return res; 3651} 3652 3653/** 3654 * construct Bt node 3655 */ 3656ir_node *new_bd_ia32_Bt(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right) 3657{ 3658 ir_graph *irg = get_irn_irg(block); 3659 ir_op *op = op_ia32_Bt; 3660 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 3661 ir_node *res; 3662 backend_info_t *info; 3663 int arity = 2; 3664 ir_node *in[2]; 3665 int n_res = 1; 3666 ir_mode *mode = mode_Iu; 3667 static const arch_register_req_t *in_reqs[] = 3668 { 3669 & ia32_requirements_gp_gp, 3670 & ia32_requirements_gp_gp, 3671 }; 3672 3673 /* construct in array */ 3674 in[0] = left; 3675 in[1] = right; 3676 3677 /* flags */ 3678 irn_flags_ |= arch_irn_flags_rematerializable; 3679 3680 /* create node */ 3681 assert(op != NULL); 3682 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 3683 3684 /* init node attributes */ 3685 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 3686 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 3687 3688 info = be_get_info(res); 3689 (void) info; /* avoid potential warning */ 3690 info->out_infos[0].req = &ia32_requirements_flags_flags; 3691 3692 3693 /* optimize node */ 3694 res = optimize_node(res); 3695 irn_verify_irg(res, irg); 3696 3697 return res; 3698} 3699 3700/** 3701 * construct Or node 3702 */ 3703ir_node *new_bd_ia32_Or(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right) 3704{ 3705 ir_graph *irg = get_irn_irg(block); 3706 ir_op *op = op_ia32_Or; 3707 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 3708 ir_node *res; 3709 backend_info_t *info; 3710 int arity = 5; 3711 ir_node *in[5]; 3712 int n_res = 3; 3713 ir_mode *mode = mode_Iu; 3714 static const arch_register_req_t *in_reqs[] = 3715 { 3716 & ia32_requirements_gp_gp, 3717 & ia32_requirements_gp_gp, 3718 & ia32_requirements__none, 3719 & ia32_requirements_gp_gp, 3720 & ia32_requirements_gp_gp, 3721 }; 3722 3723 /* construct in array */ 3724 in[0] = base; 3725 in[1] = index; 3726 in[2] = mem; 3727 in[3] = left; 3728 in[4] = right; 3729 3730 /* flags */ 3731 irn_flags_ |= arch_irn_flags_rematerializable; 3732 3733 /* create node */ 3734 assert(op != NULL); 3735 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 3736 3737 /* init node attributes */ 3738 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 3739 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 3740 set_ia32_am_support(res, ia32_am_binary); 3741 info = be_get_info(res); 3742 (void) info; /* avoid potential warning */ 3743 info->out_infos[0].req = &ia32_requirements_gp_in_r4_in_r5; 3744 info->out_infos[1].req = &ia32_requirements_flags_flags; 3745 info->out_infos[2].req = &ia32_requirements__none; 3746 3747 3748 /* optimize node */ 3749 res = optimize_node(res); 3750 irn_verify_irg(res, irg); 3751 3752 return res; 3753} 3754 3755/** 3756 * construct Xor node 3757 */ 3758ir_node *new_bd_ia32_Xor(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right) 3759{ 3760 ir_graph *irg = get_irn_irg(block); 3761 ir_op *op = op_ia32_Xor; 3762 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 3763 ir_node *res; 3764 backend_info_t *info; 3765 int arity = 5; 3766 ir_node *in[5]; 3767 int n_res = 3; 3768 ir_mode *mode = mode_Iu; 3769 static const arch_register_req_t *in_reqs[] = 3770 { 3771 & ia32_requirements_gp_gp, 3772 & ia32_requirements_gp_gp, 3773 & ia32_requirements__none, 3774 & ia32_requirements_gp_gp, 3775 & ia32_requirements_gp_gp, 3776 }; 3777 3778 /* construct in array */ 3779 in[0] = base; 3780 in[1] = index; 3781 in[2] = mem; 3782 in[3] = left; 3783 in[4] = right; 3784 3785 /* flags */ 3786 irn_flags_ |= arch_irn_flags_rematerializable; 3787 3788 /* create node */ 3789 assert(op != NULL); 3790 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 3791 3792 /* init node attributes */ 3793 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 3794 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 3795 set_ia32_am_support(res, ia32_am_binary); 3796 info = be_get_info(res); 3797 (void) info; /* avoid potential warning */ 3798 info->out_infos[0].req = &ia32_requirements_gp_in_r4_in_r5; 3799 info->out_infos[1].req = &ia32_requirements_flags_flags; 3800 info->out_infos[2].req = &ia32_requirements__none; 3801 3802 3803 /* optimize node */ 3804 res = optimize_node(res); 3805 irn_verify_irg(res, irg); 3806 3807 return res; 3808} 3809 3810/** 3811 * construct CopyB_i node 3812 */ 3813ir_node *new_bd_ia32_CopyB_i(dbg_info *dbgi, ir_node *block, ir_node *dest, ir_node *source, ir_node *mem, unsigned size) 3814{ 3815 ir_graph *irg = get_irn_irg(block); 3816 ir_op *op = op_ia32_CopyB_i; 3817 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 3818 ir_node *res; 3819 backend_info_t *info; 3820 int arity = 3; 3821 ir_node *in[3]; 3822 int n_res = 5; 3823 ir_mode *mode = mode_T; 3824 static const arch_register_req_t *in_reqs[] = 3825 { 3826 & ia32_requirements_gp_edi, 3827 & ia32_requirements_gp_esi, 3828 & ia32_requirements__none, 3829 }; 3830 3831 /* construct in array */ 3832 in[0] = dest; 3833 in[1] = source; 3834 in[2] = mem; 3835 3836 /* create node */ 3837 assert(op != NULL); 3838 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 3839 3840 /* init node attributes */ 3841 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 3842 init_ia32_copyb_attributes(res, size); 3843 3844 info = be_get_info(res); 3845 (void) info; /* avoid potential warning */ 3846 info->out_infos[0].req = &ia32_requirements_gp_edi; 3847 info->out_infos[1].req = &ia32_requirements_gp_esi; 3848 info->out_infos[2].req = &ia32_requirements__none; 3849 info->out_infos[3].req = &ia32_requirements__none; 3850 info->out_infos[4].req = &ia32_requirements__none; 3851 3852 3853 /* optimize node */ 3854 res = optimize_node(res); 3855 irn_verify_irg(res, irg); 3856 3857 return res; 3858} 3859 3860/** 3861 * construct IncMem node 3862 */ 3863ir_node *new_bd_ia32_IncMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem) 3864{ 3865 ir_graph *irg = get_irn_irg(block); 3866 ir_op *op = op_ia32_IncMem; 3867 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 3868 ir_node *res; 3869 backend_info_t *info; 3870 int arity = 3; 3871 ir_node *in[3]; 3872 int n_res = 1; 3873 ir_mode *mode = mode_M; 3874 static const arch_register_req_t *in_reqs[] = 3875 { 3876 & ia32_requirements_gp_gp, 3877 & ia32_requirements_gp_gp, 3878 & ia32_requirements__none, 3879 }; 3880 3881 /* construct in array */ 3882 in[0] = base; 3883 in[1] = index; 3884 in[2] = mem; 3885 3886 /* flags */ 3887 irn_flags_ |= arch_irn_flags_rematerializable; 3888 3889 /* create node */ 3890 assert(op != NULL); 3891 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 3892 3893 /* init node attributes */ 3894 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 3895 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 3896 3897 info = be_get_info(res); 3898 (void) info; /* avoid potential warning */ 3899 info->out_infos[0].req = &ia32_requirements__none; 3900 3901 3902 /* optimize node */ 3903 res = optimize_node(res); 3904 irn_verify_irg(res, irg); 3905 3906 return res; 3907} 3908 3909/** 3910 * construct xAllOnes node 3911 */ 3912ir_node *new_bd_ia32_xAllOnes(dbg_info *dbgi, ir_node *block) 3913{ 3914 ir_graph *irg = get_irn_irg(block); 3915 ir_op *op = op_ia32_xAllOnes; 3916 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 3917 ir_node *res; 3918 backend_info_t *info; 3919 int arity = 0; 3920 ir_node **in = NULL; 3921 int n_res = 1; 3922 ir_mode *mode = mode_D; 3923 static const arch_register_req_t **in_reqs = NULL; 3924 3925 /* flags */ 3926 irn_flags_ |= arch_irn_flags_rematerializable; 3927 3928 /* create node */ 3929 assert(op != NULL); 3930 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 3931 3932 /* init node attributes */ 3933 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 3934 3935 info = be_get_info(res); 3936 (void) info; /* avoid potential warning */ 3937 info->out_infos[0].req = &ia32_requirements_xmm_xmm; 3938 3939 3940 /* optimize node */ 3941 res = optimize_node(res); 3942 irn_verify_irg(res, irg); 3943 3944 return res; 3945} 3946 3947/** 3948 * construct Breakpoint node 3949 */ 3950ir_node *new_bd_ia32_Breakpoint(dbg_info *dbgi, ir_node *block, ir_node *mem) 3951{ 3952 ir_graph *irg = get_irn_irg(block); 3953 ir_op *op = op_ia32_Breakpoint; 3954 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 3955 ir_node *res; 3956 backend_info_t *info; 3957 int arity = 1; 3958 ir_node *in[1]; 3959 int n_res = 1; 3960 ir_mode *mode = mode_M; 3961 static const arch_register_req_t *in_reqs[] = 3962 { 3963 & ia32_requirements__none, 3964 }; 3965 3966 /* construct in array */ 3967 in[0] = mem; 3968 3969 /* create node */ 3970 assert(op != NULL); 3971 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 3972 3973 /* init node attributes */ 3974 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 3975 3976 info = be_get_info(res); 3977 (void) info; /* avoid potential warning */ 3978 info->out_infos[0].req = &ia32_requirements__none; 3979 3980 3981 /* optimize node */ 3982 res = optimize_node(res); 3983 irn_verify_irg(res, irg); 3984 3985 return res; 3986} 3987 3988/** 3989 * construct ClimbFrame node 3990 */ 3991ir_node *new_bd_ia32_ClimbFrame(dbg_info *dbgi, ir_node *block, ir_node *frame, ir_node *cnt, ir_node *tmp, unsigned count) 3992{ 3993 ir_graph *irg = get_irn_irg(block); 3994 ir_op *op = op_ia32_ClimbFrame; 3995 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 3996 ir_node *res; 3997 backend_info_t *info; 3998 int arity = 3; 3999 ir_node *in[3]; 4000 int n_res = 1; 4001 ir_mode *mode = mode_Iu; 4002 static const arch_register_req_t *in_reqs[] = 4003 { 4004 & ia32_requirements_gp_gp, 4005 & ia32_requirements_gp_gp, 4006 & ia32_requirements_gp_gp, 4007 }; 4008 4009 /* construct in array */ 4010 in[0] = frame; 4011 in[1] = cnt; 4012 in[2] = tmp; 4013 4014 /* create node */ 4015 assert(op != NULL); 4016 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 4017 4018 /* init node attributes */ 4019 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 4020 init_ia32_climbframe_attributes(res, count); 4021 4022 info = be_get_info(res); 4023 (void) info; /* avoid potential warning */ 4024 info->out_infos[0].req = &ia32_requirements_gp_in_r3; 4025 4026 4027 /* optimize node */ 4028 res = optimize_node(res); 4029 irn_verify_irg(res, irg); 4030 4031 return res; 4032} 4033 4034/** 4035 * construct ffreep node 4036 */ 4037ir_node *new_bd_ia32_ffreep(dbg_info *dbgi, ir_node *block) 4038{ 4039 ir_graph *irg = get_irn_irg(block); 4040 ir_op *op = op_ia32_ffreep; 4041 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 4042 ir_node *res; 4043 backend_info_t *info; 4044 int arity = 0; 4045 ir_node **in = NULL; 4046 int n_res = 1; 4047 ir_mode *mode = mode_ANY; 4048 static const arch_register_req_t **in_reqs = NULL; 4049 4050 /* create node */ 4051 assert(op != NULL); 4052 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 4053 4054 /* init node attributes */ 4055 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 4056 init_ia32_x87_attributes(res); 4057 4058 info = be_get_info(res); 4059 (void) info; /* avoid potential warning */ 4060 info->out_infos[0].req = &ia32_requirements__none; 4061 4062 4063 /* optimize node */ 4064 res = optimize_node(res); 4065 irn_verify_irg(res, irg); 4066 4067 return res; 4068} 4069 4070/** 4071 * construct SubMem node 4072 */ 4073ir_node *new_bd_ia32_SubMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *subtrahend) 4074{ 4075 ir_graph *irg = get_irn_irg(block); 4076 ir_op *op = op_ia32_SubMem; 4077 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 4078 ir_node *res; 4079 backend_info_t *info; 4080 int arity = 4; 4081 ir_node *in[4]; 4082 int n_res = 1; 4083 ir_mode *mode = mode_M; 4084 static const arch_register_req_t *in_reqs[] = 4085 { 4086 & ia32_requirements_gp_gp, 4087 & ia32_requirements_gp_gp, 4088 & ia32_requirements__none, 4089 & ia32_requirements_gp_gp, 4090 }; 4091 4092 /* construct in array */ 4093 in[0] = base; 4094 in[1] = index; 4095 in[2] = mem; 4096 in[3] = subtrahend; 4097 4098 /* flags */ 4099 irn_flags_ |= arch_irn_flags_rematerializable; 4100 4101 /* create node */ 4102 assert(op != NULL); 4103 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 4104 4105 /* init node attributes */ 4106 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 4107 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 4108 4109 info = be_get_info(res); 4110 (void) info; /* avoid potential warning */ 4111 info->out_infos[0].req = &ia32_requirements__none; 4112 4113 4114 /* optimize node */ 4115 res = optimize_node(res); 4116 irn_verify_irg(res, irg); 4117 4118 return res; 4119} 4120 4121/** 4122 * construct AddMem node 4123 */ 4124ir_node *new_bd_ia32_AddMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val) 4125{ 4126 ir_graph *irg = get_irn_irg(block); 4127 ir_op *op = op_ia32_AddMem; 4128 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 4129 ir_node *res; 4130 backend_info_t *info; 4131 int arity = 4; 4132 ir_node *in[4]; 4133 int n_res = 1; 4134 ir_mode *mode = mode_M; 4135 static const arch_register_req_t *in_reqs[] = 4136 { 4137 & ia32_requirements_gp_gp, 4138 & ia32_requirements_gp_gp, 4139 & ia32_requirements__none, 4140 & ia32_requirements_gp_gp, 4141 }; 4142 4143 /* construct in array */ 4144 in[0] = base; 4145 in[1] = index; 4146 in[2] = mem; 4147 in[3] = val; 4148 4149 /* flags */ 4150 irn_flags_ |= arch_irn_flags_rematerializable; 4151 4152 /* create node */ 4153 assert(op != NULL); 4154 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 4155 4156 /* init node attributes */ 4157 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 4158 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 4159 4160 info = be_get_info(res); 4161 (void) info; /* avoid potential warning */ 4162 info->out_infos[0].req = &ia32_requirements__none; 4163 4164 4165 /* optimize node */ 4166 res = optimize_node(res); 4167 irn_verify_irg(res, irg); 4168 4169 return res; 4170} 4171 4172/** 4173 * construct ShlMem node 4174 */ 4175ir_node *new_bd_ia32_ShlMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count) 4176{ 4177 ir_graph *irg = get_irn_irg(block); 4178 ir_op *op = op_ia32_ShlMem; 4179 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 4180 ir_node *res; 4181 backend_info_t *info; 4182 int arity = 4; 4183 ir_node *in[4]; 4184 int n_res = 1; 4185 ir_mode *mode = mode_M; 4186 static const arch_register_req_t *in_reqs[] = 4187 { 4188 & ia32_requirements_gp_gp, 4189 & ia32_requirements_gp_gp, 4190 & ia32_requirements__none, 4191 & ia32_requirements_gp_ecx, 4192 }; 4193 4194 /* construct in array */ 4195 in[0] = base; 4196 in[1] = index; 4197 in[2] = mem; 4198 in[3] = count; 4199 4200 /* flags */ 4201 irn_flags_ |= arch_irn_flags_rematerializable; 4202 4203 /* create node */ 4204 assert(op != NULL); 4205 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 4206 4207 /* init node attributes */ 4208 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 4209 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 4210 4211 info = be_get_info(res); 4212 (void) info; /* avoid potential warning */ 4213 info->out_infos[0].req = &ia32_requirements__none; 4214 4215 4216 /* optimize node */ 4217 res = optimize_node(res); 4218 irn_verify_irg(res, irg); 4219 4220 return res; 4221} 4222 4223/** 4224 * construct fdiv node 4225 */ 4226ir_node *new_bd_ia32_fdiv(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *dividend, ir_node *divisor, ir_node *fpcw) 4227{ 4228 ir_graph *irg = get_irn_irg(block); 4229 ir_op *op = op_ia32_fdiv; 4230 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 4231 ir_node *res; 4232 backend_info_t *info; 4233 int arity = 6; 4234 ir_node *in[6]; 4235 int n_res = 3; 4236 ir_mode *mode = mode_T; 4237 static const arch_register_req_t *in_reqs[] = 4238 { 4239 & ia32_requirements_gp_gp, 4240 & ia32_requirements_gp_gp, 4241 & ia32_requirements__none, 4242 & ia32_requirements_fp_fp, 4243 & ia32_requirements_fp_fp, 4244 & ia32_requirements_fp_cw_fpcw, 4245 }; 4246 4247 /* construct in array */ 4248 in[0] = base; 4249 in[1] = index; 4250 in[2] = mem; 4251 in[3] = dividend; 4252 in[4] = divisor; 4253 in[5] = fpcw; 4254 4255 /* create node */ 4256 assert(op != NULL); 4257 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 4258 4259 /* init node attributes */ 4260 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 4261 init_ia32_x87_attributes(res); 4262 set_ia32_am_support(res, ia32_am_binary); 4263 info = be_get_info(res); 4264 (void) info; /* avoid potential warning */ 4265 info->out_infos[0].req = &ia32_requirements_fp_fp; 4266 info->out_infos[1].req = &ia32_requirements__none; 4267 info->out_infos[2].req = &ia32_requirements__none; 4268 4269 4270 /* optimize node */ 4271 res = optimize_node(res); 4272 irn_verify_irg(res, irg); 4273 4274 return res; 4275} 4276 4277/** 4278 * construct Outport node 4279 */ 4280ir_node *new_bd_ia32_Outport(dbg_info *dbgi, ir_node *block, ir_node *port, ir_node *value, ir_node *mem) 4281{ 4282 ir_graph *irg = get_irn_irg(block); 4283 ir_op *op = op_ia32_Outport; 4284 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 4285 ir_node *res; 4286 backend_info_t *info; 4287 int arity = 3; 4288 ir_node *in[3]; 4289 int n_res = 1; 4290 ir_mode *mode = mode_M; 4291 static const arch_register_req_t *in_reqs[] = 4292 { 4293 & ia32_requirements_gp_edx, 4294 & ia32_requirements_gp_eax, 4295 & ia32_requirements__none, 4296 }; 4297 4298 /* construct in array */ 4299 in[0] = port; 4300 in[1] = value; 4301 in[2] = mem; 4302 4303 /* flags */ 4304 irn_flags_ |= arch_irn_flags_rematerializable; 4305 4306 /* create node */ 4307 assert(op != NULL); 4308 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 4309 4310 /* init node attributes */ 4311 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 4312 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 4313 4314 info = be_get_info(res); 4315 (void) info; /* avoid potential warning */ 4316 info->out_infos[0].req = &ia32_requirements__none; 4317 4318 4319 /* optimize node */ 4320 res = optimize_node(res); 4321 irn_verify_irg(res, irg); 4322 4323 return res; 4324} 4325 4326/** 4327 * construct xMin node 4328 */ 4329ir_node *new_bd_ia32_xMin(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right) 4330{ 4331 ir_graph *irg = get_irn_irg(block); 4332 ir_op *op = op_ia32_xMin; 4333 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 4334 ir_node *res; 4335 backend_info_t *info; 4336 int arity = 5; 4337 ir_node *in[5]; 4338 int n_res = 3; 4339 ir_mode *mode = mode_D; 4340 static const arch_register_req_t *in_reqs[] = 4341 { 4342 & ia32_requirements_gp_gp, 4343 & ia32_requirements_gp_gp, 4344 & ia32_requirements__none, 4345 & ia32_requirements_xmm_xmm, 4346 & ia32_requirements_xmm_xmm, 4347 }; 4348 4349 /* construct in array */ 4350 in[0] = base; 4351 in[1] = index; 4352 in[2] = mem; 4353 in[3] = left; 4354 in[4] = right; 4355 4356 /* flags */ 4357 irn_flags_ |= arch_irn_flags_rematerializable; 4358 4359 /* create node */ 4360 assert(op != NULL); 4361 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 4362 4363 /* init node attributes */ 4364 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 4365 set_ia32_am_support(res, ia32_am_binary); 4366 info = be_get_info(res); 4367 (void) info; /* avoid potential warning */ 4368 info->out_infos[0].req = &ia32_requirements_xmm_in_r4_in_r5; 4369 info->out_infos[1].req = &ia32_requirements_flags_flags; 4370 info->out_infos[2].req = &ia32_requirements__none; 4371 4372 4373 /* optimize node */ 4374 res = optimize_node(res); 4375 irn_verify_irg(res, irg); 4376 4377 return res; 4378} 4379 4380/** 4381 * construct fist node 4382 */ 4383ir_node *new_bd_ia32_fist(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_node *fpcw) 4384{ 4385 ir_graph *irg = get_irn_irg(block); 4386 ir_op *op = op_ia32_fist; 4387 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 4388 ir_node *res; 4389 backend_info_t *info; 4390 int arity = 5; 4391 ir_node *in[5]; 4392 int n_res = 4; 4393 ir_mode *mode = mode_T; 4394 static const arch_register_req_t *in_reqs[] = 4395 { 4396 & ia32_requirements_gp_gp, 4397 & ia32_requirements_gp_gp, 4398 & ia32_requirements__none, 4399 & ia32_requirements_fp_fp, 4400 & ia32_requirements_fp_cw_fpcw, 4401 }; 4402 4403 /* construct in array */ 4404 in[0] = base; 4405 in[1] = index; 4406 in[2] = mem; 4407 in[3] = val; 4408 in[4] = fpcw; 4409 4410 /* create node */ 4411 assert(op != NULL); 4412 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 4413 4414 /* init node attributes */ 4415 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 4416 init_ia32_x87_attributes(res); 4417 4418 info = be_get_info(res); 4419 (void) info; /* avoid potential warning */ 4420 info->out_infos[0].req = &ia32_requirements__none; 4421 info->out_infos[1].req = &ia32_requirements__none; 4422 info->out_infos[2].req = &ia32_requirements__none; 4423 info->out_infos[3].req = &ia32_requirements__none; 4424 4425 4426 /* optimize node */ 4427 res = optimize_node(res); 4428 irn_verify_irg(res, irg); 4429 4430 return res; 4431} 4432 4433/** 4434 * construct xXor node 4435 */ 4436ir_node *new_bd_ia32_xXor(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right) 4437{ 4438 ir_graph *irg = get_irn_irg(block); 4439 ir_op *op = op_ia32_xXor; 4440 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 4441 ir_node *res; 4442 backend_info_t *info; 4443 int arity = 5; 4444 ir_node *in[5]; 4445 int n_res = 3; 4446 ir_mode *mode = mode_D; 4447 static const arch_register_req_t *in_reqs[] = 4448 { 4449 & ia32_requirements_gp_gp, 4450 & ia32_requirements_gp_gp, 4451 & ia32_requirements__none, 4452 & ia32_requirements_xmm_xmm, 4453 & ia32_requirements_xmm_xmm, 4454 }; 4455 4456 /* construct in array */ 4457 in[0] = base; 4458 in[1] = index; 4459 in[2] = mem; 4460 in[3] = left; 4461 in[4] = right; 4462 4463 /* flags */ 4464 irn_flags_ |= arch_irn_flags_rematerializable; 4465 4466 /* create node */ 4467 assert(op != NULL); 4468 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 4469 4470 /* init node attributes */ 4471 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 4472 set_ia32_am_support(res, ia32_am_binary); 4473 info = be_get_info(res); 4474 (void) info; /* avoid potential warning */ 4475 info->out_infos[0].req = &ia32_requirements_xmm_in_r4_in_r5; 4476 info->out_infos[1].req = &ia32_requirements_flags_flags; 4477 info->out_infos[2].req = &ia32_requirements__none; 4478 4479 4480 /* optimize node */ 4481 res = optimize_node(res); 4482 irn_verify_irg(res, irg); 4483 4484 return res; 4485} 4486 4487/** 4488 * construct IJmp node 4489 */ 4490ir_node *new_bd_ia32_IJmp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *target) 4491{ 4492 ir_graph *irg = get_irn_irg(block); 4493 ir_op *op = op_ia32_IJmp; 4494 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 4495 ir_node *res; 4496 backend_info_t *info; 4497 int arity = 4; 4498 ir_node *in[4]; 4499 int n_res = 3; 4500 ir_mode *mode = mode_X; 4501 static const arch_register_req_t *in_reqs[] = 4502 { 4503 & ia32_requirements_gp_gp, 4504 & ia32_requirements_gp_gp, 4505 & ia32_requirements__none, 4506 & ia32_requirements_gp_gp, 4507 }; 4508 4509 /* construct in array */ 4510 in[0] = base; 4511 in[1] = index; 4512 in[2] = mem; 4513 in[3] = target; 4514 4515 /* create node */ 4516 assert(op != NULL); 4517 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 4518 4519 /* init node attributes */ 4520 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 4521 set_ia32_am_support(res, ia32_am_unary); 4522 info = be_get_info(res); 4523 (void) info; /* avoid potential warning */ 4524 info->out_infos[0].req = &ia32_requirements__none; 4525 info->out_infos[1].req = &ia32_requirements_flags_flags; 4526 info->out_infos[2].req = &ia32_requirements__none; 4527 4528 4529 /* optimize node */ 4530 res = optimize_node(res); 4531 irn_verify_irg(res, irg); 4532 4533 return res; 4534} 4535 4536/** 4537 * construct NegMem node 4538 */ 4539ir_node *new_bd_ia32_NegMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem) 4540{ 4541 ir_graph *irg = get_irn_irg(block); 4542 ir_op *op = op_ia32_NegMem; 4543 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 4544 ir_node *res; 4545 backend_info_t *info; 4546 int arity = 3; 4547 ir_node *in[3]; 4548 int n_res = 1; 4549 ir_mode *mode = mode_M; 4550 static const arch_register_req_t *in_reqs[] = 4551 { 4552 & ia32_requirements_gp_gp, 4553 & ia32_requirements_gp_gp, 4554 & ia32_requirements__none, 4555 }; 4556 4557 /* construct in array */ 4558 in[0] = base; 4559 in[1] = index; 4560 in[2] = mem; 4561 4562 /* flags */ 4563 irn_flags_ |= arch_irn_flags_rematerializable; 4564 4565 /* create node */ 4566 assert(op != NULL); 4567 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 4568 4569 /* init node attributes */ 4570 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 4571 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 4572 4573 info = be_get_info(res); 4574 (void) info; /* avoid potential warning */ 4575 info->out_infos[0].req = &ia32_requirements__none; 4576 4577 4578 /* optimize node */ 4579 res = optimize_node(res); 4580 irn_verify_irg(res, irg); 4581 4582 return res; 4583} 4584 4585/** 4586 * construct CMovcc node 4587 */ 4588ir_node *new_bd_ia32_CMovcc(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val_false, ir_node *val_true, ir_node *eflags, ia32_condition_code_t condition_code) 4589{ 4590 ir_graph *irg = get_irn_irg(block); 4591 ir_op *op = op_ia32_CMovcc; 4592 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 4593 ir_node *res; 4594 backend_info_t *info; 4595 int arity = 6; 4596 ir_node *in[6]; 4597 int n_res = 3; 4598 ir_mode *mode = mode_Iu; 4599 static const arch_register_req_t *in_reqs[] = 4600 { 4601 & ia32_requirements_gp_gp, 4602 & ia32_requirements_gp_gp, 4603 & ia32_requirements__none, 4604 & ia32_requirements_gp_gp, 4605 & ia32_requirements_gp_gp, 4606 & ia32_requirements_flags_eflags, 4607 }; 4608 4609 /* construct in array */ 4610 in[0] = base; 4611 in[1] = index; 4612 in[2] = mem; 4613 in[3] = val_false; 4614 in[4] = val_true; 4615 in[5] = eflags; 4616 4617 /* create node */ 4618 assert(op != NULL); 4619 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 4620 4621 /* init node attributes */ 4622 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 4623 init_ia32_condcode_attributes(res, condition_code); 4624 set_ia32_am_support(res, ia32_am_binary); 4625 info = be_get_info(res); 4626 (void) info; /* avoid potential warning */ 4627 info->out_infos[0].req = &ia32_requirements_gp_in_r4_in_r5; 4628 info->out_infos[1].req = &ia32_requirements_flags_flags; 4629 info->out_infos[2].req = &ia32_requirements__none; 4630 4631 4632 /* optimize node */ 4633 res = optimize_node(res); 4634 irn_verify_irg(res, irg); 4635 4636 return res; 4637} 4638 4639/** 4640 * construct Mul node 4641 */ 4642ir_node *new_bd_ia32_Mul(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right) 4643{ 4644 ir_graph *irg = get_irn_irg(block); 4645 ir_op *op = op_ia32_Mul; 4646 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 4647 ir_node *res; 4648 backend_info_t *info; 4649 int arity = 5; 4650 ir_node *in[5]; 4651 int n_res = 4; 4652 ir_mode *mode = mode_T; 4653 static const arch_register_req_t *in_reqs[] = 4654 { 4655 & ia32_requirements_gp_gp, 4656 & ia32_requirements_gp_gp, 4657 & ia32_requirements__none, 4658 & ia32_requirements_gp_eax, 4659 & ia32_requirements_gp_gp, 4660 }; 4661 4662 /* construct in array */ 4663 in[0] = base; 4664 in[1] = index; 4665 in[2] = mem; 4666 in[3] = left; 4667 in[4] = right; 4668 4669 /* create node */ 4670 assert(op != NULL); 4671 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 4672 4673 /* init node attributes */ 4674 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 4675 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 4676 set_ia32_am_support(res, ia32_am_binary); 4677 info = be_get_info(res); 4678 (void) info; /* avoid potential warning */ 4679 info->out_infos[0].req = &ia32_requirements_gp_eax; 4680 info->out_infos[1].req = &ia32_requirements_flags_flags; 4681 info->out_infos[2].req = &ia32_requirements__none; 4682 info->out_infos[3].req = &ia32_requirements_gp_edx; 4683 4684 4685 /* optimize node */ 4686 res = optimize_node(res); 4687 irn_verify_irg(res, irg); 4688 4689 return res; 4690} 4691 4692/** 4693 * construct Sahf node 4694 */ 4695ir_node *new_bd_ia32_Sahf(dbg_info *dbgi, ir_node *block, ir_node *val) 4696{ 4697 ir_graph *irg = get_irn_irg(block); 4698 ir_op *op = op_ia32_Sahf; 4699 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 4700 ir_node *res; 4701 backend_info_t *info; 4702 int arity = 1; 4703 ir_node *in[1]; 4704 int n_res = 1; 4705 ir_mode *mode = mode_Iu; 4706 static const arch_register_req_t *in_reqs[] = 4707 { 4708 & ia32_requirements_gp_eax, 4709 }; 4710 4711 /* construct in array */ 4712 in[0] = val; 4713 4714 /* flags */ 4715 irn_flags_ |= arch_irn_flags_rematerializable; 4716 4717 /* create node */ 4718 assert(op != NULL); 4719 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 4720 4721 /* init node attributes */ 4722 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 4723 4724 info = be_get_info(res); 4725 (void) info; /* avoid potential warning */ 4726 info->out_infos[0].req = &ia32_requirements_flags_eflags; 4727 4728 4729 /* optimize node */ 4730 res = optimize_node(res); 4731 irn_verify_irg(res, irg); 4732 4733 return res; 4734} 4735 4736/** 4737 * construct SubMem8Bit node 4738 */ 4739ir_node *new_bd_ia32_SubMem8Bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *subtrahend) 4740{ 4741 ir_graph *irg = get_irn_irg(block); 4742 ir_op *op = op_ia32_SubMem8Bit; 4743 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 4744 ir_node *res; 4745 backend_info_t *info; 4746 int arity = 4; 4747 ir_node *in[4]; 4748 int n_res = 1; 4749 ir_mode *mode = mode_M; 4750 static const arch_register_req_t *in_reqs[] = 4751 { 4752 & ia32_requirements_gp_gp, 4753 & ia32_requirements_gp_gp, 4754 & ia32_requirements__none, 4755 & ia32_requirements_gp_eax_ebx_ecx_edx, 4756 }; 4757 4758 /* construct in array */ 4759 in[0] = base; 4760 in[1] = index; 4761 in[2] = mem; 4762 in[3] = subtrahend; 4763 4764 /* flags */ 4765 irn_flags_ |= arch_irn_flags_rematerializable; 4766 4767 /* create node */ 4768 assert(op != NULL); 4769 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 4770 4771 /* init node attributes */ 4772 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 4773 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 4774 4775 info = be_get_info(res); 4776 (void) info; /* avoid potential warning */ 4777 info->out_infos[0].req = &ia32_requirements__none; 4778 4779 4780 /* optimize node */ 4781 res = optimize_node(res); 4782 irn_verify_irg(res, irg); 4783 4784 return res; 4785} 4786 4787/** 4788 * construct AddMem8Bit node 4789 */ 4790ir_node *new_bd_ia32_AddMem8Bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val) 4791{ 4792 ir_graph *irg = get_irn_irg(block); 4793 ir_op *op = op_ia32_AddMem8Bit; 4794 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 4795 ir_node *res; 4796 backend_info_t *info; 4797 int arity = 4; 4798 ir_node *in[4]; 4799 int n_res = 1; 4800 ir_mode *mode = mode_M; 4801 static const arch_register_req_t *in_reqs[] = 4802 { 4803 & ia32_requirements_gp_gp, 4804 & ia32_requirements_gp_gp, 4805 & ia32_requirements__none, 4806 & ia32_requirements_gp_eax_ebx_ecx_edx, 4807 }; 4808 4809 /* construct in array */ 4810 in[0] = base; 4811 in[1] = index; 4812 in[2] = mem; 4813 in[3] = val; 4814 4815 /* flags */ 4816 irn_flags_ |= arch_irn_flags_rematerializable; 4817 4818 /* create node */ 4819 assert(op != NULL); 4820 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 4821 4822 /* init node attributes */ 4823 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 4824 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 4825 4826 info = be_get_info(res); 4827 (void) info; /* avoid potential warning */ 4828 info->out_infos[0].req = &ia32_requirements__none; 4829 4830 4831 /* optimize node */ 4832 res = optimize_node(res); 4833 irn_verify_irg(res, irg); 4834 4835 return res; 4836} 4837 4838/** 4839 * construct fst node 4840 */ 4841ir_node *new_bd_ia32_fst(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_mode *store_mode) 4842{ 4843 ir_graph *irg = get_irn_irg(block); 4844 ir_op *op = op_ia32_fst; 4845 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 4846 ir_node *res; 4847 backend_info_t *info; 4848 int arity = 4; 4849 ir_node *in[4]; 4850 int n_res = 3; 4851 ir_mode *mode = mode_T; 4852 static const arch_register_req_t *in_reqs[] = 4853 { 4854 & ia32_requirements_gp_gp, 4855 & ia32_requirements_gp_gp, 4856 & ia32_requirements__none, 4857 & ia32_requirements_fp_fp, 4858 }; 4859 ia32_x87_attr_t *attr; 4860 4861 /* construct in array */ 4862 in[0] = base; 4863 in[1] = index; 4864 in[2] = mem; 4865 in[3] = val; 4866 4867 /* flags */ 4868 irn_flags_ |= arch_irn_flags_rematerializable; 4869 4870 /* create node */ 4871 assert(op != NULL); 4872 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 4873 4874 /* init node attributes */ 4875 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 4876 init_ia32_x87_attributes(res); 4877 4878 info = be_get_info(res); 4879 (void) info; /* avoid potential warning */ 4880 info->out_infos[0].req = &ia32_requirements__none; 4881 info->out_infos[1].req = &ia32_requirements__none; 4882 info->out_infos[2].req = &ia32_requirements__none; 4883 4884 4885 attr = (ia32_x87_attr_t*)get_irn_generic_attr(res); 4886 (void) attr; /* avoid potential warning */ 4887 attr->attr.ls_mode = store_mode; 4888 /* optimize node */ 4889 res = optimize_node(res); 4890 irn_verify_irg(res, irg); 4891 4892 return res; 4893} 4894 4895/** 4896 * construct FucomppFnstsw node 4897 */ 4898ir_node *new_bd_ia32_FucomppFnstsw(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, bool ins_permuted) 4899{ 4900 ir_graph *irg = get_irn_irg(block); 4901 ir_op *op = op_ia32_FucomppFnstsw; 4902 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 4903 ir_node *res; 4904 backend_info_t *info; 4905 int arity = 2; 4906 ir_node *in[2]; 4907 int n_res = 1; 4908 ir_mode *mode = mode_Iu; 4909 static const arch_register_req_t *in_reqs[] = 4910 { 4911 & ia32_requirements_fp_fp, 4912 & ia32_requirements_fp_fp, 4913 }; 4914 ia32_x87_attr_t *attr; 4915 4916 /* construct in array */ 4917 in[0] = left; 4918 in[1] = right; 4919 4920 /* create node */ 4921 assert(op != NULL); 4922 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 4923 4924 /* init node attributes */ 4925 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 4926 init_ia32_x87_attributes(res); 4927 4928 info = be_get_info(res); 4929 (void) info; /* avoid potential warning */ 4930 info->out_infos[0].req = &ia32_requirements_gp_eax; 4931 4932 4933 attr = (ia32_x87_attr_t*)get_irn_generic_attr(res); 4934 (void) attr; /* avoid potential warning */ 4935 attr->attr.data.ins_permuted = ins_permuted; 4936 /* optimize node */ 4937 res = optimize_node(res); 4938 irn_verify_irg(res, irg); 4939 4940 return res; 4941} 4942 4943/** 4944 * construct RorMem node 4945 */ 4946ir_node *new_bd_ia32_RorMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count) 4947{ 4948 ir_graph *irg = get_irn_irg(block); 4949 ir_op *op = op_ia32_RorMem; 4950 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 4951 ir_node *res; 4952 backend_info_t *info; 4953 int arity = 4; 4954 ir_node *in[4]; 4955 int n_res = 1; 4956 ir_mode *mode = mode_M; 4957 static const arch_register_req_t *in_reqs[] = 4958 { 4959 & ia32_requirements_gp_gp, 4960 & ia32_requirements_gp_gp, 4961 & ia32_requirements__none, 4962 & ia32_requirements_gp_ecx, 4963 }; 4964 4965 /* construct in array */ 4966 in[0] = base; 4967 in[1] = index; 4968 in[2] = mem; 4969 in[3] = count; 4970 4971 /* flags */ 4972 irn_flags_ |= arch_irn_flags_rematerializable; 4973 4974 /* create node */ 4975 assert(op != NULL); 4976 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 4977 4978 /* init node attributes */ 4979 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 4980 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 4981 4982 info = be_get_info(res); 4983 (void) info; /* avoid potential warning */ 4984 info->out_infos[0].req = &ia32_requirements__none; 4985 4986 4987 /* optimize node */ 4988 res = optimize_node(res); 4989 irn_verify_irg(res, irg); 4990 4991 return res; 4992} 4993 4994/** 4995 * construct fpush node 4996 */ 4997ir_node *new_bd_ia32_fpush(dbg_info *dbgi, ir_node *block) 4998{ 4999 ir_graph *irg = get_irn_irg(block); 5000 ir_op *op = op_ia32_fpush; 5001 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 5002 ir_node *res; 5003 backend_info_t *info; 5004 int arity = 0; 5005 ir_node **in = NULL; 5006 int n_res = 1; 5007 ir_mode *mode = mode_ANY; 5008 static const arch_register_req_t **in_reqs = NULL; 5009 5010 /* create node */ 5011 assert(op != NULL); 5012 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 5013 5014 /* init node attributes */ 5015 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 5016 init_ia32_x87_attributes(res); 5017 5018 info = be_get_info(res); 5019 (void) info; /* avoid potential warning */ 5020 info->out_infos[0].req = &ia32_requirements__none; 5021 5022 5023 /* optimize node */ 5024 res = optimize_node(res); 5025 irn_verify_irg(res, irg); 5026 5027 return res; 5028} 5029 5030/** 5031 * construct fild node 5032 */ 5033ir_node *new_bd_ia32_fild(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem) 5034{ 5035 ir_graph *irg = get_irn_irg(block); 5036 ir_op *op = op_ia32_fild; 5037 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 5038 ir_node *res; 5039 backend_info_t *info; 5040 int arity = 3; 5041 ir_node *in[3]; 5042 int n_res = 3; 5043 ir_mode *mode = mode_T; 5044 static const arch_register_req_t *in_reqs[] = 5045 { 5046 & ia32_requirements_gp_gp, 5047 & ia32_requirements_gp_gp, 5048 & ia32_requirements__none, 5049 }; 5050 5051 /* construct in array */ 5052 in[0] = base; 5053 in[1] = index; 5054 in[2] = mem; 5055 5056 /* create node */ 5057 assert(op != NULL); 5058 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 5059 5060 /* init node attributes */ 5061 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 5062 init_ia32_x87_attributes(res); 5063 5064 info = be_get_info(res); 5065 (void) info; /* avoid potential warning */ 5066 info->out_infos[0].req = &ia32_requirements_fp_fp; 5067 info->out_infos[1].req = &ia32_requirements__none; 5068 info->out_infos[2].req = &ia32_requirements__none; 5069 5070 5071 /* optimize node */ 5072 res = optimize_node(res); 5073 irn_verify_irg(res, irg); 5074 5075 return res; 5076} 5077 5078/** 5079 * construct xOr node 5080 */ 5081ir_node *new_bd_ia32_xOr(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right) 5082{ 5083 ir_graph *irg = get_irn_irg(block); 5084 ir_op *op = op_ia32_xOr; 5085 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 5086 ir_node *res; 5087 backend_info_t *info; 5088 int arity = 5; 5089 ir_node *in[5]; 5090 int n_res = 3; 5091 ir_mode *mode = mode_D; 5092 static const arch_register_req_t *in_reqs[] = 5093 { 5094 & ia32_requirements_gp_gp, 5095 & ia32_requirements_gp_gp, 5096 & ia32_requirements__none, 5097 & ia32_requirements_xmm_xmm, 5098 & ia32_requirements_xmm_xmm, 5099 }; 5100 5101 /* construct in array */ 5102 in[0] = base; 5103 in[1] = index; 5104 in[2] = mem; 5105 in[3] = left; 5106 in[4] = right; 5107 5108 /* flags */ 5109 irn_flags_ |= arch_irn_flags_rematerializable; 5110 5111 /* create node */ 5112 assert(op != NULL); 5113 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 5114 5115 /* init node attributes */ 5116 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 5117 set_ia32_am_support(res, ia32_am_binary); 5118 info = be_get_info(res); 5119 (void) info; /* avoid potential warning */ 5120 info->out_infos[0].req = &ia32_requirements_xmm_in_r4_in_r5; 5121 info->out_infos[1].req = &ia32_requirements_flags_flags; 5122 info->out_infos[2].req = &ia32_requirements__none; 5123 5124 5125 /* optimize node */ 5126 res = optimize_node(res); 5127 irn_verify_irg(res, irg); 5128 5129 return res; 5130} 5131 5132/** 5133 * construct Conv_I2I8Bit node 5134 */ 5135ir_node *new_bd_ia32_Conv_I2I8Bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_mode *smaller_mode) 5136{ 5137 ir_graph *irg = get_irn_irg(block); 5138 ir_op *op = op_ia32_Conv_I2I8Bit; 5139 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 5140 ir_node *res; 5141 backend_info_t *info; 5142 int arity = 4; 5143 ir_node *in[4]; 5144 int n_res = 5; 5145 ir_mode *mode = mode_Iu; 5146 static const arch_register_req_t *in_reqs[] = 5147 { 5148 & ia32_requirements_gp_gp, 5149 & ia32_requirements_gp_gp, 5150 & ia32_requirements__none, 5151 & ia32_requirements_gp_eax_ebx_ecx_edx, 5152 }; 5153 ia32_attr_t *attr; 5154 5155 /* construct in array */ 5156 in[0] = base; 5157 in[1] = index; 5158 in[2] = mem; 5159 in[3] = val; 5160 5161 /* create node */ 5162 assert(op != NULL); 5163 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 5164 5165 /* init node attributes */ 5166 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 5167 set_ia32_am_support(res, ia32_am_unary); 5168 info = be_get_info(res); 5169 (void) info; /* avoid potential warning */ 5170 info->out_infos[0].req = &ia32_requirements_gp_gp; 5171 info->out_infos[1].req = &ia32_requirements__none; 5172 info->out_infos[2].req = &ia32_requirements__none; 5173 info->out_infos[3].req = &ia32_requirements__none; 5174 info->out_infos[4].req = &ia32_requirements__none; 5175 5176 5177 attr = (ia32_attr_t*)get_irn_generic_attr(res); 5178 (void) attr; /* avoid potential warning */ 5179 attr->ls_mode = smaller_mode; 5180 /* optimize node */ 5181 res = optimize_node(res); 5182 irn_verify_irg(res, irg); 5183 5184 return res; 5185} 5186 5187/** 5188 * construct Store node 5189 */ 5190ir_node *new_bd_ia32_Store(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val) 5191{ 5192 ir_graph *irg = get_irn_irg(block); 5193 ir_op *op = op_ia32_Store; 5194 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 5195 ir_node *res; 5196 backend_info_t *info; 5197 int arity = 4; 5198 ir_node *in[4]; 5199 int n_res = 3; 5200 ir_mode *mode = mode_T; 5201 static const arch_register_req_t *in_reqs[] = 5202 { 5203 & ia32_requirements_gp_gp, 5204 & ia32_requirements_gp_gp, 5205 & ia32_requirements__none, 5206 & ia32_requirements_gp_gp, 5207 }; 5208 5209 /* construct in array */ 5210 in[0] = base; 5211 in[1] = index; 5212 in[2] = mem; 5213 in[3] = val; 5214 5215 /* create node */ 5216 assert(op != NULL); 5217 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 5218 5219 /* init node attributes */ 5220 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 5221 5222 info = be_get_info(res); 5223 (void) info; /* avoid potential warning */ 5224 info->out_infos[0].req = &ia32_requirements__none; 5225 info->out_infos[1].req = &ia32_requirements__none; 5226 info->out_infos[2].req = &ia32_requirements__none; 5227 5228 5229 /* optimize node */ 5230 res = optimize_node(res); 5231 irn_verify_irg(res, irg); 5232 5233 return res; 5234} 5235 5236/** 5237 * construct fldln2 node 5238 */ 5239ir_node *new_bd_ia32_fldln2(dbg_info *dbgi, ir_node *block) 5240{ 5241 ir_graph *irg = get_irn_irg(block); 5242 ir_op *op = op_ia32_fldln2; 5243 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 5244 ir_node *res; 5245 backend_info_t *info; 5246 int arity = 0; 5247 ir_node **in = NULL; 5248 int n_res = 1; 5249 ir_mode *mode = ia32_mode_E; 5250 static const arch_register_req_t **in_reqs = NULL; 5251 5252 /* flags */ 5253 irn_flags_ |= arch_irn_flags_rematerializable; 5254 5255 /* create node */ 5256 assert(op != NULL); 5257 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 5258 5259 /* init node attributes */ 5260 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 5261 init_ia32_x87_attributes(res); 5262 5263 info = be_get_info(res); 5264 (void) info; /* avoid potential warning */ 5265 info->out_infos[0].req = &ia32_requirements_fp_fp; 5266 5267 5268 /* optimize node */ 5269 res = optimize_node(res); 5270 irn_verify_irg(res, irg); 5271 5272 return res; 5273} 5274 5275/** 5276 * construct SwitchJmp node 5277 */ 5278ir_node *new_bd_ia32_SwitchJmp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, int n_res, const ir_switch_table *switch_table) 5279{ 5280 ir_graph *irg = get_irn_irg(block); 5281 ir_op *op = op_ia32_SwitchJmp; 5282 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 5283 ir_node *res; 5284 backend_info_t *info; 5285 int arity = 2; 5286 ir_node *in[2]; 5287 ir_mode *mode = mode_T; 5288 static const arch_register_req_t *in_reqs[] = 5289 { 5290 & ia32_requirements_gp_gp, 5291 & ia32_requirements_gp_gp, 5292 }; 5293 5294 /* construct in array */ 5295 in[0] = base; 5296 in[1] = index; 5297 5298 /* create node */ 5299 assert(op != NULL); 5300 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 5301 5302 /* init node attributes */ 5303 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 5304 init_ia32_switch_attributes(res, switch_table); 5305 5306 info = be_get_info(res); 5307 (void) info; /* avoid potential warning */ 5308 5309 5310 /* optimize node */ 5311 res = optimize_node(res); 5312 irn_verify_irg(res, irg); 5313 5314 return res; 5315} 5316 5317/** 5318 * construct IMul node 5319 */ 5320ir_node *new_bd_ia32_IMul(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right) 5321{ 5322 ir_graph *irg = get_irn_irg(block); 5323 ir_op *op = op_ia32_IMul; 5324 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 5325 ir_node *res; 5326 backend_info_t *info; 5327 int arity = 5; 5328 ir_node *in[5]; 5329 int n_res = 3; 5330 ir_mode *mode = mode_Iu; 5331 static const arch_register_req_t *in_reqs[] = 5332 { 5333 & ia32_requirements_gp_gp, 5334 & ia32_requirements_gp_gp, 5335 & ia32_requirements__none, 5336 & ia32_requirements_gp_gp, 5337 & ia32_requirements_gp_gp, 5338 }; 5339 5340 /* construct in array */ 5341 in[0] = base; 5342 in[1] = index; 5343 in[2] = mem; 5344 in[3] = left; 5345 in[4] = right; 5346 5347 /* flags */ 5348 irn_flags_ |= arch_irn_flags_rematerializable; 5349 5350 /* create node */ 5351 assert(op != NULL); 5352 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 5353 5354 /* init node attributes */ 5355 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 5356 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 5357 set_ia32_am_support(res, ia32_am_binary); 5358 info = be_get_info(res); 5359 (void) info; /* avoid potential warning */ 5360 info->out_infos[0].req = &ia32_requirements_gp_in_r4_in_r5; 5361 info->out_infos[1].req = &ia32_requirements_flags_flags; 5362 info->out_infos[2].req = &ia32_requirements__none; 5363 5364 5365 /* optimize node */ 5366 res = optimize_node(res); 5367 irn_verify_irg(res, irg); 5368 5369 return res; 5370} 5371 5372/** 5373 * construct Ucomi node 5374 */ 5375ir_node *new_bd_ia32_Ucomi(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, bool ins_permuted) 5376{ 5377 ir_graph *irg = get_irn_irg(block); 5378 ir_op *op = op_ia32_Ucomi; 5379 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 5380 ir_node *res; 5381 backend_info_t *info; 5382 int arity = 5; 5383 ir_node *in[5]; 5384 int n_res = 1; 5385 ir_mode *mode = mode_Iu; 5386 static const arch_register_req_t *in_reqs[] = 5387 { 5388 & ia32_requirements_gp_gp, 5389 & ia32_requirements_gp_gp, 5390 & ia32_requirements__none, 5391 & ia32_requirements_xmm_xmm, 5392 & ia32_requirements_xmm_xmm, 5393 }; 5394 ia32_attr_t *attr; 5395 5396 /* construct in array */ 5397 in[0] = base; 5398 in[1] = index; 5399 in[2] = mem; 5400 in[3] = left; 5401 in[4] = right; 5402 5403 /* flags */ 5404 irn_flags_ |= arch_irn_flags_rematerializable; 5405 5406 /* create node */ 5407 assert(op != NULL); 5408 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 5409 5410 /* init node attributes */ 5411 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 5412 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 5413 set_ia32_am_support(res, ia32_am_binary); 5414 info = be_get_info(res); 5415 (void) info; /* avoid potential warning */ 5416 info->out_infos[0].req = &ia32_requirements_flags_eflags; 5417 5418 5419 attr = (ia32_attr_t*)get_irn_generic_attr(res); 5420 (void) attr; /* avoid potential warning */ 5421 attr->data.ins_permuted = ins_permuted; 5422 /* optimize node */ 5423 res = optimize_node(res); 5424 irn_verify_irg(res, irg); 5425 5426 return res; 5427} 5428 5429/** 5430 * construct fldz node 5431 */ 5432ir_node *new_bd_ia32_fldz(dbg_info *dbgi, ir_node *block) 5433{ 5434 ir_graph *irg = get_irn_irg(block); 5435 ir_op *op = op_ia32_fldz; 5436 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 5437 ir_node *res; 5438 backend_info_t *info; 5439 int arity = 0; 5440 ir_node **in = NULL; 5441 int n_res = 1; 5442 ir_mode *mode = ia32_mode_E; 5443 static const arch_register_req_t **in_reqs = NULL; 5444 5445 /* flags */ 5446 irn_flags_ |= arch_irn_flags_rematerializable; 5447 5448 /* create node */ 5449 assert(op != NULL); 5450 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 5451 5452 /* init node attributes */ 5453 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 5454 init_ia32_x87_attributes(res); 5455 5456 info = be_get_info(res); 5457 (void) info; /* avoid potential warning */ 5458 info->out_infos[0].req = &ia32_requirements_fp_fp; 5459 5460 5461 /* optimize node */ 5462 res = optimize_node(res); 5463 irn_verify_irg(res, irg); 5464 5465 return res; 5466} 5467 5468/** 5469 * construct Store8Bit node 5470 */ 5471ir_node *new_bd_ia32_Store8Bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val) 5472{ 5473 ir_graph *irg = get_irn_irg(block); 5474 ir_op *op = op_ia32_Store8Bit; 5475 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 5476 ir_node *res; 5477 backend_info_t *info; 5478 int arity = 4; 5479 ir_node *in[4]; 5480 int n_res = 3; 5481 ir_mode *mode = mode_T; 5482 static const arch_register_req_t *in_reqs[] = 5483 { 5484 & ia32_requirements_gp_gp, 5485 & ia32_requirements_gp_gp, 5486 & ia32_requirements__none, 5487 & ia32_requirements_gp_eax_ebx_ecx_edx, 5488 }; 5489 5490 /* construct in array */ 5491 in[0] = base; 5492 in[1] = index; 5493 in[2] = mem; 5494 in[3] = val; 5495 5496 /* create node */ 5497 assert(op != NULL); 5498 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 5499 5500 /* init node attributes */ 5501 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 5502 5503 info = be_get_info(res); 5504 (void) info; /* avoid potential warning */ 5505 info->out_infos[0].req = &ia32_requirements__none; 5506 info->out_infos[1].req = &ia32_requirements__none; 5507 info->out_infos[2].req = &ia32_requirements__none; 5508 5509 5510 /* optimize node */ 5511 res = optimize_node(res); 5512 irn_verify_irg(res, irg); 5513 5514 return res; 5515} 5516 5517/** 5518 * construct fpop node 5519 */ 5520ir_node *new_bd_ia32_fpop(dbg_info *dbgi, ir_node *block) 5521{ 5522 ir_graph *irg = get_irn_irg(block); 5523 ir_op *op = op_ia32_fpop; 5524 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 5525 ir_node *res; 5526 backend_info_t *info; 5527 int arity = 0; 5528 ir_node **in = NULL; 5529 int n_res = 1; 5530 ir_mode *mode = mode_ANY; 5531 static const arch_register_req_t **in_reqs = NULL; 5532 5533 /* create node */ 5534 assert(op != NULL); 5535 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 5536 5537 /* init node attributes */ 5538 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 5539 init_ia32_x87_attributes(res); 5540 5541 info = be_get_info(res); 5542 (void) info; /* avoid potential warning */ 5543 info->out_infos[0].req = &ia32_requirements__none; 5544 5545 5546 /* optimize node */ 5547 res = optimize_node(res); 5548 irn_verify_irg(res, irg); 5549 5550 return res; 5551} 5552 5553/** 5554 * construct l_Sub node 5555 */ 5556ir_node *new_bd_ia32_l_Sub(dbg_info *dbgi, ir_node *block, ir_node *minuend, ir_node *subtrahend, ir_mode *mode) 5557{ 5558 ir_graph *irg = get_irn_irg(block); 5559 ir_op *op = op_ia32_l_Sub; 5560 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 5561 ir_node *res; 5562 backend_info_t *info; 5563 int arity = 2; 5564 ir_node *in[2]; 5565 int n_res = 0; 5566 static const arch_register_req_t **in_reqs = NULL; 5567 5568 /* construct in array */ 5569 in[0] = minuend; 5570 in[1] = subtrahend; 5571 5572 /* create node */ 5573 assert(op != NULL); 5574 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 5575 5576 /* init node attributes */ 5577 (void)in;(void)irn_flags_;(void)in_reqs;(void)n_res; 5578 5579 info = be_get_info(res); 5580 (void) info; /* avoid potential warning */ 5581 5582 5583 /* optimize node */ 5584 res = optimize_node(res); 5585 irn_verify_irg(res, irg); 5586 5587 return res; 5588} 5589 5590/** 5591 * construct Sbb node 5592 */ 5593ir_node *new_bd_ia32_Sbb(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *minuend, ir_node *subtrahend, ir_node *eflags) 5594{ 5595 ir_graph *irg = get_irn_irg(block); 5596 ir_op *op = op_ia32_Sbb; 5597 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 5598 ir_node *res; 5599 backend_info_t *info; 5600 int arity = 6; 5601 ir_node *in[6]; 5602 int n_res = 3; 5603 ir_mode *mode = mode_Iu; 5604 static const arch_register_req_t *in_reqs[] = 5605 { 5606 & ia32_requirements_gp_gp, 5607 & ia32_requirements_gp_gp, 5608 & ia32_requirements__none, 5609 & ia32_requirements_gp_gp, 5610 & ia32_requirements_gp_gp, 5611 & ia32_requirements_flags_flags, 5612 }; 5613 5614 /* construct in array */ 5615 in[0] = base; 5616 in[1] = index; 5617 in[2] = mem; 5618 in[3] = minuend; 5619 in[4] = subtrahend; 5620 in[5] = eflags; 5621 5622 /* create node */ 5623 assert(op != NULL); 5624 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 5625 5626 /* init node attributes */ 5627 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 5628 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 5629 set_ia32_am_support(res, ia32_am_binary); 5630 info = be_get_info(res); 5631 (void) info; /* avoid potential warning */ 5632 info->out_infos[0].req = &ia32_requirements_gp_in_r4; 5633 info->out_infos[1].req = &ia32_requirements_flags_flags; 5634 info->out_infos[2].req = &ia32_requirements__none; 5635 5636 5637 /* optimize node */ 5638 res = optimize_node(res); 5639 irn_verify_irg(res, irg); 5640 5641 return res; 5642} 5643 5644/** 5645 * construct FucomFnstsw node 5646 */ 5647ir_node *new_bd_ia32_FucomFnstsw(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, bool ins_permuted) 5648{ 5649 ir_graph *irg = get_irn_irg(block); 5650 ir_op *op = op_ia32_FucomFnstsw; 5651 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 5652 ir_node *res; 5653 backend_info_t *info; 5654 int arity = 2; 5655 ir_node *in[2]; 5656 int n_res = 1; 5657 ir_mode *mode = mode_Iu; 5658 static const arch_register_req_t *in_reqs[] = 5659 { 5660 & ia32_requirements_fp_fp, 5661 & ia32_requirements_fp_fp, 5662 }; 5663 ia32_x87_attr_t *attr; 5664 5665 /* construct in array */ 5666 in[0] = left; 5667 in[1] = right; 5668 5669 /* create node */ 5670 assert(op != NULL); 5671 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 5672 5673 /* init node attributes */ 5674 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 5675 init_ia32_x87_attributes(res); 5676 5677 info = be_get_info(res); 5678 (void) info; /* avoid potential warning */ 5679 info->out_infos[0].req = &ia32_requirements_gp_eax; 5680 5681 5682 attr = (ia32_x87_attr_t*)get_irn_generic_attr(res); 5683 (void) attr; /* avoid potential warning */ 5684 attr->attr.data.ins_permuted = ins_permuted; 5685 /* optimize node */ 5686 res = optimize_node(res); 5687 irn_verify_irg(res, irg); 5688 5689 return res; 5690} 5691 5692/** 5693 * construct xMul node 5694 */ 5695ir_node *new_bd_ia32_xMul(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right) 5696{ 5697 ir_graph *irg = get_irn_irg(block); 5698 ir_op *op = op_ia32_xMul; 5699 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 5700 ir_node *res; 5701 backend_info_t *info; 5702 int arity = 5; 5703 ir_node *in[5]; 5704 int n_res = 3; 5705 ir_mode *mode = mode_D; 5706 static const arch_register_req_t *in_reqs[] = 5707 { 5708 & ia32_requirements_gp_gp, 5709 & ia32_requirements_gp_gp, 5710 & ia32_requirements__none, 5711 & ia32_requirements_xmm_xmm, 5712 & ia32_requirements_xmm_xmm, 5713 }; 5714 5715 /* construct in array */ 5716 in[0] = base; 5717 in[1] = index; 5718 in[2] = mem; 5719 in[3] = left; 5720 in[4] = right; 5721 5722 /* flags */ 5723 irn_flags_ |= arch_irn_flags_rematerializable; 5724 5725 /* create node */ 5726 assert(op != NULL); 5727 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 5728 5729 /* init node attributes */ 5730 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 5731 set_ia32_am_support(res, ia32_am_binary); 5732 info = be_get_info(res); 5733 (void) info; /* avoid potential warning */ 5734 info->out_infos[0].req = &ia32_requirements_xmm_in_r4_in_r5; 5735 info->out_infos[1].req = &ia32_requirements_flags_flags; 5736 info->out_infos[2].req = &ia32_requirements__none; 5737 5738 5739 /* optimize node */ 5740 res = optimize_node(res); 5741 irn_verify_irg(res, irg); 5742 5743 return res; 5744} 5745 5746/** 5747 * construct Push node 5748 */ 5749ir_node *new_bd_ia32_Push(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_node *stack) 5750{ 5751 ir_graph *irg = get_irn_irg(block); 5752 ir_op *op = op_ia32_Push; 5753 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 5754 ir_node *res; 5755 backend_info_t *info; 5756 int arity = 5; 5757 ir_node *in[5]; 5758 int n_res = 2; 5759 ir_mode *mode = mode_T; 5760 static const arch_register_req_t *in_reqs[] = 5761 { 5762 & ia32_requirements_gp_gp, 5763 & ia32_requirements_gp_gp, 5764 & ia32_requirements__none, 5765 & ia32_requirements_gp_gp, 5766 & ia32_requirements_gp_esp, 5767 }; 5768 5769 /* construct in array */ 5770 in[0] = base; 5771 in[1] = index; 5772 in[2] = mem; 5773 in[3] = val; 5774 in[4] = stack; 5775 5776 /* create node */ 5777 assert(op != NULL); 5778 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 5779 5780 /* init node attributes */ 5781 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 5782 set_ia32_am_support(res, ia32_am_unary); 5783 info = be_get_info(res); 5784 (void) info; /* avoid potential warning */ 5785 info->out_infos[0].req = &ia32_requirements_gp_esp_I_S; 5786 info->out_infos[1].req = &ia32_requirements__none; 5787 5788 5789 /* optimize node */ 5790 res = optimize_node(res); 5791 irn_verify_irg(res, irg); 5792 5793 return res; 5794} 5795 5796/** 5797 * construct xPslld node 5798 */ 5799ir_node *new_bd_ia32_xPslld(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_node *op1) 5800{ 5801 ir_graph *irg = get_irn_irg(block); 5802 ir_op *op = op_ia32_xPslld; 5803 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 5804 ir_node *res; 5805 backend_info_t *info; 5806 int arity = 2; 5807 ir_node *in[2]; 5808 int n_res = 1; 5809 ir_mode *mode = mode_D; 5810 static const arch_register_req_t *in_reqs[] = 5811 { 5812 & ia32_requirements_xmm_xmm, 5813 & ia32_requirements_xmm_xmm, 5814 }; 5815 5816 /* construct in array */ 5817 in[0] = op0; 5818 in[1] = op1; 5819 5820 /* flags */ 5821 irn_flags_ |= arch_irn_flags_rematerializable; 5822 5823 /* create node */ 5824 assert(op != NULL); 5825 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 5826 5827 /* init node attributes */ 5828 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 5829 5830 info = be_get_info(res); 5831 (void) info; /* avoid potential warning */ 5832 info->out_infos[0].req = &ia32_requirements_xmm_in_r1_not_in_r2; 5833 5834 5835 /* optimize node */ 5836 res = optimize_node(res); 5837 irn_verify_irg(res, irg); 5838 5839 return res; 5840} 5841 5842/** 5843 * construct Cmp node 5844 */ 5845ir_node *new_bd_ia32_Cmp(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, bool ins_permuted) 5846{ 5847 ir_graph *irg = get_irn_irg(block); 5848 ir_op *op = op_ia32_Cmp; 5849 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 5850 ir_node *res; 5851 backend_info_t *info; 5852 int arity = 5; 5853 ir_node *in[5]; 5854 int n_res = 3; 5855 ir_mode *mode = mode_Iu; 5856 static const arch_register_req_t *in_reqs[] = 5857 { 5858 & ia32_requirements_gp_gp, 5859 & ia32_requirements_gp_gp, 5860 & ia32_requirements__none, 5861 & ia32_requirements_gp_gp, 5862 & ia32_requirements_gp_gp, 5863 }; 5864 ia32_attr_t *attr; 5865 5866 /* construct in array */ 5867 in[0] = base; 5868 in[1] = index; 5869 in[2] = mem; 5870 in[3] = left; 5871 in[4] = right; 5872 5873 /* flags */ 5874 irn_flags_ |= arch_irn_flags_rematerializable; 5875 5876 /* create node */ 5877 assert(op != NULL); 5878 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 5879 5880 /* init node attributes */ 5881 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 5882 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 5883 set_ia32_am_support(res, ia32_am_binary); 5884 info = be_get_info(res); 5885 (void) info; /* avoid potential warning */ 5886 info->out_infos[0].req = &ia32_requirements_flags_flags; 5887 info->out_infos[1].req = &ia32_requirements__none; 5888 info->out_infos[2].req = &ia32_requirements__none; 5889 5890 5891 attr = (ia32_attr_t*)get_irn_generic_attr(res); 5892 (void) attr; /* avoid potential warning */ 5893 attr->data.ins_permuted = ins_permuted; 5894 /* optimize node */ 5895 res = optimize_node(res); 5896 irn_verify_irg(res, irg); 5897 5898 return res; 5899} 5900 5901/** 5902 * construct xSub node 5903 */ 5904ir_node *new_bd_ia32_xSub(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *minuend, ir_node *subtrahend) 5905{ 5906 ir_graph *irg = get_irn_irg(block); 5907 ir_op *op = op_ia32_xSub; 5908 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 5909 ir_node *res; 5910 backend_info_t *info; 5911 int arity = 5; 5912 ir_node *in[5]; 5913 int n_res = 3; 5914 ir_mode *mode = mode_D; 5915 static const arch_register_req_t *in_reqs[] = 5916 { 5917 & ia32_requirements_gp_gp, 5918 & ia32_requirements_gp_gp, 5919 & ia32_requirements__none, 5920 & ia32_requirements_xmm_xmm, 5921 & ia32_requirements_xmm_xmm, 5922 }; 5923 5924 /* construct in array */ 5925 in[0] = base; 5926 in[1] = index; 5927 in[2] = mem; 5928 in[3] = minuend; 5929 in[4] = subtrahend; 5930 5931 /* flags */ 5932 irn_flags_ |= arch_irn_flags_rematerializable; 5933 5934 /* create node */ 5935 assert(op != NULL); 5936 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 5937 5938 /* init node attributes */ 5939 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 5940 set_ia32_am_support(res, ia32_am_binary); 5941 info = be_get_info(res); 5942 (void) info; /* avoid potential warning */ 5943 info->out_infos[0].req = &ia32_requirements_xmm_in_r4; 5944 info->out_infos[1].req = &ia32_requirements_flags_flags; 5945 info->out_infos[2].req = &ia32_requirements__none; 5946 5947 5948 /* optimize node */ 5949 res = optimize_node(res); 5950 irn_verify_irg(res, irg); 5951 5952 return res; 5953} 5954 5955/** 5956 * construct xMovd node 5957 */ 5958ir_node *new_bd_ia32_xMovd(dbg_info *dbgi, ir_node *block, ir_node *op0) 5959{ 5960 ir_graph *irg = get_irn_irg(block); 5961 ir_op *op = op_ia32_xMovd; 5962 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 5963 ir_node *res; 5964 backend_info_t *info; 5965 int arity = 1; 5966 ir_node *in[1]; 5967 int n_res = 1; 5968 ir_mode *mode = mode_D; 5969 static const arch_register_req_t *in_reqs[] = 5970 { 5971 & ia32_requirements_gp_gp, 5972 }; 5973 5974 /* construct in array */ 5975 in[0] = op0; 5976 5977 /* flags */ 5978 irn_flags_ |= arch_irn_flags_rematerializable; 5979 5980 /* create node */ 5981 assert(op != NULL); 5982 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 5983 5984 /* init node attributes */ 5985 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 5986 5987 info = be_get_info(res); 5988 (void) info; /* avoid potential warning */ 5989 info->out_infos[0].req = &ia32_requirements_xmm_xmm; 5990 5991 5992 /* optimize node */ 5993 res = optimize_node(res); 5994 irn_verify_irg(res, irg); 5995 5996 return res; 5997} 5998 5999/** 6000 * construct Cltd node 6001 */ 6002ir_node *new_bd_ia32_Cltd(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *clobbered) 6003{ 6004 ir_graph *irg = get_irn_irg(block); 6005 ir_op *op = op_ia32_Cltd; 6006 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 6007 ir_node *res; 6008 backend_info_t *info; 6009 int arity = 2; 6010 ir_node *in[2]; 6011 int n_res = 1; 6012 ir_mode *mode = mode_Iu; 6013 static const arch_register_req_t *in_reqs[] = 6014 { 6015 & ia32_requirements_gp_eax, 6016 & ia32_requirements_gp_edx, 6017 }; 6018 6019 /* construct in array */ 6020 in[0] = val; 6021 in[1] = clobbered; 6022 6023 /* create node */ 6024 assert(op != NULL); 6025 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 6026 6027 /* init node attributes */ 6028 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 6029 6030 info = be_get_info(res); 6031 (void) info; /* avoid potential warning */ 6032 info->out_infos[0].req = &ia32_requirements_gp_edx; 6033 6034 6035 /* optimize node */ 6036 res = optimize_node(res); 6037 irn_verify_irg(res, irg); 6038 6039 return res; 6040} 6041 6042/** 6043 * construct xPsrld node 6044 */ 6045ir_node *new_bd_ia32_xPsrld(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_node *op1) 6046{ 6047 ir_graph *irg = get_irn_irg(block); 6048 ir_op *op = op_ia32_xPsrld; 6049 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 6050 ir_node *res; 6051 backend_info_t *info; 6052 int arity = 2; 6053 ir_node *in[2]; 6054 int n_res = 1; 6055 ir_mode *mode = mode_D; 6056 static const arch_register_req_t *in_reqs[] = 6057 { 6058 & ia32_requirements_xmm_xmm, 6059 & ia32_requirements_xmm_xmm, 6060 }; 6061 6062 /* construct in array */ 6063 in[0] = op0; 6064 in[1] = op1; 6065 6066 /* flags */ 6067 irn_flags_ |= arch_irn_flags_rematerializable; 6068 6069 /* create node */ 6070 assert(op != NULL); 6071 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 6072 6073 /* init node attributes */ 6074 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 6075 6076 info = be_get_info(res); 6077 (void) info; /* avoid potential warning */ 6078 info->out_infos[0].req = &ia32_requirements_xmm_in_r1_not_in_r2; 6079 6080 6081 /* optimize node */ 6082 res = optimize_node(res); 6083 irn_verify_irg(res, irg); 6084 6085 return res; 6086} 6087 6088/** 6089 * construct PushEax node 6090 */ 6091ir_node *new_bd_ia32_PushEax(dbg_info *dbgi, ir_node *block, ir_node *stack) 6092{ 6093 ir_graph *irg = get_irn_irg(block); 6094 ir_op *op = op_ia32_PushEax; 6095 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 6096 ir_node *res; 6097 backend_info_t *info; 6098 int arity = 1; 6099 ir_node *in[1]; 6100 int n_res = 1; 6101 ir_mode *mode = mode_Iu; 6102 static const arch_register_req_t *in_reqs[] = 6103 { 6104 & ia32_requirements_gp_esp, 6105 }; 6106 6107 /* construct in array */ 6108 in[0] = stack; 6109 6110 /* create node */ 6111 assert(op != NULL); 6112 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 6113 6114 /* init node attributes */ 6115 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 6116 6117 info = be_get_info(res); 6118 (void) info; /* avoid potential warning */ 6119 info->out_infos[0].req = &ia32_requirements_gp_esp_I_S; 6120 6121 6122 /* optimize node */ 6123 res = optimize_node(res); 6124 irn_verify_irg(res, irg); 6125 6126 return res; 6127} 6128 6129/** 6130 * construct XorHighLow node 6131 */ 6132ir_node *new_bd_ia32_XorHighLow(dbg_info *dbgi, ir_node *block, ir_node *value) 6133{ 6134 ir_graph *irg = get_irn_irg(block); 6135 ir_op *op = op_ia32_XorHighLow; 6136 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 6137 ir_node *res; 6138 backend_info_t *info; 6139 int arity = 1; 6140 ir_node *in[1]; 6141 int n_res = 2; 6142 ir_mode *mode = mode_Iu; 6143 static const arch_register_req_t *in_reqs[] = 6144 { 6145 & ia32_requirements_gp_eax_ebx_ecx_edx, 6146 }; 6147 6148 /* construct in array */ 6149 in[0] = value; 6150 6151 /* flags */ 6152 irn_flags_ |= arch_irn_flags_rematerializable; 6153 6154 /* create node */ 6155 assert(op != NULL); 6156 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 6157 6158 /* init node attributes */ 6159 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 6160 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 6161 6162 info = be_get_info(res); 6163 (void) info; /* avoid potential warning */ 6164 info->out_infos[0].req = &ia32_requirements_gp_in_r1; 6165 info->out_infos[1].req = &ia32_requirements_flags_flags; 6166 6167 6168 /* optimize node */ 6169 res = optimize_node(res); 6170 irn_verify_irg(res, irg); 6171 6172 return res; 6173} 6174 6175/** 6176 * construct xPzero node 6177 */ 6178ir_node *new_bd_ia32_xPzero(dbg_info *dbgi, ir_node *block) 6179{ 6180 ir_graph *irg = get_irn_irg(block); 6181 ir_op *op = op_ia32_xPzero; 6182 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 6183 ir_node *res; 6184 backend_info_t *info; 6185 int arity = 0; 6186 ir_node **in = NULL; 6187 int n_res = 1; 6188 ir_mode *mode = mode_D; 6189 static const arch_register_req_t **in_reqs = NULL; 6190 6191 /* flags */ 6192 irn_flags_ |= arch_irn_flags_rematerializable; 6193 6194 /* create node */ 6195 assert(op != NULL); 6196 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 6197 6198 /* init node attributes */ 6199 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 6200 6201 info = be_get_info(res); 6202 (void) info; /* avoid potential warning */ 6203 info->out_infos[0].req = &ia32_requirements_xmm_xmm; 6204 6205 6206 /* optimize node */ 6207 res = optimize_node(res); 6208 irn_verify_irg(res, irg); 6209 6210 return res; 6211} 6212 6213/** 6214 * construct Rol node 6215 */ 6216ir_node *new_bd_ia32_Rol(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count) 6217{ 6218 ir_graph *irg = get_irn_irg(block); 6219 ir_op *op = op_ia32_Rol; 6220 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 6221 ir_node *res; 6222 backend_info_t *info; 6223 int arity = 2; 6224 ir_node *in[2]; 6225 int n_res = 2; 6226 ir_mode *mode = mode_Iu; 6227 static const arch_register_req_t *in_reqs[] = 6228 { 6229 & ia32_requirements_gp_gp, 6230 & ia32_requirements_gp_ecx, 6231 }; 6232 6233 /* construct in array */ 6234 in[0] = val; 6235 in[1] = count; 6236 6237 /* flags */ 6238 irn_flags_ |= arch_irn_flags_rematerializable; 6239 6240 /* create node */ 6241 assert(op != NULL); 6242 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 6243 6244 /* init node attributes */ 6245 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 6246 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 6247 6248 info = be_get_info(res); 6249 (void) info; /* avoid potential warning */ 6250 info->out_infos[0].req = &ia32_requirements_gp_in_r1_not_in_r2; 6251 info->out_infos[1].req = &ia32_requirements_flags_flags; 6252 6253 6254 /* optimize node */ 6255 res = optimize_node(res); 6256 irn_verify_irg(res, irg); 6257 6258 return res; 6259} 6260 6261/** 6262 * construct Cmc node 6263 */ 6264ir_node *new_bd_ia32_Cmc(dbg_info *dbgi, ir_node *block, ir_node *op0) 6265{ 6266 ir_graph *irg = get_irn_irg(block); 6267 ir_op *op = op_ia32_Cmc; 6268 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 6269 ir_node *res; 6270 backend_info_t *info; 6271 int arity = 1; 6272 ir_node *in[1]; 6273 int n_res = 1; 6274 ir_mode *mode = mode_Iu; 6275 static const arch_register_req_t *in_reqs[] = 6276 { 6277 & ia32_requirements_flags_flags, 6278 }; 6279 6280 /* construct in array */ 6281 in[0] = op0; 6282 6283 /* create node */ 6284 assert(op != NULL); 6285 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 6286 6287 /* init node attributes */ 6288 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 6289 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 6290 6291 info = be_get_info(res); 6292 (void) info; /* avoid potential warning */ 6293 info->out_infos[0].req = &ia32_requirements_flags_flags; 6294 6295 6296 /* optimize node */ 6297 res = optimize_node(res); 6298 irn_verify_irg(res, irg); 6299 6300 return res; 6301} 6302 6303/** 6304 * construct Cmp8Bit node 6305 */ 6306ir_node *new_bd_ia32_Cmp8Bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, bool ins_permuted) 6307{ 6308 ir_graph *irg = get_irn_irg(block); 6309 ir_op *op = op_ia32_Cmp8Bit; 6310 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 6311 ir_node *res; 6312 backend_info_t *info; 6313 int arity = 5; 6314 ir_node *in[5]; 6315 int n_res = 3; 6316 ir_mode *mode = mode_Iu; 6317 static const arch_register_req_t *in_reqs[] = 6318 { 6319 & ia32_requirements_gp_gp, 6320 & ia32_requirements_gp_gp, 6321 & ia32_requirements__none, 6322 & ia32_requirements_gp_eax_ebx_ecx_edx, 6323 & ia32_requirements_gp_eax_ebx_ecx_edx, 6324 }; 6325 ia32_attr_t *attr; 6326 6327 /* construct in array */ 6328 in[0] = base; 6329 in[1] = index; 6330 in[2] = mem; 6331 in[3] = left; 6332 in[4] = right; 6333 6334 /* flags */ 6335 irn_flags_ |= arch_irn_flags_rematerializable; 6336 6337 /* create node */ 6338 assert(op != NULL); 6339 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 6340 6341 /* init node attributes */ 6342 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 6343 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 6344 set_ia32_am_support(res, ia32_am_binary); 6345 info = be_get_info(res); 6346 (void) info; /* avoid potential warning */ 6347 info->out_infos[0].req = &ia32_requirements_flags_flags; 6348 info->out_infos[1].req = &ia32_requirements__none; 6349 info->out_infos[2].req = &ia32_requirements__none; 6350 6351 6352 attr = (ia32_attr_t*)get_irn_generic_attr(res); 6353 (void) attr; /* avoid potential warning */ 6354 attr->data.ins_permuted = ins_permuted; 6355 /* optimize node */ 6356 res = optimize_node(res); 6357 irn_verify_irg(res, irg); 6358 6359 return res; 6360} 6361 6362/** 6363 * construct xDiv node 6364 */ 6365ir_node *new_bd_ia32_xDiv(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *dividend, ir_node *divisor) 6366{ 6367 ir_graph *irg = get_irn_irg(block); 6368 ir_op *op = op_ia32_xDiv; 6369 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 6370 ir_node *res; 6371 backend_info_t *info; 6372 int arity = 5; 6373 ir_node *in[5]; 6374 int n_res = 3; 6375 ir_mode *mode = mode_T; 6376 static const arch_register_req_t *in_reqs[] = 6377 { 6378 & ia32_requirements_gp_gp, 6379 & ia32_requirements_gp_gp, 6380 & ia32_requirements__none, 6381 & ia32_requirements_xmm_xmm, 6382 & ia32_requirements_xmm_xmm, 6383 }; 6384 6385 /* construct in array */ 6386 in[0] = base; 6387 in[1] = index; 6388 in[2] = mem; 6389 in[3] = dividend; 6390 in[4] = divisor; 6391 6392 /* flags */ 6393 irn_flags_ |= arch_irn_flags_rematerializable; 6394 6395 /* create node */ 6396 assert(op != NULL); 6397 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 6398 6399 /* init node attributes */ 6400 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 6401 set_ia32_am_support(res, ia32_am_binary); 6402 info = be_get_info(res); 6403 (void) info; /* avoid potential warning */ 6404 info->out_infos[0].req = &ia32_requirements_xmm_in_r4_not_in_r5; 6405 info->out_infos[1].req = &ia32_requirements_flags_flags; 6406 info->out_infos[2].req = &ia32_requirements__none; 6407 6408 6409 /* optimize node */ 6410 res = optimize_node(res); 6411 irn_verify_irg(res, irg); 6412 6413 return res; 6414} 6415 6416/** 6417 * construct xUnknown node 6418 */ 6419ir_node *new_bd_ia32_xUnknown(dbg_info *dbgi, ir_node *block) 6420{ 6421 ir_graph *irg = get_irn_irg(block); 6422 ir_op *op = op_ia32_xUnknown; 6423 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 6424 ir_node *res; 6425 backend_info_t *info; 6426 int arity = 0; 6427 ir_node **in = NULL; 6428 int n_res = 1; 6429 ir_mode *mode = mode_D; 6430 static const arch_register_req_t **in_reqs = NULL; 6431 6432 /* flags */ 6433 irn_flags_ |= arch_irn_flags_rematerializable; 6434 6435 /* create node */ 6436 assert(op != NULL); 6437 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 6438 6439 /* init node attributes */ 6440 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 6441 6442 info = be_get_info(res); 6443 (void) info; /* avoid potential warning */ 6444 info->out_infos[0].req = &ia32_requirements_xmm_xmm; 6445 6446 6447 /* optimize node */ 6448 res = optimize_node(res); 6449 irn_verify_irg(res, irg); 6450 6451 return res; 6452} 6453 6454/** 6455 * construct Test8Bit node 6456 */ 6457ir_node *new_bd_ia32_Test8Bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, bool ins_permuted) 6458{ 6459 ir_graph *irg = get_irn_irg(block); 6460 ir_op *op = op_ia32_Test8Bit; 6461 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 6462 ir_node *res; 6463 backend_info_t *info; 6464 int arity = 5; 6465 ir_node *in[5]; 6466 int n_res = 3; 6467 ir_mode *mode = mode_Iu; 6468 static const arch_register_req_t *in_reqs[] = 6469 { 6470 & ia32_requirements_gp_gp, 6471 & ia32_requirements_gp_gp, 6472 & ia32_requirements__none, 6473 & ia32_requirements_gp_eax_ebx_ecx_edx, 6474 & ia32_requirements_gp_eax_ebx_ecx_edx, 6475 }; 6476 ia32_attr_t *attr; 6477 6478 /* construct in array */ 6479 in[0] = base; 6480 in[1] = index; 6481 in[2] = mem; 6482 in[3] = left; 6483 in[4] = right; 6484 6485 /* flags */ 6486 irn_flags_ |= arch_irn_flags_rematerializable; 6487 6488 /* create node */ 6489 assert(op != NULL); 6490 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 6491 6492 /* init node attributes */ 6493 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 6494 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 6495 set_ia32_am_support(res, ia32_am_binary); 6496 info = be_get_info(res); 6497 (void) info; /* avoid potential warning */ 6498 info->out_infos[0].req = &ia32_requirements_flags_flags; 6499 info->out_infos[1].req = &ia32_requirements__none; 6500 info->out_infos[2].req = &ia32_requirements__none; 6501 6502 6503 attr = (ia32_attr_t*)get_irn_generic_attr(res); 6504 (void) attr; /* avoid potential warning */ 6505 attr->data.ins_permuted = ins_permuted; 6506 /* optimize node */ 6507 res = optimize_node(res); 6508 irn_verify_irg(res, irg); 6509 6510 return res; 6511} 6512 6513/** 6514 * construct Sub node 6515 */ 6516ir_node *new_bd_ia32_Sub(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *minuend, ir_node *subtrahend) 6517{ 6518 ir_graph *irg = get_irn_irg(block); 6519 ir_op *op = op_ia32_Sub; 6520 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 6521 ir_node *res; 6522 backend_info_t *info; 6523 int arity = 5; 6524 ir_node *in[5]; 6525 int n_res = 3; 6526 ir_mode *mode = mode_Iu; 6527 static const arch_register_req_t *in_reqs[] = 6528 { 6529 & ia32_requirements_gp_gp, 6530 & ia32_requirements_gp_gp, 6531 & ia32_requirements__none, 6532 & ia32_requirements_gp_gp, 6533 & ia32_requirements_gp_gp, 6534 }; 6535 6536 /* construct in array */ 6537 in[0] = base; 6538 in[1] = index; 6539 in[2] = mem; 6540 in[3] = minuend; 6541 in[4] = subtrahend; 6542 6543 /* flags */ 6544 irn_flags_ |= arch_irn_flags_rematerializable; 6545 6546 /* create node */ 6547 assert(op != NULL); 6548 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 6549 6550 /* init node attributes */ 6551 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 6552 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 6553 set_ia32_am_support(res, ia32_am_binary); 6554 info = be_get_info(res); 6555 (void) info; /* avoid potential warning */ 6556 info->out_infos[0].req = &ia32_requirements_gp_in_r4; 6557 info->out_infos[1].req = &ia32_requirements_flags_flags; 6558 info->out_infos[2].req = &ia32_requirements__none; 6559 6560 6561 /* optimize node */ 6562 res = optimize_node(res); 6563 irn_verify_irg(res, irg); 6564 6565 return res; 6566} 6567 6568/** 6569 * construct PrefetchNTA node 6570 */ 6571ir_node *new_bd_ia32_PrefetchNTA(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem) 6572{ 6573 ir_graph *irg = get_irn_irg(block); 6574 ir_op *op = op_ia32_PrefetchNTA; 6575 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 6576 ir_node *res; 6577 backend_info_t *info; 6578 int arity = 3; 6579 ir_node *in[3]; 6580 int n_res = 1; 6581 ir_mode *mode = mode_T; 6582 static const arch_register_req_t *in_reqs[] = 6583 { 6584 & ia32_requirements_gp_gp, 6585 & ia32_requirements_gp_gp, 6586 & ia32_requirements__none, 6587 }; 6588 6589 /* construct in array */ 6590 in[0] = base; 6591 in[1] = index; 6592 in[2] = mem; 6593 6594 /* create node */ 6595 assert(op != NULL); 6596 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 6597 6598 /* init node attributes */ 6599 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 6600 6601 info = be_get_info(res); 6602 (void) info; /* avoid potential warning */ 6603 info->out_infos[0].req = &ia32_requirements__none; 6604 6605 6606 /* optimize node */ 6607 res = optimize_node(res); 6608 irn_verify_irg(res, irg); 6609 6610 return res; 6611} 6612 6613/** 6614 * construct Shr node 6615 */ 6616ir_node *new_bd_ia32_Shr(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count) 6617{ 6618 ir_graph *irg = get_irn_irg(block); 6619 ir_op *op = op_ia32_Shr; 6620 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 6621 ir_node *res; 6622 backend_info_t *info; 6623 int arity = 2; 6624 ir_node *in[2]; 6625 int n_res = 2; 6626 ir_mode *mode = mode_Iu; 6627 static const arch_register_req_t *in_reqs[] = 6628 { 6629 & ia32_requirements_gp_gp, 6630 & ia32_requirements_gp_ecx, 6631 }; 6632 6633 /* construct in array */ 6634 in[0] = val; 6635 in[1] = count; 6636 6637 /* flags */ 6638 irn_flags_ |= arch_irn_flags_rematerializable; 6639 6640 /* create node */ 6641 assert(op != NULL); 6642 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 6643 6644 /* init node attributes */ 6645 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 6646 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 6647 6648 info = be_get_info(res); 6649 (void) info; /* avoid potential warning */ 6650 info->out_infos[0].req = &ia32_requirements_gp_in_r1_not_in_r2; 6651 info->out_infos[1].req = &ia32_requirements_flags_flags; 6652 6653 6654 /* optimize node */ 6655 res = optimize_node(res); 6656 irn_verify_irg(res, irg); 6657 6658 return res; 6659} 6660 6661/** 6662 * construct fprem node 6663 */ 6664ir_node *new_bd_ia32_fprem(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_node *fpcw) 6665{ 6666 ir_graph *irg = get_irn_irg(block); 6667 ir_op *op = op_ia32_fprem; 6668 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 6669 ir_node *res; 6670 backend_info_t *info; 6671 int arity = 3; 6672 ir_node *in[3]; 6673 int n_res = 1; 6674 ir_mode *mode = ia32_mode_E; 6675 static const arch_register_req_t *in_reqs[] = 6676 { 6677 & ia32_requirements_fp_fp, 6678 & ia32_requirements_fp_fp, 6679 & ia32_requirements_fp_cw_fpcw, 6680 }; 6681 6682 /* construct in array */ 6683 in[0] = left; 6684 in[1] = right; 6685 in[2] = fpcw; 6686 6687 /* create node */ 6688 assert(op != NULL); 6689 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 6690 6691 /* init node attributes */ 6692 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 6693 init_ia32_x87_attributes(res); 6694 6695 info = be_get_info(res); 6696 (void) info; /* avoid potential warning */ 6697 info->out_infos[0].req = &ia32_requirements_fp_fp; 6698 6699 6700 /* optimize node */ 6701 res = optimize_node(res); 6702 irn_verify_irg(res, irg); 6703 6704 return res; 6705} 6706 6707/** 6708 * construct IDiv node 6709 */ 6710ir_node *new_bd_ia32_IDiv(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *divisor, ir_node *dividend_low, ir_node *dividend_high) 6711{ 6712 ir_graph *irg = get_irn_irg(block); 6713 ir_op *op = op_ia32_IDiv; 6714 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 6715 ir_node *res; 6716 backend_info_t *info; 6717 int arity = 6; 6718 ir_node *in[6]; 6719 int n_res = 6; 6720 ir_mode *mode = mode_T; 6721 static const arch_register_req_t *in_reqs[] = 6722 { 6723 & ia32_requirements_gp_gp, 6724 & ia32_requirements_gp_gp, 6725 & ia32_requirements__none, 6726 & ia32_requirements_gp_gp, 6727 & ia32_requirements_gp_eax, 6728 & ia32_requirements_gp_edx, 6729 }; 6730 6731 /* construct in array */ 6732 in[0] = base; 6733 in[1] = index; 6734 in[2] = mem; 6735 in[3] = divisor; 6736 in[4] = dividend_low; 6737 in[5] = dividend_high; 6738 6739 /* create node */ 6740 assert(op != NULL); 6741 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 6742 6743 /* init node attributes */ 6744 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 6745 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 6746 set_ia32_am_support(res, ia32_am_unary); 6747 info = be_get_info(res); 6748 (void) info; /* avoid potential warning */ 6749 info->out_infos[0].req = &ia32_requirements_gp_eax; 6750 info->out_infos[1].req = &ia32_requirements_flags_flags; 6751 info->out_infos[2].req = &ia32_requirements__none; 6752 info->out_infos[3].req = &ia32_requirements_gp_edx; 6753 info->out_infos[4].req = &ia32_requirements__none; 6754 info->out_infos[5].req = &ia32_requirements__none; 6755 6756 6757 /* optimize node */ 6758 res = optimize_node(res); 6759 irn_verify_irg(res, irg); 6760 6761 return res; 6762} 6763 6764/** 6765 * construct l_Adc node 6766 */ 6767ir_node *new_bd_ia32_l_Adc(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_node *eflags, ir_mode *mode) 6768{ 6769 ir_graph *irg = get_irn_irg(block); 6770 ir_op *op = op_ia32_l_Adc; 6771 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 6772 ir_node *res; 6773 backend_info_t *info; 6774 int arity = 3; 6775 ir_node *in[3]; 6776 int n_res = 0; 6777 static const arch_register_req_t **in_reqs = NULL; 6778 6779 /* construct in array */ 6780 in[0] = left; 6781 in[1] = right; 6782 in[2] = eflags; 6783 6784 /* create node */ 6785 assert(op != NULL); 6786 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 6787 6788 /* init node attributes */ 6789 (void)in;(void)irn_flags_;(void)in_reqs;(void)n_res; 6790 6791 info = be_get_info(res); 6792 (void) info; /* avoid potential warning */ 6793 6794 6795 /* optimize node */ 6796 res = optimize_node(res); 6797 irn_verify_irg(res, irg); 6798 6799 return res; 6800} 6801 6802/** 6803 * construct Setcc node 6804 */ 6805ir_node *new_bd_ia32_Setcc(dbg_info *dbgi, ir_node *block, ir_node *eflags, ia32_condition_code_t condition_code) 6806{ 6807 ir_graph *irg = get_irn_irg(block); 6808 ir_op *op = op_ia32_Setcc; 6809 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 6810 ir_node *res; 6811 backend_info_t *info; 6812 int arity = 1; 6813 ir_node *in[1]; 6814 int n_res = 1; 6815 ir_mode *mode = mode_Iu; 6816 static const arch_register_req_t *in_reqs[] = 6817 { 6818 & ia32_requirements_flags_eflags, 6819 }; 6820 ia32_condcode_attr_t *attr; 6821 6822 /* construct in array */ 6823 in[0] = eflags; 6824 6825 /* create node */ 6826 assert(op != NULL); 6827 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 6828 6829 /* init node attributes */ 6830 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 6831 init_ia32_condcode_attributes(res, condition_code); 6832 6833 info = be_get_info(res); 6834 (void) info; /* avoid potential warning */ 6835 info->out_infos[0].req = &ia32_requirements_gp_eax_ebx_ecx_edx; 6836 6837 6838 attr = (ia32_condcode_attr_t*)get_irn_generic_attr(res); 6839 (void) attr; /* avoid potential warning */ 6840 set_ia32_ls_mode(res, mode_Bu); 6841 if (condition_code & ia32_cc_additional_float_cases) { 6842 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 6843 /* attr->latency = 3; */ 6844 } 6845 6846 /* optimize node */ 6847 res = optimize_node(res); 6848 irn_verify_irg(res, irg); 6849 6850 return res; 6851} 6852 6853/** 6854 * construct l_LLtoFloat node 6855 */ 6856ir_node *new_bd_ia32_l_LLtoFloat(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_mode *mode) 6857{ 6858 ir_graph *irg = get_irn_irg(block); 6859 ir_op *op = op_ia32_l_LLtoFloat; 6860 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 6861 ir_node *res; 6862 backend_info_t *info; 6863 int arity = 2; 6864 ir_node *in[2]; 6865 int n_res = 0; 6866 static const arch_register_req_t **in_reqs = NULL; 6867 6868 /* construct in array */ 6869 in[0] = val_high; 6870 in[1] = val_low; 6871 6872 /* create node */ 6873 assert(op != NULL); 6874 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 6875 6876 /* init node attributes */ 6877 (void)in;(void)irn_flags_;(void)in_reqs;(void)n_res; 6878 6879 info = be_get_info(res); 6880 (void) info; /* avoid potential warning */ 6881 6882 6883 /* optimize node */ 6884 res = optimize_node(res); 6885 irn_verify_irg(res, irg); 6886 6887 return res; 6888} 6889 6890/** 6891 * construct ProduceVal node 6892 */ 6893ir_node *new_bd_ia32_ProduceVal(dbg_info *dbgi, ir_node *block) 6894{ 6895 ir_graph *irg = get_irn_irg(block); 6896 ir_op *op = op_ia32_ProduceVal; 6897 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 6898 ir_node *res; 6899 backend_info_t *info; 6900 int arity = 0; 6901 ir_node **in = NULL; 6902 int n_res = 1; 6903 ir_mode *mode = mode_Iu; 6904 static const arch_register_req_t **in_reqs = NULL; 6905 6906 /* flags */ 6907 irn_flags_ |= arch_irn_flags_rematerializable; 6908 6909 /* create node */ 6910 assert(op != NULL); 6911 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 6912 6913 /* init node attributes */ 6914 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 6915 6916 info = be_get_info(res); 6917 (void) info; /* avoid potential warning */ 6918 info->out_infos[0].req = &ia32_requirements_gp_gp; 6919 6920 6921 /* optimize node */ 6922 res = optimize_node(res); 6923 irn_verify_irg(res, irg); 6924 6925 return res; 6926} 6927 6928/** 6929 * construct Bswap node 6930 */ 6931ir_node *new_bd_ia32_Bswap(dbg_info *dbgi, ir_node *block, ir_node *val) 6932{ 6933 ir_graph *irg = get_irn_irg(block); 6934 ir_op *op = op_ia32_Bswap; 6935 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 6936 ir_node *res; 6937 backend_info_t *info; 6938 int arity = 1; 6939 ir_node *in[1]; 6940 int n_res = 1; 6941 ir_mode *mode = mode_Iu; 6942 static const arch_register_req_t *in_reqs[] = 6943 { 6944 & ia32_requirements_gp_gp, 6945 }; 6946 6947 /* construct in array */ 6948 in[0] = val; 6949 6950 /* flags */ 6951 irn_flags_ |= arch_irn_flags_rematerializable; 6952 6953 /* create node */ 6954 assert(op != NULL); 6955 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 6956 6957 /* init node attributes */ 6958 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 6959 6960 info = be_get_info(res); 6961 (void) info; /* avoid potential warning */ 6962 info->out_infos[0].req = &ia32_requirements_gp_in_r1; 6963 6964 6965 /* optimize node */ 6966 res = optimize_node(res); 6967 irn_verify_irg(res, irg); 6968 6969 return res; 6970} 6971 6972/** 6973 * construct SetccMem node 6974 */ 6975ir_node *new_bd_ia32_SetccMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *eflags, ia32_condition_code_t condition_code) 6976{ 6977 ir_graph *irg = get_irn_irg(block); 6978 ir_op *op = op_ia32_SetccMem; 6979 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 6980 ir_node *res; 6981 backend_info_t *info; 6982 int arity = 4; 6983 ir_node *in[4]; 6984 int n_res = 1; 6985 ir_mode *mode = mode_M; 6986 static const arch_register_req_t *in_reqs[] = 6987 { 6988 & ia32_requirements_gp_gp, 6989 & ia32_requirements_gp_gp, 6990 & ia32_requirements__none, 6991 & ia32_requirements_flags_eflags, 6992 }; 6993 ia32_condcode_attr_t *attr; 6994 6995 /* construct in array */ 6996 in[0] = base; 6997 in[1] = index; 6998 in[2] = mem; 6999 in[3] = eflags; 7000 7001 /* create node */ 7002 assert(op != NULL); 7003 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 7004 7005 /* init node attributes */ 7006 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 7007 init_ia32_condcode_attributes(res, condition_code); 7008 7009 info = be_get_info(res); 7010 (void) info; /* avoid potential warning */ 7011 info->out_infos[0].req = &ia32_requirements__none; 7012 7013 7014 attr = (ia32_condcode_attr_t*)get_irn_generic_attr(res); 7015 (void) attr; /* avoid potential warning */ 7016 set_ia32_ls_mode(res, mode_Bu); 7017 7018 /* optimize node */ 7019 res = optimize_node(res); 7020 irn_verify_irg(res, irg); 7021 7022 return res; 7023} 7024 7025/** 7026 * construct Test node 7027 */ 7028ir_node *new_bd_ia32_Test(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, bool ins_permuted) 7029{ 7030 ir_graph *irg = get_irn_irg(block); 7031 ir_op *op = op_ia32_Test; 7032 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 7033 ir_node *res; 7034 backend_info_t *info; 7035 int arity = 5; 7036 ir_node *in[5]; 7037 int n_res = 3; 7038 ir_mode *mode = mode_Iu; 7039 static const arch_register_req_t *in_reqs[] = 7040 { 7041 & ia32_requirements_gp_gp, 7042 & ia32_requirements_gp_gp, 7043 & ia32_requirements__none, 7044 & ia32_requirements_gp_gp, 7045 & ia32_requirements_gp_gp, 7046 }; 7047 ia32_attr_t *attr; 7048 7049 /* construct in array */ 7050 in[0] = base; 7051 in[1] = index; 7052 in[2] = mem; 7053 in[3] = left; 7054 in[4] = right; 7055 7056 /* flags */ 7057 irn_flags_ |= arch_irn_flags_rematerializable; 7058 7059 /* create node */ 7060 assert(op != NULL); 7061 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 7062 7063 /* init node attributes */ 7064 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 7065 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 7066 set_ia32_am_support(res, ia32_am_binary); 7067 info = be_get_info(res); 7068 (void) info; /* avoid potential warning */ 7069 info->out_infos[0].req = &ia32_requirements_flags_flags; 7070 info->out_infos[1].req = &ia32_requirements__none; 7071 info->out_infos[2].req = &ia32_requirements__none; 7072 7073 7074 attr = (ia32_attr_t*)get_irn_generic_attr(res); 7075 (void) attr; /* avoid potential warning */ 7076 attr->data.ins_permuted = ins_permuted; 7077 /* optimize node */ 7078 res = optimize_node(res); 7079 irn_verify_irg(res, irg); 7080 7081 return res; 7082} 7083 7084/** 7085 * construct l_Add node 7086 */ 7087ir_node *new_bd_ia32_l_Add(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right, ir_mode *mode) 7088{ 7089 ir_graph *irg = get_irn_irg(block); 7090 ir_op *op = op_ia32_l_Add; 7091 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 7092 ir_node *res; 7093 backend_info_t *info; 7094 int arity = 2; 7095 ir_node *in[2]; 7096 int n_res = 0; 7097 static const arch_register_req_t **in_reqs = NULL; 7098 7099 /* construct in array */ 7100 in[0] = left; 7101 in[1] = right; 7102 7103 /* create node */ 7104 assert(op != NULL); 7105 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 7106 7107 /* init node attributes */ 7108 (void)in;(void)irn_flags_;(void)in_reqs;(void)n_res; 7109 7110 info = be_get_info(res); 7111 (void) info; /* avoid potential warning */ 7112 7113 7114 /* optimize node */ 7115 res = optimize_node(res); 7116 irn_verify_irg(res, irg); 7117 7118 return res; 7119} 7120 7121/** 7122 * construct AddSP node 7123 */ 7124ir_node *new_bd_ia32_AddSP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *stack, ir_node *size) 7125{ 7126 ir_graph *irg = get_irn_irg(block); 7127 ir_op *op = op_ia32_AddSP; 7128 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 7129 ir_node *res; 7130 backend_info_t *info; 7131 int arity = 5; 7132 ir_node *in[5]; 7133 int n_res = 2; 7134 ir_mode *mode = mode_T; 7135 static const arch_register_req_t *in_reqs[] = 7136 { 7137 & ia32_requirements_gp_gp, 7138 & ia32_requirements_gp_gp, 7139 & ia32_requirements__none, 7140 & ia32_requirements_gp_esp, 7141 & ia32_requirements_gp_gp, 7142 }; 7143 7144 /* construct in array */ 7145 in[0] = base; 7146 in[1] = index; 7147 in[2] = mem; 7148 in[3] = stack; 7149 in[4] = size; 7150 7151 /* create node */ 7152 assert(op != NULL); 7153 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 7154 7155 /* init node attributes */ 7156 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 7157 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 7158 set_ia32_am_support(res, ia32_am_binary); 7159 info = be_get_info(res); 7160 (void) info; /* avoid potential warning */ 7161 info->out_infos[0].req = &ia32_requirements_gp_esp_I_S; 7162 info->out_infos[1].req = &ia32_requirements__none; 7163 7164 7165 /* optimize node */ 7166 res = optimize_node(res); 7167 irn_verify_irg(res, irg); 7168 7169 return res; 7170} 7171 7172/** 7173 * construct RolMem node 7174 */ 7175ir_node *new_bd_ia32_RolMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count) 7176{ 7177 ir_graph *irg = get_irn_irg(block); 7178 ir_op *op = op_ia32_RolMem; 7179 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 7180 ir_node *res; 7181 backend_info_t *info; 7182 int arity = 4; 7183 ir_node *in[4]; 7184 int n_res = 1; 7185 ir_mode *mode = mode_M; 7186 static const arch_register_req_t *in_reqs[] = 7187 { 7188 & ia32_requirements_gp_gp, 7189 & ia32_requirements_gp_gp, 7190 & ia32_requirements__none, 7191 & ia32_requirements_gp_ecx, 7192 }; 7193 7194 /* construct in array */ 7195 in[0] = base; 7196 in[1] = index; 7197 in[2] = mem; 7198 in[3] = count; 7199 7200 /* flags */ 7201 irn_flags_ |= arch_irn_flags_rematerializable; 7202 7203 /* create node */ 7204 assert(op != NULL); 7205 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 7206 7207 /* init node attributes */ 7208 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 7209 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 7210 7211 info = be_get_info(res); 7212 (void) info; /* avoid potential warning */ 7213 info->out_infos[0].req = &ia32_requirements__none; 7214 7215 7216 /* optimize node */ 7217 res = optimize_node(res); 7218 irn_verify_irg(res, irg); 7219 7220 return res; 7221} 7222 7223/** 7224 * construct Conv_I2FP node 7225 */ 7226ir_node *new_bd_ia32_Conv_I2FP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val) 7227{ 7228 ir_graph *irg = get_irn_irg(block); 7229 ir_op *op = op_ia32_Conv_I2FP; 7230 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 7231 ir_node *res; 7232 backend_info_t *info; 7233 int arity = 4; 7234 ir_node *in[4]; 7235 int n_res = 2; 7236 ir_mode *mode = mode_D; 7237 static const arch_register_req_t *in_reqs[] = 7238 { 7239 & ia32_requirements_gp_gp, 7240 & ia32_requirements_gp_gp, 7241 & ia32_requirements__none, 7242 & ia32_requirements_gp_gp, 7243 }; 7244 7245 /* construct in array */ 7246 in[0] = base; 7247 in[1] = index; 7248 in[2] = mem; 7249 in[3] = val; 7250 7251 /* create node */ 7252 assert(op != NULL); 7253 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 7254 7255 /* init node attributes */ 7256 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 7257 set_ia32_am_support(res, ia32_am_unary); 7258 info = be_get_info(res); 7259 (void) info; /* avoid potential warning */ 7260 info->out_infos[0].req = &ia32_requirements_xmm_xmm; 7261 info->out_infos[1].req = &ia32_requirements__none; 7262 7263 7264 /* optimize node */ 7265 res = optimize_node(res); 7266 irn_verify_irg(res, irg); 7267 7268 return res; 7269} 7270 7271/** 7272 * construct Conv_FP2FP node 7273 */ 7274ir_node *new_bd_ia32_Conv_FP2FP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val) 7275{ 7276 ir_graph *irg = get_irn_irg(block); 7277 ir_op *op = op_ia32_Conv_FP2FP; 7278 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 7279 ir_node *res; 7280 backend_info_t *info; 7281 int arity = 4; 7282 ir_node *in[4]; 7283 int n_res = 2; 7284 ir_mode *mode = mode_D; 7285 static const arch_register_req_t *in_reqs[] = 7286 { 7287 & ia32_requirements_gp_gp, 7288 & ia32_requirements_gp_gp, 7289 & ia32_requirements__none, 7290 & ia32_requirements_xmm_xmm, 7291 }; 7292 7293 /* construct in array */ 7294 in[0] = base; 7295 in[1] = index; 7296 in[2] = mem; 7297 in[3] = val; 7298 7299 /* create node */ 7300 assert(op != NULL); 7301 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 7302 7303 /* init node attributes */ 7304 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 7305 set_ia32_am_support(res, ia32_am_unary); 7306 info = be_get_info(res); 7307 (void) info; /* avoid potential warning */ 7308 info->out_infos[0].req = &ia32_requirements_xmm_xmm; 7309 info->out_infos[1].req = &ia32_requirements__none; 7310 7311 7312 /* optimize node */ 7313 res = optimize_node(res); 7314 irn_verify_irg(res, irg); 7315 7316 return res; 7317} 7318 7319/** 7320 * construct ChangeCW node 7321 */ 7322ir_node *new_bd_ia32_ChangeCW(dbg_info *dbgi, ir_node *block) 7323{ 7324 ir_graph *irg = get_irn_irg(block); 7325 ir_op *op = op_ia32_ChangeCW; 7326 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 7327 ir_node *res; 7328 backend_info_t *info; 7329 int arity = 0; 7330 ir_node **in = NULL; 7331 int n_res = 1; 7332 ir_mode *mode = ia32_mode_fpcw; 7333 static const arch_register_req_t **in_reqs = NULL; 7334 7335 /* flags */ 7336 irn_flags_ |= arch_irn_flags_not_scheduled; 7337 7338 /* create node */ 7339 assert(op != NULL); 7340 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 7341 7342 /* init node attributes */ 7343 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 7344 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 7345 7346 info = be_get_info(res); 7347 (void) info; /* avoid potential warning */ 7348 info->out_infos[0].req = &ia32_requirements_fp_cw_fpcw_I; 7349 7350 7351 /* optimize node */ 7352 res = optimize_node(res); 7353 irn_verify_irg(res, irg); 7354 7355 return res; 7356} 7357 7358/** 7359 * construct Prefetch2 node 7360 */ 7361ir_node *new_bd_ia32_Prefetch2(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem) 7362{ 7363 ir_graph *irg = get_irn_irg(block); 7364 ir_op *op = op_ia32_Prefetch2; 7365 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 7366 ir_node *res; 7367 backend_info_t *info; 7368 int arity = 3; 7369 ir_node *in[3]; 7370 int n_res = 1; 7371 ir_mode *mode = mode_T; 7372 static const arch_register_req_t *in_reqs[] = 7373 { 7374 & ia32_requirements_gp_gp, 7375 & ia32_requirements_gp_gp, 7376 & ia32_requirements__none, 7377 }; 7378 7379 /* construct in array */ 7380 in[0] = base; 7381 in[1] = index; 7382 in[2] = mem; 7383 7384 /* create node */ 7385 assert(op != NULL); 7386 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 7387 7388 /* init node attributes */ 7389 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 7390 7391 info = be_get_info(res); 7392 (void) info; /* avoid potential warning */ 7393 info->out_infos[0].req = &ia32_requirements__none; 7394 7395 7396 /* optimize node */ 7397 res = optimize_node(res); 7398 irn_verify_irg(res, irg); 7399 7400 return res; 7401} 7402 7403/** 7404 * construct NoReg_GP node 7405 */ 7406ir_node *new_bd_ia32_NoReg_GP(dbg_info *dbgi, ir_node *block) 7407{ 7408 ir_graph *irg = get_irn_irg(block); 7409 ir_op *op = op_ia32_NoReg_GP; 7410 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 7411 ir_node *res; 7412 backend_info_t *info; 7413 int arity = 0; 7414 ir_node **in = NULL; 7415 int n_res = 1; 7416 ir_mode *mode = mode_Iu; 7417 static const arch_register_req_t **in_reqs = NULL; 7418 7419 /* flags */ 7420 irn_flags_ |= arch_irn_flags_not_scheduled; 7421 7422 /* create node */ 7423 assert(op != NULL); 7424 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 7425 7426 /* init node attributes */ 7427 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 7428 7429 info = be_get_info(res); 7430 (void) info; /* avoid potential warning */ 7431 info->out_infos[0].req = &ia32_requirements_gp_gp_NOREG_I; 7432 7433 7434 /* optimize node */ 7435 res = optimize_node(res); 7436 irn_verify_irg(res, irg); 7437 7438 return res; 7439} 7440 7441/** 7442 * construct Const node 7443 */ 7444ir_node *new_bd_ia32_Const(dbg_info *dbgi, ir_node *block, ir_entity *symconst, int symconst_sign, int no_pic_adjust, long offset) 7445{ 7446 ir_graph *irg = get_irn_irg(block); 7447 ir_op *op = op_ia32_Const; 7448 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 7449 ir_node *res; 7450 backend_info_t *info; 7451 int arity = 0; 7452 ir_node **in = NULL; 7453 int n_res = 1; 7454 ir_mode *mode = mode_Iu; 7455 static const arch_register_req_t **in_reqs = NULL; 7456 7457 /* flags */ 7458 irn_flags_ |= arch_irn_flags_rematerializable; 7459 7460 /* create node */ 7461 assert(op != NULL); 7462 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 7463 7464 /* init node attributes */ 7465 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 7466 init_ia32_immediate_attributes(res, symconst, symconst_sign, no_pic_adjust, offset); 7467 7468 info = be_get_info(res); 7469 (void) info; /* avoid potential warning */ 7470 info->out_infos[0].req = &ia32_requirements_gp_gp; 7471 7472 7473 /* optimize node */ 7474 res = optimize_node(res); 7475 irn_verify_irg(res, irg); 7476 7477 return res; 7478} 7479 7480/** 7481 * construct Minus64Bit node 7482 */ 7483ir_node *new_bd_ia32_Minus64Bit(dbg_info *dbgi, ir_node *block, ir_node *op0, ir_node *op1) 7484{ 7485 ir_graph *irg = get_irn_irg(block); 7486 ir_op *op = op_ia32_Minus64Bit; 7487 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 7488 ir_node *res; 7489 backend_info_t *info; 7490 int arity = 2; 7491 ir_node *in[2]; 7492 int n_res = 2; 7493 ir_mode *mode = mode_T; 7494 static const arch_register_req_t *in_reqs[] = 7495 { 7496 & ia32_requirements_gp_gp, 7497 & ia32_requirements_gp_gp, 7498 }; 7499 7500 /* construct in array */ 7501 in[0] = op0; 7502 in[1] = op1; 7503 7504 /* flags */ 7505 irn_flags_ |= arch_irn_flags_rematerializable; 7506 7507 /* create node */ 7508 assert(op != NULL); 7509 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 7510 7511 /* init node attributes */ 7512 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 7513 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 7514 7515 info = be_get_info(res); 7516 (void) info; /* avoid potential warning */ 7517 info->out_infos[0].req = &ia32_requirements_gp_in_r1; 7518 info->out_infos[1].req = &ia32_requirements_gp_in_r2; 7519 7520 7521 /* optimize node */ 7522 res = optimize_node(res); 7523 irn_verify_irg(res, irg); 7524 7525 return res; 7526} 7527 7528/** 7529 * construct Jmp node 7530 */ 7531ir_node *new_bd_ia32_Jmp(dbg_info *dbgi, ir_node *block) 7532{ 7533 ir_graph *irg = get_irn_irg(block); 7534 ir_op *op = op_ia32_Jmp; 7535 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 7536 ir_node *res; 7537 backend_info_t *info; 7538 int arity = 0; 7539 ir_node **in = NULL; 7540 int n_res = 1; 7541 ir_mode *mode = mode_X; 7542 static const arch_register_req_t **in_reqs = NULL; 7543 7544 /* flags */ 7545 irn_flags_ |= arch_irn_flags_simple_jump; 7546 7547 /* create node */ 7548 assert(op != NULL); 7549 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 7550 7551 /* init node attributes */ 7552 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 7553 7554 info = be_get_info(res); 7555 (void) info; /* avoid potential warning */ 7556 info->out_infos[0].req = &ia32_requirements__none; 7557 7558 7559 /* optimize node */ 7560 res = optimize_node(res); 7561 irn_verify_irg(res, irg); 7562 7563 return res; 7564} 7565 7566/** 7567 * construct FnstCW node 7568 */ 7569ir_node *new_bd_ia32_FnstCW(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *fpcw) 7570{ 7571 ir_graph *irg = get_irn_irg(block); 7572 ir_op *op = op_ia32_FnstCW; 7573 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 7574 ir_node *res; 7575 backend_info_t *info; 7576 int arity = 4; 7577 ir_node *in[4]; 7578 int n_res = 1; 7579 ir_mode *mode = mode_M; 7580 static const arch_register_req_t *in_reqs[] = 7581 { 7582 & ia32_requirements_gp_gp, 7583 & ia32_requirements_gp_gp, 7584 & ia32_requirements__none, 7585 & ia32_requirements_fp_cw_fp_cw, 7586 }; 7587 7588 /* construct in array */ 7589 in[0] = base; 7590 in[1] = index; 7591 in[2] = mem; 7592 in[3] = fpcw; 7593 7594 /* create node */ 7595 assert(op != NULL); 7596 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 7597 7598 /* init node attributes */ 7599 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 7600 7601 info = be_get_info(res); 7602 (void) info; /* avoid potential warning */ 7603 info->out_infos[0].req = &ia32_requirements__none; 7604 7605 7606 /* optimize node */ 7607 res = optimize_node(res); 7608 irn_verify_irg(res, irg); 7609 7610 return res; 7611} 7612 7613/** 7614 * construct Prefetch0 node 7615 */ 7616ir_node *new_bd_ia32_Prefetch0(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem) 7617{ 7618 ir_graph *irg = get_irn_irg(block); 7619 ir_op *op = op_ia32_Prefetch0; 7620 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 7621 ir_node *res; 7622 backend_info_t *info; 7623 int arity = 3; 7624 ir_node *in[3]; 7625 int n_res = 1; 7626 ir_mode *mode = mode_T; 7627 static const arch_register_req_t *in_reqs[] = 7628 { 7629 & ia32_requirements_gp_gp, 7630 & ia32_requirements_gp_gp, 7631 & ia32_requirements__none, 7632 }; 7633 7634 /* construct in array */ 7635 in[0] = base; 7636 in[1] = index; 7637 in[2] = mem; 7638 7639 /* create node */ 7640 assert(op != NULL); 7641 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 7642 7643 /* init node attributes */ 7644 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 7645 7646 info = be_get_info(res); 7647 (void) info; /* avoid potential warning */ 7648 info->out_infos[0].req = &ia32_requirements__none; 7649 7650 7651 /* optimize node */ 7652 res = optimize_node(res); 7653 irn_verify_irg(res, irg); 7654 7655 return res; 7656} 7657 7658/** 7659 * construct OrMem node 7660 */ 7661ir_node *new_bd_ia32_OrMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val) 7662{ 7663 ir_graph *irg = get_irn_irg(block); 7664 ir_op *op = op_ia32_OrMem; 7665 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 7666 ir_node *res; 7667 backend_info_t *info; 7668 int arity = 4; 7669 ir_node *in[4]; 7670 int n_res = 1; 7671 ir_mode *mode = mode_M; 7672 static const arch_register_req_t *in_reqs[] = 7673 { 7674 & ia32_requirements_gp_gp, 7675 & ia32_requirements_gp_gp, 7676 & ia32_requirements__none, 7677 & ia32_requirements_gp_gp, 7678 }; 7679 7680 /* construct in array */ 7681 in[0] = base; 7682 in[1] = index; 7683 in[2] = mem; 7684 in[3] = val; 7685 7686 /* flags */ 7687 irn_flags_ |= arch_irn_flags_rematerializable; 7688 7689 /* create node */ 7690 assert(op != NULL); 7691 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 7692 7693 /* init node attributes */ 7694 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 7695 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 7696 7697 info = be_get_info(res); 7698 (void) info; /* avoid potential warning */ 7699 info->out_infos[0].req = &ia32_requirements__none; 7700 7701 7702 /* optimize node */ 7703 res = optimize_node(res); 7704 irn_verify_irg(res, irg); 7705 7706 return res; 7707} 7708 7709/** 7710 * construct fldlg2 node 7711 */ 7712ir_node *new_bd_ia32_fldlg2(dbg_info *dbgi, ir_node *block) 7713{ 7714 ir_graph *irg = get_irn_irg(block); 7715 ir_op *op = op_ia32_fldlg2; 7716 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 7717 ir_node *res; 7718 backend_info_t *info; 7719 int arity = 0; 7720 ir_node **in = NULL; 7721 int n_res = 1; 7722 ir_mode *mode = ia32_mode_E; 7723 static const arch_register_req_t **in_reqs = NULL; 7724 7725 /* flags */ 7726 irn_flags_ |= arch_irn_flags_rematerializable; 7727 7728 /* create node */ 7729 assert(op != NULL); 7730 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 7731 7732 /* init node attributes */ 7733 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 7734 init_ia32_x87_attributes(res); 7735 7736 info = be_get_info(res); 7737 (void) info; /* avoid potential warning */ 7738 info->out_infos[0].req = &ia32_requirements_fp_fp; 7739 7740 7741 /* optimize node */ 7742 res = optimize_node(res); 7743 irn_verify_irg(res, irg); 7744 7745 return res; 7746} 7747 7748/** 7749 * construct fld1 node 7750 */ 7751ir_node *new_bd_ia32_fld1(dbg_info *dbgi, ir_node *block) 7752{ 7753 ir_graph *irg = get_irn_irg(block); 7754 ir_op *op = op_ia32_fld1; 7755 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 7756 ir_node *res; 7757 backend_info_t *info; 7758 int arity = 0; 7759 ir_node **in = NULL; 7760 int n_res = 1; 7761 ir_mode *mode = ia32_mode_E; 7762 static const arch_register_req_t **in_reqs = NULL; 7763 7764 /* flags */ 7765 irn_flags_ |= arch_irn_flags_rematerializable; 7766 7767 /* create node */ 7768 assert(op != NULL); 7769 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 7770 7771 /* init node attributes */ 7772 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 7773 init_ia32_x87_attributes(res); 7774 7775 info = be_get_info(res); 7776 (void) info; /* avoid potential warning */ 7777 info->out_infos[0].req = &ia32_requirements_fp_fp; 7778 7779 7780 /* optimize node */ 7781 res = optimize_node(res); 7782 irn_verify_irg(res, irg); 7783 7784 return res; 7785} 7786 7787/** 7788 * construct Conv_FP2I node 7789 */ 7790ir_node *new_bd_ia32_Conv_FP2I(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val) 7791{ 7792 ir_graph *irg = get_irn_irg(block); 7793 ir_op *op = op_ia32_Conv_FP2I; 7794 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 7795 ir_node *res; 7796 backend_info_t *info; 7797 int arity = 4; 7798 ir_node *in[4]; 7799 int n_res = 2; 7800 ir_mode *mode = mode_Iu; 7801 static const arch_register_req_t *in_reqs[] = 7802 { 7803 & ia32_requirements_gp_gp, 7804 & ia32_requirements_gp_gp, 7805 & ia32_requirements__none, 7806 & ia32_requirements_xmm_xmm, 7807 }; 7808 7809 /* construct in array */ 7810 in[0] = base; 7811 in[1] = index; 7812 in[2] = mem; 7813 in[3] = val; 7814 7815 /* create node */ 7816 assert(op != NULL); 7817 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 7818 7819 /* init node attributes */ 7820 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 7821 set_ia32_am_support(res, ia32_am_unary); 7822 info = be_get_info(res); 7823 (void) info; /* avoid potential warning */ 7824 info->out_infos[0].req = &ia32_requirements_gp_gp; 7825 info->out_infos[1].req = &ia32_requirements__none; 7826 7827 7828 /* optimize node */ 7829 res = optimize_node(res); 7830 irn_verify_irg(res, irg); 7831 7832 return res; 7833} 7834 7835/** 7836 * construct Popcnt node 7837 */ 7838ir_node *new_bd_ia32_Popcnt(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *operand) 7839{ 7840 ir_graph *irg = get_irn_irg(block); 7841 ir_op *op = op_ia32_Popcnt; 7842 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 7843 ir_node *res; 7844 backend_info_t *info; 7845 int arity = 4; 7846 ir_node *in[4]; 7847 int n_res = 3; 7848 ir_mode *mode = mode_Iu; 7849 static const arch_register_req_t *in_reqs[] = 7850 { 7851 & ia32_requirements_gp_gp, 7852 & ia32_requirements_gp_gp, 7853 & ia32_requirements__none, 7854 & ia32_requirements_gp_gp, 7855 }; 7856 7857 /* construct in array */ 7858 in[0] = base; 7859 in[1] = index; 7860 in[2] = mem; 7861 in[3] = operand; 7862 7863 /* flags */ 7864 irn_flags_ |= arch_irn_flags_rematerializable; 7865 7866 /* create node */ 7867 assert(op != NULL); 7868 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 7869 7870 /* init node attributes */ 7871 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 7872 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 7873 set_ia32_am_support(res, ia32_am_binary); 7874 info = be_get_info(res); 7875 (void) info; /* avoid potential warning */ 7876 info->out_infos[0].req = &ia32_requirements_gp_gp; 7877 info->out_infos[1].req = &ia32_requirements_flags_flags; 7878 info->out_infos[2].req = &ia32_requirements__none; 7879 7880 7881 /* optimize node */ 7882 res = optimize_node(res); 7883 irn_verify_irg(res, irg); 7884 7885 return res; 7886} 7887 7888/** 7889 * construct Ror node 7890 */ 7891ir_node *new_bd_ia32_Ror(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count) 7892{ 7893 ir_graph *irg = get_irn_irg(block); 7894 ir_op *op = op_ia32_Ror; 7895 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 7896 ir_node *res; 7897 backend_info_t *info; 7898 int arity = 2; 7899 ir_node *in[2]; 7900 int n_res = 2; 7901 ir_mode *mode = mode_Iu; 7902 static const arch_register_req_t *in_reqs[] = 7903 { 7904 & ia32_requirements_gp_gp, 7905 & ia32_requirements_gp_ecx, 7906 }; 7907 7908 /* construct in array */ 7909 in[0] = val; 7910 in[1] = count; 7911 7912 /* flags */ 7913 irn_flags_ |= arch_irn_flags_rematerializable; 7914 7915 /* create node */ 7916 assert(op != NULL); 7917 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 7918 7919 /* init node attributes */ 7920 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 7921 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 7922 7923 info = be_get_info(res); 7924 (void) info; /* avoid potential warning */ 7925 info->out_infos[0].req = &ia32_requirements_gp_in_r1_not_in_r2; 7926 info->out_infos[1].req = &ia32_requirements_flags_flags; 7927 7928 7929 /* optimize node */ 7930 res = optimize_node(res); 7931 irn_verify_irg(res, irg); 7932 7933 return res; 7934} 7935 7936/** 7937 * construct Shl node 7938 */ 7939ir_node *new_bd_ia32_Shl(dbg_info *dbgi, ir_node *block, ir_node *val, ir_node *count) 7940{ 7941 ir_graph *irg = get_irn_irg(block); 7942 ir_op *op = op_ia32_Shl; 7943 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 7944 ir_node *res; 7945 backend_info_t *info; 7946 int arity = 2; 7947 ir_node *in[2]; 7948 int n_res = 2; 7949 ir_mode *mode = mode_Iu; 7950 static const arch_register_req_t *in_reqs[] = 7951 { 7952 & ia32_requirements_gp_gp, 7953 & ia32_requirements_gp_ecx, 7954 }; 7955 7956 /* construct in array */ 7957 in[0] = val; 7958 in[1] = count; 7959 7960 /* flags */ 7961 irn_flags_ |= arch_irn_flags_rematerializable; 7962 7963 /* create node */ 7964 assert(op != NULL); 7965 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 7966 7967 /* init node attributes */ 7968 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 7969 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 7970 7971 info = be_get_info(res); 7972 (void) info; /* avoid potential warning */ 7973 info->out_infos[0].req = &ia32_requirements_gp_in_r1_not_in_r2; 7974 info->out_infos[1].req = &ia32_requirements_flags_flags; 7975 7976 7977 /* optimize node */ 7978 res = optimize_node(res); 7979 irn_verify_irg(res, irg); 7980 7981 return res; 7982} 7983 7984/** 7985 * construct AndMem8Bit node 7986 */ 7987ir_node *new_bd_ia32_AndMem8Bit(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val) 7988{ 7989 ir_graph *irg = get_irn_irg(block); 7990 ir_op *op = op_ia32_AndMem8Bit; 7991 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 7992 ir_node *res; 7993 backend_info_t *info; 7994 int arity = 4; 7995 ir_node *in[4]; 7996 int n_res = 1; 7997 ir_mode *mode = mode_M; 7998 static const arch_register_req_t *in_reqs[] = 7999 { 8000 & ia32_requirements_gp_gp, 8001 & ia32_requirements_gp_gp, 8002 & ia32_requirements__none, 8003 & ia32_requirements_gp_eax_ebx_ecx_edx, 8004 }; 8005 8006 /* construct in array */ 8007 in[0] = base; 8008 in[1] = index; 8009 in[2] = mem; 8010 in[3] = val; 8011 8012 /* flags */ 8013 irn_flags_ |= arch_irn_flags_rematerializable; 8014 8015 /* create node */ 8016 assert(op != NULL); 8017 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 8018 8019 /* init node attributes */ 8020 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 8021 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 8022 8023 info = be_get_info(res); 8024 (void) info; /* avoid potential warning */ 8025 info->out_infos[0].req = &ia32_requirements__none; 8026 8027 8028 /* optimize node */ 8029 res = optimize_node(res); 8030 irn_verify_irg(res, irg); 8031 8032 return res; 8033} 8034 8035/** 8036 * construct Add node 8037 */ 8038ir_node *new_bd_ia32_Add(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right) 8039{ 8040 ir_graph *irg = get_irn_irg(block); 8041 ir_op *op = op_ia32_Add; 8042 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 8043 ir_node *res; 8044 backend_info_t *info; 8045 int arity = 5; 8046 ir_node *in[5]; 8047 int n_res = 3; 8048 ir_mode *mode = mode_Iu; 8049 static const arch_register_req_t *in_reqs[] = 8050 { 8051 & ia32_requirements_gp_gp, 8052 & ia32_requirements_gp_gp, 8053 & ia32_requirements__none, 8054 & ia32_requirements_gp_gp, 8055 & ia32_requirements_gp_gp, 8056 }; 8057 8058 /* construct in array */ 8059 in[0] = base; 8060 in[1] = index; 8061 in[2] = mem; 8062 in[3] = left; 8063 in[4] = right; 8064 8065 /* flags */ 8066 irn_flags_ |= arch_irn_flags_rematerializable; 8067 8068 /* create node */ 8069 assert(op != NULL); 8070 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 8071 8072 /* init node attributes */ 8073 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 8074 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 8075 set_ia32_am_support(res, ia32_am_binary); 8076 info = be_get_info(res); 8077 (void) info; /* avoid potential warning */ 8078 info->out_infos[0].req = &ia32_requirements_gp_in_r4_in_r5; 8079 info->out_infos[1].req = &ia32_requirements_flags_flags; 8080 info->out_infos[2].req = &ia32_requirements__none; 8081 8082 8083 /* optimize node */ 8084 res = optimize_node(res); 8085 irn_verify_irg(res, irg); 8086 8087 return res; 8088} 8089 8090/** 8091 * construct SubSP node 8092 */ 8093ir_node *new_bd_ia32_SubSP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *stack, ir_node *size) 8094{ 8095 ir_graph *irg = get_irn_irg(block); 8096 ir_op *op = op_ia32_SubSP; 8097 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 8098 ir_node *res; 8099 backend_info_t *info; 8100 int arity = 5; 8101 ir_node *in[5]; 8102 int n_res = 3; 8103 ir_mode *mode = mode_T; 8104 static const arch_register_req_t *in_reqs[] = 8105 { 8106 & ia32_requirements_gp_gp, 8107 & ia32_requirements_gp_gp, 8108 & ia32_requirements__none, 8109 & ia32_requirements_gp_esp, 8110 & ia32_requirements_gp_gp, 8111 }; 8112 8113 /* construct in array */ 8114 in[0] = base; 8115 in[1] = index; 8116 in[2] = mem; 8117 in[3] = stack; 8118 in[4] = size; 8119 8120 /* create node */ 8121 assert(op != NULL); 8122 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 8123 8124 /* init node attributes */ 8125 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 8126 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 8127 set_ia32_am_support(res, ia32_am_binary); 8128 info = be_get_info(res); 8129 (void) info; /* avoid potential warning */ 8130 info->out_infos[0].req = &ia32_requirements_gp_esp_I_S; 8131 info->out_infos[1].req = &ia32_requirements_gp_gp; 8132 info->out_infos[2].req = &ia32_requirements__none; 8133 8134 8135 /* optimize node */ 8136 res = optimize_node(res); 8137 irn_verify_irg(res, irg); 8138 8139 return res; 8140} 8141 8142/** 8143 * construct PrefetchW node 8144 */ 8145ir_node *new_bd_ia32_PrefetchW(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem) 8146{ 8147 ir_graph *irg = get_irn_irg(block); 8148 ir_op *op = op_ia32_PrefetchW; 8149 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 8150 ir_node *res; 8151 backend_info_t *info; 8152 int arity = 3; 8153 ir_node *in[3]; 8154 int n_res = 1; 8155 ir_mode *mode = mode_T; 8156 static const arch_register_req_t *in_reqs[] = 8157 { 8158 & ia32_requirements_gp_gp, 8159 & ia32_requirements_gp_gp, 8160 & ia32_requirements__none, 8161 }; 8162 8163 /* construct in array */ 8164 in[0] = base; 8165 in[1] = index; 8166 in[2] = mem; 8167 8168 /* create node */ 8169 assert(op != NULL); 8170 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 8171 8172 /* init node attributes */ 8173 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 8174 8175 info = be_get_info(res); 8176 (void) info; /* avoid potential warning */ 8177 info->out_infos[0].req = &ia32_requirements__none; 8178 8179 8180 /* optimize node */ 8181 res = optimize_node(res); 8182 irn_verify_irg(res, irg); 8183 8184 return res; 8185} 8186 8187/** 8188 * construct Conv_I2I node 8189 */ 8190ir_node *new_bd_ia32_Conv_I2I(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val, ir_mode *smaller_mode) 8191{ 8192 ir_graph *irg = get_irn_irg(block); 8193 ir_op *op = op_ia32_Conv_I2I; 8194 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 8195 ir_node *res; 8196 backend_info_t *info; 8197 int arity = 4; 8198 ir_node *in[4]; 8199 int n_res = 5; 8200 ir_mode *mode = mode_Iu; 8201 static const arch_register_req_t *in_reqs[] = 8202 { 8203 & ia32_requirements_gp_gp, 8204 & ia32_requirements_gp_gp, 8205 & ia32_requirements__none, 8206 & ia32_requirements_gp_gp, 8207 }; 8208 ia32_attr_t *attr; 8209 8210 /* construct in array */ 8211 in[0] = base; 8212 in[1] = index; 8213 in[2] = mem; 8214 in[3] = val; 8215 8216 /* create node */ 8217 assert(op != NULL); 8218 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 8219 8220 /* init node attributes */ 8221 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 8222 set_ia32_am_support(res, ia32_am_unary); 8223 info = be_get_info(res); 8224 (void) info; /* avoid potential warning */ 8225 info->out_infos[0].req = &ia32_requirements_gp_gp; 8226 info->out_infos[1].req = &ia32_requirements__none; 8227 info->out_infos[2].req = &ia32_requirements__none; 8228 info->out_infos[3].req = &ia32_requirements__none; 8229 info->out_infos[4].req = &ia32_requirements__none; 8230 8231 8232 attr = (ia32_attr_t*)get_irn_generic_attr(res); 8233 (void) attr; /* avoid potential warning */ 8234 attr->ls_mode = smaller_mode; 8235 /* optimize node */ 8236 res = optimize_node(res); 8237 irn_verify_irg(res, irg); 8238 8239 return res; 8240} 8241 8242/** 8243 * construct fxch node 8244 */ 8245ir_node *new_bd_ia32_fxch(dbg_info *dbgi, ir_node *block) 8246{ 8247 ir_graph *irg = get_irn_irg(block); 8248 ir_op *op = op_ia32_fxch; 8249 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 8250 ir_node *res; 8251 backend_info_t *info; 8252 int arity = 0; 8253 ir_node **in = NULL; 8254 int n_res = 1; 8255 ir_mode *mode = mode_ANY; 8256 static const arch_register_req_t **in_reqs = NULL; 8257 8258 /* create node */ 8259 assert(op != NULL); 8260 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 8261 8262 /* init node attributes */ 8263 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 8264 init_ia32_x87_attributes(res); 8265 8266 info = be_get_info(res); 8267 (void) info; /* avoid potential warning */ 8268 info->out_infos[0].req = &ia32_requirements__none; 8269 8270 8271 /* optimize node */ 8272 res = optimize_node(res); 8273 irn_verify_irg(res, irg); 8274 8275 return res; 8276} 8277 8278/** 8279 * construct fchs node 8280 */ 8281ir_node *new_bd_ia32_fchs(dbg_info *dbgi, ir_node *block, ir_node *value) 8282{ 8283 ir_graph *irg = get_irn_irg(block); 8284 ir_op *op = op_ia32_fchs; 8285 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 8286 ir_node *res; 8287 backend_info_t *info; 8288 int arity = 1; 8289 ir_node *in[1]; 8290 int n_res = 1; 8291 ir_mode *mode = ia32_mode_E; 8292 static const arch_register_req_t *in_reqs[] = 8293 { 8294 & ia32_requirements_fp_fp, 8295 }; 8296 8297 /* construct in array */ 8298 in[0] = value; 8299 8300 /* flags */ 8301 irn_flags_ |= arch_irn_flags_rematerializable; 8302 8303 /* create node */ 8304 assert(op != NULL); 8305 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 8306 8307 /* init node attributes */ 8308 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 8309 init_ia32_x87_attributes(res); 8310 8311 info = be_get_info(res); 8312 (void) info; /* avoid potential warning */ 8313 info->out_infos[0].req = &ia32_requirements_fp_fp; 8314 8315 8316 /* optimize node */ 8317 res = optimize_node(res); 8318 irn_verify_irg(res, irg); 8319 8320 return res; 8321} 8322 8323/** 8324 * construct ShrD node 8325 */ 8326ir_node *new_bd_ia32_ShrD(dbg_info *dbgi, ir_node *block, ir_node *val_high, ir_node *val_low, ir_node *count) 8327{ 8328 ir_graph *irg = get_irn_irg(block); 8329 ir_op *op = op_ia32_ShrD; 8330 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 8331 ir_node *res; 8332 backend_info_t *info; 8333 int arity = 3; 8334 ir_node *in[3]; 8335 int n_res = 2; 8336 ir_mode *mode = mode_Iu; 8337 static const arch_register_req_t *in_reqs[] = 8338 { 8339 & ia32_requirements_gp_gp, 8340 & ia32_requirements_gp_gp, 8341 & ia32_requirements_gp_ecx, 8342 }; 8343 8344 /* construct in array */ 8345 in[0] = val_high; 8346 in[1] = val_low; 8347 in[2] = count; 8348 8349 /* flags */ 8350 irn_flags_ |= arch_irn_flags_rematerializable; 8351 8352 /* create node */ 8353 assert(op != NULL); 8354 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 8355 8356 /* init node attributes */ 8357 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 8358 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 8359 8360 info = be_get_info(res); 8361 (void) info; /* avoid potential warning */ 8362 info->out_infos[0].req = &ia32_requirements_gp_in_r1_not_in_r2_not_in_r3; 8363 info->out_infos[1].req = &ia32_requirements_flags_flags; 8364 8365 8366 /* optimize node */ 8367 res = optimize_node(res); 8368 irn_verify_irg(res, irg); 8369 8370 return res; 8371} 8372 8373/** 8374 * construct Unknown node 8375 */ 8376ir_node *new_bd_ia32_Unknown(dbg_info *dbgi, ir_node *block) 8377{ 8378 ir_graph *irg = get_irn_irg(block); 8379 ir_op *op = op_ia32_Unknown; 8380 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 8381 ir_node *res; 8382 backend_info_t *info; 8383 int arity = 0; 8384 ir_node **in = NULL; 8385 int n_res = 1; 8386 ir_mode *mode = mode_Iu; 8387 static const arch_register_req_t **in_reqs = NULL; 8388 8389 /* flags */ 8390 irn_flags_ |= arch_irn_flags_rematerializable; 8391 8392 /* create node */ 8393 assert(op != NULL); 8394 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 8395 8396 /* init node attributes */ 8397 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 8398 8399 info = be_get_info(res); 8400 (void) info; /* avoid potential warning */ 8401 info->out_infos[0].req = &ia32_requirements_gp_gp; 8402 8403 8404 /* optimize node */ 8405 res = optimize_node(res); 8406 irn_verify_irg(res, irg); 8407 8408 return res; 8409} 8410 8411/** 8412 * construct UD2 node 8413 */ 8414ir_node *new_bd_ia32_UD2(dbg_info *dbgi, ir_node *block, ir_node *mem) 8415{ 8416 ir_graph *irg = get_irn_irg(block); 8417 ir_op *op = op_ia32_UD2; 8418 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 8419 ir_node *res; 8420 backend_info_t *info; 8421 int arity = 1; 8422 ir_node *in[1]; 8423 int n_res = 1; 8424 ir_mode *mode = mode_M; 8425 static const arch_register_req_t *in_reqs[] = 8426 { 8427 & ia32_requirements__none, 8428 }; 8429 8430 /* construct in array */ 8431 in[0] = mem; 8432 8433 /* create node */ 8434 assert(op != NULL); 8435 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 8436 8437 /* init node attributes */ 8438 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 8439 8440 info = be_get_info(res); 8441 (void) info; /* avoid potential warning */ 8442 info->out_infos[0].req = &ia32_requirements__none; 8443 8444 8445 /* optimize node */ 8446 res = optimize_node(res); 8447 irn_verify_irg(res, irg); 8448 8449 return res; 8450} 8451 8452/** 8453 * construct Cwtl node 8454 */ 8455ir_node *new_bd_ia32_Cwtl(dbg_info *dbgi, ir_node *block, ir_node *val) 8456{ 8457 ir_graph *irg = get_irn_irg(block); 8458 ir_op *op = op_ia32_Cwtl; 8459 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 8460 ir_node *res; 8461 backend_info_t *info; 8462 int arity = 1; 8463 ir_node *in[1]; 8464 int n_res = 1; 8465 ir_mode *mode = mode_Iu; 8466 static const arch_register_req_t *in_reqs[] = 8467 { 8468 & ia32_requirements_gp_eax, 8469 }; 8470 8471 /* construct in array */ 8472 in[0] = val; 8473 8474 /* create node */ 8475 assert(op != NULL); 8476 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 8477 8478 /* init node attributes */ 8479 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 8480 8481 info = be_get_info(res); 8482 (void) info; /* avoid potential warning */ 8483 info->out_infos[0].req = &ia32_requirements_gp_eax; 8484 8485 8486 /* optimize node */ 8487 res = optimize_node(res); 8488 irn_verify_irg(res, irg); 8489 8490 return res; 8491} 8492 8493/** 8494 * construct fabs node 8495 */ 8496ir_node *new_bd_ia32_fabs(dbg_info *dbgi, ir_node *block, ir_node *value) 8497{ 8498 ir_graph *irg = get_irn_irg(block); 8499 ir_op *op = op_ia32_fabs; 8500 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 8501 ir_node *res; 8502 backend_info_t *info; 8503 int arity = 1; 8504 ir_node *in[1]; 8505 int n_res = 1; 8506 ir_mode *mode = ia32_mode_E; 8507 static const arch_register_req_t *in_reqs[] = 8508 { 8509 & ia32_requirements_fp_fp, 8510 }; 8511 8512 /* construct in array */ 8513 in[0] = value; 8514 8515 /* flags */ 8516 irn_flags_ |= arch_irn_flags_rematerializable; 8517 8518 /* create node */ 8519 assert(op != NULL); 8520 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 8521 8522 /* init node attributes */ 8523 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 8524 init_ia32_x87_attributes(res); 8525 8526 info = be_get_info(res); 8527 (void) info; /* avoid potential warning */ 8528 info->out_infos[0].req = &ia32_requirements_fp_fp; 8529 8530 8531 /* optimize node */ 8532 res = optimize_node(res); 8533 irn_verify_irg(res, irg); 8534 8535 return res; 8536} 8537 8538/** 8539 * construct fldpi node 8540 */ 8541ir_node *new_bd_ia32_fldpi(dbg_info *dbgi, ir_node *block) 8542{ 8543 ir_graph *irg = get_irn_irg(block); 8544 ir_op *op = op_ia32_fldpi; 8545 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 8546 ir_node *res; 8547 backend_info_t *info; 8548 int arity = 0; 8549 ir_node **in = NULL; 8550 int n_res = 1; 8551 ir_mode *mode = ia32_mode_E; 8552 static const arch_register_req_t **in_reqs = NULL; 8553 8554 /* flags */ 8555 irn_flags_ |= arch_irn_flags_rematerializable; 8556 8557 /* create node */ 8558 assert(op != NULL); 8559 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 8560 8561 /* init node attributes */ 8562 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 8563 init_ia32_x87_attributes(res); 8564 8565 info = be_get_info(res); 8566 (void) info; /* avoid potential warning */ 8567 info->out_infos[0].req = &ia32_requirements_fp_fp; 8568 8569 8570 /* optimize node */ 8571 res = optimize_node(res); 8572 irn_verify_irg(res, irg); 8573 8574 return res; 8575} 8576 8577/** 8578 * construct Leave node 8579 */ 8580ir_node *new_bd_ia32_Leave(dbg_info *dbgi, ir_node *block, ir_node *op0) 8581{ 8582 ir_graph *irg = get_irn_irg(block); 8583 ir_op *op = op_ia32_Leave; 8584 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 8585 ir_node *res; 8586 backend_info_t *info; 8587 int arity = 1; 8588 ir_node *in[1]; 8589 int n_res = 2; 8590 ir_mode *mode = mode_T; 8591 static const arch_register_req_t *in_reqs[] = 8592 { 8593 & ia32_requirements_gp_ebp, 8594 }; 8595 8596 /* construct in array */ 8597 in[0] = op0; 8598 8599 /* create node */ 8600 assert(op != NULL); 8601 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 8602 8603 /* init node attributes */ 8604 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 8605 8606 info = be_get_info(res); 8607 (void) info; /* avoid potential warning */ 8608 info->out_infos[0].req = &ia32_requirements_gp_ebp_I; 8609 info->out_infos[1].req = &ia32_requirements_gp_esp_I_S; 8610 8611 8612 /* optimize node */ 8613 res = optimize_node(res); 8614 irn_verify_irg(res, irg); 8615 8616 return res; 8617} 8618 8619/** 8620 * construct Neg node 8621 */ 8622ir_node *new_bd_ia32_Neg(dbg_info *dbgi, ir_node *block, ir_node *val) 8623{ 8624 ir_graph *irg = get_irn_irg(block); 8625 ir_op *op = op_ia32_Neg; 8626 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 8627 ir_node *res; 8628 backend_info_t *info; 8629 int arity = 1; 8630 ir_node *in[1]; 8631 int n_res = 2; 8632 ir_mode *mode = mode_Iu; 8633 static const arch_register_req_t *in_reqs[] = 8634 { 8635 & ia32_requirements_gp_gp, 8636 }; 8637 8638 /* construct in array */ 8639 in[0] = val; 8640 8641 /* flags */ 8642 irn_flags_ |= arch_irn_flags_rematerializable; 8643 8644 /* create node */ 8645 assert(op != NULL); 8646 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 8647 8648 /* init node attributes */ 8649 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 8650 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 8651 8652 info = be_get_info(res); 8653 (void) info; /* avoid potential warning */ 8654 info->out_infos[0].req = &ia32_requirements_gp_in_r1; 8655 info->out_infos[1].req = &ia32_requirements_flags_flags; 8656 8657 8658 /* optimize node */ 8659 res = optimize_node(res); 8660 irn_verify_irg(res, irg); 8661 8662 return res; 8663} 8664 8665/** 8666 * construct IMul1OP node 8667 */ 8668ir_node *new_bd_ia32_IMul1OP(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right) 8669{ 8670 ir_graph *irg = get_irn_irg(block); 8671 ir_op *op = op_ia32_IMul1OP; 8672 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 8673 ir_node *res; 8674 backend_info_t *info; 8675 int arity = 5; 8676 ir_node *in[5]; 8677 int n_res = 4; 8678 ir_mode *mode = mode_T; 8679 static const arch_register_req_t *in_reqs[] = 8680 { 8681 & ia32_requirements_gp_gp, 8682 & ia32_requirements_gp_gp, 8683 & ia32_requirements__none, 8684 & ia32_requirements_gp_eax, 8685 & ia32_requirements_gp_gp, 8686 }; 8687 8688 /* construct in array */ 8689 in[0] = base; 8690 in[1] = index; 8691 in[2] = mem; 8692 in[3] = left; 8693 in[4] = right; 8694 8695 /* flags */ 8696 irn_flags_ |= arch_irn_flags_rematerializable; 8697 8698 /* create node */ 8699 assert(op != NULL); 8700 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 8701 8702 /* init node attributes */ 8703 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 8704 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 8705 set_ia32_am_support(res, ia32_am_binary); 8706 info = be_get_info(res); 8707 (void) info; /* avoid potential warning */ 8708 info->out_infos[0].req = &ia32_requirements_gp_eax; 8709 info->out_infos[1].req = &ia32_requirements_flags_flags; 8710 info->out_infos[2].req = &ia32_requirements__none; 8711 info->out_infos[3].req = &ia32_requirements_gp_edx; 8712 8713 8714 /* optimize node */ 8715 res = optimize_node(res); 8716 irn_verify_irg(res, irg); 8717 8718 return res; 8719} 8720 8721/** 8722 * construct PopMem node 8723 */ 8724ir_node *new_bd_ia32_PopMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *stack) 8725{ 8726 ir_graph *irg = get_irn_irg(block); 8727 ir_op *op = op_ia32_PopMem; 8728 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 8729 ir_node *res; 8730 backend_info_t *info; 8731 int arity = 4; 8732 ir_node *in[4]; 8733 int n_res = 4; 8734 ir_mode *mode = mode_T; 8735 static const arch_register_req_t *in_reqs[] = 8736 { 8737 & ia32_requirements_gp_gp, 8738 & ia32_requirements_gp_gp, 8739 & ia32_requirements__none, 8740 & ia32_requirements_gp_esp, 8741 }; 8742 8743 /* construct in array */ 8744 in[0] = base; 8745 in[1] = index; 8746 in[2] = mem; 8747 in[3] = stack; 8748 8749 /* create node */ 8750 assert(op != NULL); 8751 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 8752 8753 /* init node attributes */ 8754 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 8755 8756 info = be_get_info(res); 8757 (void) info; /* avoid potential warning */ 8758 info->out_infos[0].req = &ia32_requirements__none; 8759 info->out_infos[1].req = &ia32_requirements__none; 8760 info->out_infos[2].req = &ia32_requirements__none; 8761 info->out_infos[3].req = &ia32_requirements_gp_esp_I_S; 8762 8763 8764 /* optimize node */ 8765 res = optimize_node(res); 8766 irn_verify_irg(res, irg); 8767 8768 return res; 8769} 8770 8771/** 8772 * construct fld node 8773 */ 8774ir_node *new_bd_ia32_fld(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_mode *load_mode) 8775{ 8776 ir_graph *irg = get_irn_irg(block); 8777 ir_op *op = op_ia32_fld; 8778 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 8779 ir_node *res; 8780 backend_info_t *info; 8781 int arity = 3; 8782 ir_node *in[3]; 8783 int n_res = 5; 8784 ir_mode *mode = mode_T; 8785 static const arch_register_req_t *in_reqs[] = 8786 { 8787 & ia32_requirements_gp_gp, 8788 & ia32_requirements_gp_gp, 8789 & ia32_requirements__none, 8790 }; 8791 ia32_x87_attr_t *attr; 8792 8793 /* construct in array */ 8794 in[0] = base; 8795 in[1] = index; 8796 in[2] = mem; 8797 8798 /* flags */ 8799 irn_flags_ |= arch_irn_flags_rematerializable; 8800 8801 /* create node */ 8802 assert(op != NULL); 8803 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 8804 8805 /* init node attributes */ 8806 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 8807 init_ia32_x87_attributes(res); 8808 8809 info = be_get_info(res); 8810 (void) info; /* avoid potential warning */ 8811 info->out_infos[0].req = &ia32_requirements_fp_fp; 8812 info->out_infos[1].req = &ia32_requirements__none; 8813 info->out_infos[2].req = &ia32_requirements__none; 8814 info->out_infos[3].req = &ia32_requirements__none; 8815 info->out_infos[4].req = &ia32_requirements__none; 8816 8817 8818 attr = (ia32_x87_attr_t*)get_irn_generic_attr(res); 8819 (void) attr; /* avoid potential warning */ 8820 attr->attr.ls_mode = load_mode; 8821 /* optimize node */ 8822 res = optimize_node(res); 8823 irn_verify_irg(res, irg); 8824 8825 return res; 8826} 8827 8828/** 8829 * construct Dec node 8830 */ 8831ir_node *new_bd_ia32_Dec(dbg_info *dbgi, ir_node *block, ir_node *val) 8832{ 8833 ir_graph *irg = get_irn_irg(block); 8834 ir_op *op = op_ia32_Dec; 8835 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 8836 ir_node *res; 8837 backend_info_t *info; 8838 int arity = 1; 8839 ir_node *in[1]; 8840 int n_res = 2; 8841 ir_mode *mode = mode_Iu; 8842 static const arch_register_req_t *in_reqs[] = 8843 { 8844 & ia32_requirements_gp_gp, 8845 }; 8846 8847 /* construct in array */ 8848 in[0] = val; 8849 8850 /* flags */ 8851 irn_flags_ |= arch_irn_flags_rematerializable; 8852 8853 /* create node */ 8854 assert(op != NULL); 8855 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 8856 8857 /* init node attributes */ 8858 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 8859 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 8860 8861 info = be_get_info(res); 8862 (void) info; /* avoid potential warning */ 8863 info->out_infos[0].req = &ia32_requirements_gp_in_r1; 8864 info->out_infos[1].req = &ia32_requirements_flags_flags; 8865 8866 8867 /* optimize node */ 8868 res = optimize_node(res); 8869 irn_verify_irg(res, irg); 8870 8871 return res; 8872} 8873 8874/** 8875 * construct Pop node 8876 */ 8877ir_node *new_bd_ia32_Pop(dbg_info *dbgi, ir_node *block, ir_node *mem, ir_node *stack) 8878{ 8879 ir_graph *irg = get_irn_irg(block); 8880 ir_op *op = op_ia32_Pop; 8881 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 8882 ir_node *res; 8883 backend_info_t *info; 8884 int arity = 2; 8885 ir_node *in[2]; 8886 int n_res = 4; 8887 ir_mode *mode = mode_T; 8888 static const arch_register_req_t *in_reqs[] = 8889 { 8890 & ia32_requirements__none, 8891 & ia32_requirements_gp_esp, 8892 }; 8893 8894 /* construct in array */ 8895 in[0] = mem; 8896 in[1] = stack; 8897 8898 /* create node */ 8899 assert(op != NULL); 8900 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 8901 8902 /* init node attributes */ 8903 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 8904 8905 info = be_get_info(res); 8906 (void) info; /* avoid potential warning */ 8907 info->out_infos[0].req = &ia32_requirements_gp_gp; 8908 info->out_infos[1].req = &ia32_requirements__none; 8909 info->out_infos[2].req = &ia32_requirements__none; 8910 info->out_infos[3].req = &ia32_requirements_gp_esp_I_S; 8911 8912 8913 /* optimize node */ 8914 res = optimize_node(res); 8915 irn_verify_irg(res, irg); 8916 8917 return res; 8918} 8919 8920/** 8921 * construct CopyEbpEsp node 8922 */ 8923ir_node *new_bd_ia32_CopyEbpEsp(dbg_info *dbgi, ir_node *block, ir_node *ebp) 8924{ 8925 ir_graph *irg = get_irn_irg(block); 8926 ir_op *op = op_ia32_CopyEbpEsp; 8927 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 8928 ir_node *res; 8929 backend_info_t *info; 8930 int arity = 1; 8931 ir_node *in[1]; 8932 int n_res = 1; 8933 ir_mode *mode = mode_Iu; 8934 static const arch_register_req_t *in_reqs[] = 8935 { 8936 & ia32_requirements_gp_ebp, 8937 }; 8938 8939 /* construct in array */ 8940 in[0] = ebp; 8941 8942 /* create node */ 8943 assert(op != NULL); 8944 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 8945 8946 /* init node attributes */ 8947 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 8948 8949 info = be_get_info(res); 8950 (void) info; /* avoid potential warning */ 8951 info->out_infos[0].req = &ia32_requirements_gp_esp_I_S; 8952 8953 8954 /* optimize node */ 8955 res = optimize_node(res); 8956 irn_verify_irg(res, irg); 8957 8958 return res; 8959} 8960 8961/** 8962 * construct Not node 8963 */ 8964ir_node *new_bd_ia32_Not(dbg_info *dbgi, ir_node *block, ir_node *val) 8965{ 8966 ir_graph *irg = get_irn_irg(block); 8967 ir_op *op = op_ia32_Not; 8968 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 8969 ir_node *res; 8970 backend_info_t *info; 8971 int arity = 1; 8972 ir_node *in[1]; 8973 int n_res = 1; 8974 ir_mode *mode = mode_Iu; 8975 static const arch_register_req_t *in_reqs[] = 8976 { 8977 & ia32_requirements_gp_gp, 8978 }; 8979 8980 /* construct in array */ 8981 in[0] = val; 8982 8983 /* flags */ 8984 irn_flags_ |= arch_irn_flags_rematerializable; 8985 8986 /* create node */ 8987 assert(op != NULL); 8988 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 8989 8990 /* init node attributes */ 8991 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 8992 8993 info = be_get_info(res); 8994 (void) info; /* avoid potential warning */ 8995 info->out_infos[0].req = &ia32_requirements_gp_in_r1; 8996 8997 8998 /* optimize node */ 8999 res = optimize_node(res); 9000 irn_verify_irg(res, irg); 9001 9002 return res; 9003} 9004 9005/** 9006 * construct NoReg_FP node 9007 */ 9008ir_node *new_bd_ia32_NoReg_FP(dbg_info *dbgi, ir_node *block) 9009{ 9010 ir_graph *irg = get_irn_irg(block); 9011 ir_op *op = op_ia32_NoReg_FP; 9012 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 9013 ir_node *res; 9014 backend_info_t *info; 9015 int arity = 0; 9016 ir_node **in = NULL; 9017 int n_res = 1; 9018 ir_mode *mode = ia32_mode_E; 9019 static const arch_register_req_t **in_reqs = NULL; 9020 9021 /* flags */ 9022 irn_flags_ |= arch_irn_flags_not_scheduled; 9023 9024 /* create node */ 9025 assert(op != NULL); 9026 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 9027 9028 /* init node attributes */ 9029 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 9030 init_ia32_x87_attributes(res); 9031 9032 info = be_get_info(res); 9033 (void) info; /* avoid potential warning */ 9034 info->out_infos[0].req = &ia32_requirements_fp_fp_NOREG_I; 9035 9036 9037 /* optimize node */ 9038 res = optimize_node(res); 9039 irn_verify_irg(res, irg); 9040 9041 return res; 9042} 9043 9044/** 9045 * construct AndMem node 9046 */ 9047ir_node *new_bd_ia32_AndMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val) 9048{ 9049 ir_graph *irg = get_irn_irg(block); 9050 ir_op *op = op_ia32_AndMem; 9051 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 9052 ir_node *res; 9053 backend_info_t *info; 9054 int arity = 4; 9055 ir_node *in[4]; 9056 int n_res = 1; 9057 ir_mode *mode = mode_M; 9058 static const arch_register_req_t *in_reqs[] = 9059 { 9060 & ia32_requirements_gp_gp, 9061 & ia32_requirements_gp_gp, 9062 & ia32_requirements__none, 9063 & ia32_requirements_gp_gp, 9064 }; 9065 9066 /* construct in array */ 9067 in[0] = base; 9068 in[1] = index; 9069 in[2] = mem; 9070 in[3] = val; 9071 9072 /* flags */ 9073 irn_flags_ |= arch_irn_flags_rematerializable; 9074 9075 /* create node */ 9076 assert(op != NULL); 9077 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 9078 9079 /* init node attributes */ 9080 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 9081 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 9082 9083 info = be_get_info(res); 9084 (void) info; /* avoid potential warning */ 9085 info->out_infos[0].req = &ia32_requirements__none; 9086 9087 9088 /* optimize node */ 9089 res = optimize_node(res); 9090 irn_verify_irg(res, irg); 9091 9092 return res; 9093} 9094 9095/** 9096 * construct femms node 9097 */ 9098ir_node *new_bd_ia32_femms(dbg_info *dbgi, ir_node *block) 9099{ 9100 ir_graph *irg = get_irn_irg(block); 9101 ir_op *op = op_ia32_femms; 9102 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 9103 ir_node *res; 9104 backend_info_t *info; 9105 int arity = 0; 9106 ir_node **in = NULL; 9107 int n_res = 1; 9108 ir_mode *mode = mode_ANY; 9109 static const arch_register_req_t **in_reqs = NULL; 9110 9111 /* create node */ 9112 assert(op != NULL); 9113 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 9114 9115 /* init node attributes */ 9116 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 9117 init_ia32_x87_attributes(res); 9118 9119 info = be_get_info(res); 9120 (void) info; /* avoid potential warning */ 9121 info->out_infos[0].req = &ia32_requirements__none; 9122 9123 9124 /* optimize node */ 9125 res = optimize_node(res); 9126 irn_verify_irg(res, irg); 9127 9128 return res; 9129} 9130 9131/** 9132 * construct xStoreSimple node 9133 */ 9134ir_node *new_bd_ia32_xStoreSimple(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *val) 9135{ 9136 ir_graph *irg = get_irn_irg(block); 9137 ir_op *op = op_ia32_xStoreSimple; 9138 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 9139 ir_node *res; 9140 backend_info_t *info; 9141 int arity = 4; 9142 ir_node *in[4]; 9143 int n_res = 3; 9144 ir_mode *mode = mode_T; 9145 static const arch_register_req_t *in_reqs[] = 9146 { 9147 & ia32_requirements_gp_gp, 9148 & ia32_requirements_gp_gp, 9149 & ia32_requirements__none, 9150 & ia32_requirements_xmm_xmm, 9151 }; 9152 9153 /* construct in array */ 9154 in[0] = base; 9155 in[1] = index; 9156 in[2] = mem; 9157 in[3] = val; 9158 9159 /* create node */ 9160 assert(op != NULL); 9161 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 9162 9163 /* init node attributes */ 9164 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 9165 9166 info = be_get_info(res); 9167 (void) info; /* avoid potential warning */ 9168 info->out_infos[0].req = &ia32_requirements__none; 9169 info->out_infos[1].req = &ia32_requirements__none; 9170 info->out_infos[2].req = &ia32_requirements__none; 9171 9172 9173 /* optimize node */ 9174 res = optimize_node(res); 9175 irn_verify_irg(res, irg); 9176 9177 return res; 9178} 9179 9180/** 9181 * construct And node 9182 */ 9183ir_node *new_bd_ia32_And(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right) 9184{ 9185 ir_graph *irg = get_irn_irg(block); 9186 ir_op *op = op_ia32_And; 9187 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 9188 ir_node *res; 9189 backend_info_t *info; 9190 int arity = 5; 9191 ir_node *in[5]; 9192 int n_res = 3; 9193 ir_mode *mode = mode_Iu; 9194 static const arch_register_req_t *in_reqs[] = 9195 { 9196 & ia32_requirements_gp_gp, 9197 & ia32_requirements_gp_gp, 9198 & ia32_requirements__none, 9199 & ia32_requirements_gp_gp, 9200 & ia32_requirements_gp_gp, 9201 }; 9202 9203 /* construct in array */ 9204 in[0] = base; 9205 in[1] = index; 9206 in[2] = mem; 9207 in[3] = left; 9208 in[4] = right; 9209 9210 /* flags */ 9211 irn_flags_ |= arch_irn_flags_rematerializable; 9212 9213 /* create node */ 9214 assert(op != NULL); 9215 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 9216 9217 /* init node attributes */ 9218 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 9219 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 9220 set_ia32_am_support(res, ia32_am_binary); 9221 info = be_get_info(res); 9222 (void) info; /* avoid potential warning */ 9223 info->out_infos[0].req = &ia32_requirements_gp_in_r4_in_r5; 9224 info->out_infos[1].req = &ia32_requirements_flags_flags; 9225 info->out_infos[2].req = &ia32_requirements__none; 9226 9227 9228 /* optimize node */ 9229 res = optimize_node(res); 9230 irn_verify_irg(res, irg); 9231 9232 return res; 9233} 9234 9235/** 9236 * construct Jcc node 9237 */ 9238ir_node *new_bd_ia32_Jcc(dbg_info *dbgi, ir_node *block, ir_node *eflags, ia32_condition_code_t condition_code) 9239{ 9240 ir_graph *irg = get_irn_irg(block); 9241 ir_op *op = op_ia32_Jcc; 9242 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 9243 ir_node *res; 9244 backend_info_t *info; 9245 int arity = 1; 9246 ir_node *in[1]; 9247 int n_res = 2; 9248 ir_mode *mode = mode_T; 9249 static const arch_register_req_t *in_reqs[] = 9250 { 9251 & ia32_requirements_flags_eflags, 9252 }; 9253 9254 /* construct in array */ 9255 in[0] = eflags; 9256 9257 /* create node */ 9258 assert(op != NULL); 9259 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 9260 9261 /* init node attributes */ 9262 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 9263 init_ia32_condcode_attributes(res, condition_code); 9264 9265 info = be_get_info(res); 9266 (void) info; /* avoid potential warning */ 9267 info->out_infos[0].req = &ia32_requirements__none; 9268 info->out_infos[1].req = &ia32_requirements__none; 9269 9270 9271 /* optimize node */ 9272 res = optimize_node(res); 9273 irn_verify_irg(res, irg); 9274 9275 return res; 9276} 9277 9278/** 9279 * construct Asm node 9280 */ 9281ir_node *new_bd_ia32_Asm(dbg_info *dbgi, ir_node *block, int arity, ir_node *in[], int n_res, ident *asm_text, const ia32_asm_reg_t *register_map) 9282{ 9283 ir_graph *irg = get_irn_irg(block); 9284 ir_op *op = op_ia32_Asm; 9285 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 9286 ir_node *res; 9287 backend_info_t *info; 9288 ir_mode *mode = mode_T; 9289 static const arch_register_req_t **in_reqs = NULL; 9290 ia32_asm_attr_t *attr; 9291 9292 /* create node */ 9293 assert(op != NULL); 9294 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 9295 9296 /* init node attributes */ 9297 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 9298 init_ia32_x87_attributes(res); init_ia32_asm_attributes(res); 9299 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 9300 9301 info = be_get_info(res); 9302 (void) info; /* avoid potential warning */ 9303 9304 9305 attr = (ia32_asm_attr_t*)get_irn_generic_attr(res); 9306 (void) attr; /* avoid potential warning */ 9307 attr->asm_text = asm_text; 9308 attr->register_map = register_map; 9309 9310 /* optimize node */ 9311 res = optimize_node(res); 9312 irn_verify_irg(res, irg); 9313 9314 return res; 9315} 9316 9317/** 9318 * construct l_Sbb node 9319 */ 9320ir_node *new_bd_ia32_l_Sbb(dbg_info *dbgi, ir_node *block, ir_node *minuend, ir_node *subtrahend, ir_node *eflags, ir_mode *mode) 9321{ 9322 ir_graph *irg = get_irn_irg(block); 9323 ir_op *op = op_ia32_l_Sbb; 9324 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 9325 ir_node *res; 9326 backend_info_t *info; 9327 int arity = 3; 9328 ir_node *in[3]; 9329 int n_res = 0; 9330 static const arch_register_req_t **in_reqs = NULL; 9331 9332 /* construct in array */ 9333 in[0] = minuend; 9334 in[1] = subtrahend; 9335 in[2] = eflags; 9336 9337 /* create node */ 9338 assert(op != NULL); 9339 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 9340 9341 /* init node attributes */ 9342 (void)in;(void)irn_flags_;(void)in_reqs;(void)n_res; 9343 9344 info = be_get_info(res); 9345 (void) info; /* avoid potential warning */ 9346 9347 9348 /* optimize node */ 9349 res = optimize_node(res); 9350 irn_verify_irg(res, irg); 9351 9352 return res; 9353} 9354 9355/** 9356 * construct Bsr node 9357 */ 9358ir_node *new_bd_ia32_Bsr(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *operand) 9359{ 9360 ir_graph *irg = get_irn_irg(block); 9361 ir_op *op = op_ia32_Bsr; 9362 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 9363 ir_node *res; 9364 backend_info_t *info; 9365 int arity = 4; 9366 ir_node *in[4]; 9367 int n_res = 3; 9368 ir_mode *mode = mode_Iu; 9369 static const arch_register_req_t *in_reqs[] = 9370 { 9371 & ia32_requirements_gp_gp, 9372 & ia32_requirements_gp_gp, 9373 & ia32_requirements__none, 9374 & ia32_requirements_gp_gp, 9375 }; 9376 9377 /* construct in array */ 9378 in[0] = base; 9379 in[1] = index; 9380 in[2] = mem; 9381 in[3] = operand; 9382 9383 /* flags */ 9384 irn_flags_ |= arch_irn_flags_rematerializable; 9385 9386 /* create node */ 9387 assert(op != NULL); 9388 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 9389 9390 /* init node attributes */ 9391 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 9392 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 9393 set_ia32_am_support(res, ia32_am_binary); 9394 info = be_get_info(res); 9395 (void) info; /* avoid potential warning */ 9396 info->out_infos[0].req = &ia32_requirements_gp_gp; 9397 info->out_infos[1].req = &ia32_requirements_flags_flags; 9398 info->out_infos[2].req = &ia32_requirements__none; 9399 9400 9401 /* optimize node */ 9402 res = optimize_node(res); 9403 irn_verify_irg(res, irg); 9404 9405 return res; 9406} 9407 9408/** 9409 * construct Bswap16 node 9410 */ 9411ir_node *new_bd_ia32_Bswap16(dbg_info *dbgi, ir_node *block, ir_node *val) 9412{ 9413 ir_graph *irg = get_irn_irg(block); 9414 ir_op *op = op_ia32_Bswap16; 9415 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 9416 ir_node *res; 9417 backend_info_t *info; 9418 int arity = 1; 9419 ir_node *in[1]; 9420 int n_res = 1; 9421 ir_mode *mode = mode_Iu; 9422 static const arch_register_req_t *in_reqs[] = 9423 { 9424 & ia32_requirements_gp_eax_ebx_ecx_edx, 9425 }; 9426 9427 /* construct in array */ 9428 in[0] = val; 9429 9430 /* flags */ 9431 irn_flags_ |= arch_irn_flags_rematerializable; 9432 9433 /* create node */ 9434 assert(op != NULL); 9435 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 9436 9437 /* init node attributes */ 9438 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 9439 9440 info = be_get_info(res); 9441 (void) info; /* avoid potential warning */ 9442 info->out_infos[0].req = &ia32_requirements_gp_in_r1; 9443 9444 9445 /* optimize node */ 9446 res = optimize_node(res); 9447 irn_verify_irg(res, irg); 9448 9449 return res; 9450} 9451 9452/** 9453 * construct Inport node 9454 */ 9455ir_node *new_bd_ia32_Inport(dbg_info *dbgi, ir_node *block, ir_node *port, ir_node *mem) 9456{ 9457 ir_graph *irg = get_irn_irg(block); 9458 ir_op *op = op_ia32_Inport; 9459 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 9460 ir_node *res; 9461 backend_info_t *info; 9462 int arity = 2; 9463 ir_node *in[2]; 9464 int n_res = 2; 9465 ir_mode *mode = mode_T; 9466 static const arch_register_req_t *in_reqs[] = 9467 { 9468 & ia32_requirements_gp_edx, 9469 & ia32_requirements__none, 9470 }; 9471 9472 /* construct in array */ 9473 in[0] = port; 9474 in[1] = mem; 9475 9476 /* flags */ 9477 irn_flags_ |= arch_irn_flags_rematerializable; 9478 9479 /* create node */ 9480 assert(op != NULL); 9481 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 9482 9483 /* init node attributes */ 9484 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 9485 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 9486 9487 info = be_get_info(res); 9488 (void) info; /* avoid potential warning */ 9489 info->out_infos[0].req = &ia32_requirements_gp_eax; 9490 info->out_infos[1].req = &ia32_requirements__none; 9491 9492 9493 /* optimize node */ 9494 res = optimize_node(res); 9495 irn_verify_irg(res, irg); 9496 9497 return res; 9498} 9499 9500/** 9501 * construct SarMem node 9502 */ 9503ir_node *new_bd_ia32_SarMem(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *count) 9504{ 9505 ir_graph *irg = get_irn_irg(block); 9506 ir_op *op = op_ia32_SarMem; 9507 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 9508 ir_node *res; 9509 backend_info_t *info; 9510 int arity = 4; 9511 ir_node *in[4]; 9512 int n_res = 1; 9513 ir_mode *mode = mode_M; 9514 static const arch_register_req_t *in_reqs[] = 9515 { 9516 & ia32_requirements_gp_gp, 9517 & ia32_requirements_gp_gp, 9518 & ia32_requirements__none, 9519 & ia32_requirements_gp_ecx, 9520 }; 9521 9522 /* construct in array */ 9523 in[0] = base; 9524 in[1] = index; 9525 in[2] = mem; 9526 in[3] = count; 9527 9528 /* flags */ 9529 irn_flags_ |= arch_irn_flags_rematerializable; 9530 9531 /* create node */ 9532 assert(op != NULL); 9533 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 9534 9535 /* init node attributes */ 9536 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 9537 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 9538 9539 info = be_get_info(res); 9540 (void) info; /* avoid potential warning */ 9541 info->out_infos[0].req = &ia32_requirements__none; 9542 9543 9544 /* optimize node */ 9545 res = optimize_node(res); 9546 irn_verify_irg(res, irg); 9547 9548 return res; 9549} 9550 9551/** 9552 * construct RepPrefix node 9553 */ 9554ir_node *new_bd_ia32_RepPrefix(dbg_info *dbgi, ir_node *block) 9555{ 9556 ir_graph *irg = get_irn_irg(block); 9557 ir_op *op = op_ia32_RepPrefix; 9558 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 9559 ir_node *res; 9560 backend_info_t *info; 9561 int arity = 0; 9562 ir_node **in = NULL; 9563 int n_res = 0; 9564 ir_mode *mode = mode_M; 9565 static const arch_register_req_t **in_reqs = NULL; 9566 9567 /* create node */ 9568 assert(op != NULL); 9569 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 9570 9571 /* init node attributes */ 9572 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 9573 9574 info = be_get_info(res); 9575 (void) info; /* avoid potential warning */ 9576 9577 9578 /* optimize node */ 9579 res = optimize_node(res); 9580 irn_verify_irg(res, irg); 9581 9582 return res; 9583} 9584 9585/** 9586 * construct Adc node 9587 */ 9588ir_node *new_bd_ia32_Adc(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right, ir_node *eflags) 9589{ 9590 ir_graph *irg = get_irn_irg(block); 9591 ir_op *op = op_ia32_Adc; 9592 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 9593 ir_node *res; 9594 backend_info_t *info; 9595 int arity = 6; 9596 ir_node *in[6]; 9597 int n_res = 3; 9598 ir_mode *mode = mode_Iu; 9599 static const arch_register_req_t *in_reqs[] = 9600 { 9601 & ia32_requirements_gp_gp, 9602 & ia32_requirements_gp_gp, 9603 & ia32_requirements__none, 9604 & ia32_requirements_gp_gp, 9605 & ia32_requirements_gp_gp, 9606 & ia32_requirements_flags_flags, 9607 }; 9608 9609 /* construct in array */ 9610 in[0] = base; 9611 in[1] = index; 9612 in[2] = mem; 9613 in[3] = left; 9614 in[4] = right; 9615 in[5] = eflags; 9616 9617 /* create node */ 9618 assert(op != NULL); 9619 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 9620 9621 /* init node attributes */ 9622 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 9623 arch_add_irn_flags(res, arch_irn_flags_modify_flags); 9624 set_ia32_am_support(res, ia32_am_binary); 9625 info = be_get_info(res); 9626 (void) info; /* avoid potential warning */ 9627 info->out_infos[0].req = &ia32_requirements_gp_in_r4_in_r5; 9628 info->out_infos[1].req = &ia32_requirements_flags_flags; 9629 info->out_infos[2].req = &ia32_requirements__none; 9630 9631 9632 /* optimize node */ 9633 res = optimize_node(res); 9634 irn_verify_irg(res, irg); 9635 9636 return res; 9637} 9638 9639/** 9640 * construct l_Mul node 9641 */ 9642ir_node *new_bd_ia32_l_Mul(dbg_info *dbgi, ir_node *block, ir_node *left, ir_node *right) 9643{ 9644 ir_graph *irg = get_irn_irg(block); 9645 ir_op *op = op_ia32_l_Mul; 9646 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 9647 ir_node *res; 9648 backend_info_t *info; 9649 int arity = 2; 9650 ir_node *in[2]; 9651 int n_res = 4; 9652 ir_mode *mode = mode_T; 9653 static const arch_register_req_t **in_reqs = NULL; 9654 9655 /* construct in array */ 9656 in[0] = left; 9657 in[1] = right; 9658 9659 /* create node */ 9660 assert(op != NULL); 9661 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 9662 9663 /* init node attributes */ 9664 (void)in;(void)irn_flags_;(void)in_reqs;(void)n_res; 9665 9666 info = be_get_info(res); 9667 (void) info; /* avoid potential warning */ 9668 9669 9670 /* optimize node */ 9671 res = optimize_node(res); 9672 irn_verify_irg(res, irg); 9673 9674 return res; 9675} 9676 9677/** 9678 * construct xAndNot node 9679 */ 9680ir_node *new_bd_ia32_xAndNot(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem, ir_node *left, ir_node *right) 9681{ 9682 ir_graph *irg = get_irn_irg(block); 9683 ir_op *op = op_ia32_xAndNot; 9684 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 9685 ir_node *res; 9686 backend_info_t *info; 9687 int arity = 5; 9688 ir_node *in[5]; 9689 int n_res = 3; 9690 ir_mode *mode = mode_D; 9691 static const arch_register_req_t *in_reqs[] = 9692 { 9693 & ia32_requirements_gp_gp, 9694 & ia32_requirements_gp_gp, 9695 & ia32_requirements__none, 9696 & ia32_requirements_xmm_xmm, 9697 & ia32_requirements_xmm_xmm, 9698 }; 9699 9700 /* construct in array */ 9701 in[0] = base; 9702 in[1] = index; 9703 in[2] = mem; 9704 in[3] = left; 9705 in[4] = right; 9706 9707 /* flags */ 9708 irn_flags_ |= arch_irn_flags_rematerializable; 9709 9710 /* create node */ 9711 assert(op != NULL); 9712 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 9713 9714 /* init node attributes */ 9715 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 9716 set_ia32_am_support(res, ia32_am_binary); 9717 info = be_get_info(res); 9718 (void) info; /* avoid potential warning */ 9719 info->out_infos[0].req = &ia32_requirements_xmm_in_r4_not_in_r5; 9720 info->out_infos[1].req = &ia32_requirements_flags_flags; 9721 info->out_infos[2].req = &ia32_requirements__none; 9722 9723 9724 /* optimize node */ 9725 res = optimize_node(res); 9726 irn_verify_irg(res, irg); 9727 9728 return res; 9729} 9730 9731/** 9732 * construct Load node 9733 */ 9734ir_node *new_bd_ia32_Load(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem) 9735{ 9736 ir_graph *irg = get_irn_irg(block); 9737 ir_op *op = op_ia32_Load; 9738 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 9739 ir_node *res; 9740 backend_info_t *info; 9741 int arity = 3; 9742 ir_node *in[3]; 9743 int n_res = 5; 9744 ir_mode *mode = mode_T; 9745 static const arch_register_req_t *in_reqs[] = 9746 { 9747 & ia32_requirements_gp_gp, 9748 & ia32_requirements_gp_gp, 9749 & ia32_requirements__none, 9750 }; 9751 9752 /* construct in array */ 9753 in[0] = base; 9754 in[1] = index; 9755 in[2] = mem; 9756 9757 /* create node */ 9758 assert(op != NULL); 9759 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 9760 9761 /* init node attributes */ 9762 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 9763 9764 info = be_get_info(res); 9765 (void) info; /* avoid potential warning */ 9766 info->out_infos[0].req = &ia32_requirements_gp_gp; 9767 info->out_infos[1].req = &ia32_requirements__none; 9768 info->out_infos[2].req = &ia32_requirements__none; 9769 info->out_infos[3].req = &ia32_requirements__none; 9770 info->out_infos[4].req = &ia32_requirements__none; 9771 9772 9773 /* optimize node */ 9774 res = optimize_node(res); 9775 irn_verify_irg(res, irg); 9776 9777 return res; 9778} 9779 9780/** 9781 * construct Prefetch node 9782 */ 9783ir_node *new_bd_ia32_Prefetch(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index, ir_node *mem) 9784{ 9785 ir_graph *irg = get_irn_irg(block); 9786 ir_op *op = op_ia32_Prefetch; 9787 arch_irn_flags_t irn_flags_ = arch_irn_flags_none; 9788 ir_node *res; 9789 backend_info_t *info; 9790 int arity = 3; 9791 ir_node *in[3]; 9792 int n_res = 1; 9793 ir_mode *mode = mode_T; 9794 static const arch_register_req_t *in_reqs[] = 9795 { 9796 & ia32_requirements_gp_gp, 9797 & ia32_requirements_gp_gp, 9798 & ia32_requirements__none, 9799 }; 9800 9801 /* construct in array */ 9802 in[0] = base; 9803 in[1] = index; 9804 in[2] = mem; 9805 9806 /* create node */ 9807 assert(op != NULL); 9808 res = new_ir_node(dbgi, irg, block, op, mode, arity, in); 9809 9810 /* init node attributes */ 9811 init_ia32_attributes(res, irn_flags_, in_reqs, n_res); 9812 9813 info = be_get_info(res); 9814 (void) info; /* avoid potential warning */ 9815 info->out_infos[0].req = &ia32_requirements__none; 9816 9817 9818 /* optimize node */ 9819 res = optimize_node(res); 9820 irn_verify_irg(res, irg); 9821 9822 return res; 9823} 9824 9825 9826 9827/** 9828 * Creates the ia32 specific Firm machine operations 9829 * needed for the assembler irgs. 9830 */ 9831void ia32_create_opcodes(const arch_irn_ops_t *be_ops) 9832{ 9833 ir_op *op; 9834 int cur_opcode = get_next_ir_opcodes(iro_ia32_last); 9835 9836 ia32_opcode_start = cur_opcode; 9837 op = new_ir_op(cur_opcode + iro_ia32_xZero, "ia32_xZero", op_pin_state_floats, irop_flag_none, oparity_zero, 0, sizeof(ia32_attr_t)); 9838 op->ops.be_ops = be_ops; 9839 op->ops.dump_node = ia32_dump_node; 9840 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 9841 op->ops.copy_attr = ia32_copy_attr; 9842 set_op_tag(op, ia32_op_tag); 9843 ia32_init_op(op, 3); 9844 op_ia32_xZero = op; 9845 op = new_ir_op(cur_opcode + iro_ia32_FldCW, "ia32_FldCW", op_pin_state_pinned, irop_flag_uses_memory, oparity_trinary, 0, sizeof(ia32_attr_t)); 9846 op->ops.be_ops = be_ops; 9847 op->ops.dump_node = ia32_dump_node; 9848 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 9849 op->ops.copy_attr = ia32_copy_attr; 9850 set_op_tag(op, ia32_op_tag); 9851 ia32_init_op(op, 5); 9852 op_ia32_FldCW = op; 9853 op = new_ir_op(cur_opcode + iro_ia32_fadd, "ia32_fadd", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_x87_attr_t)); 9854 op->ops.be_ops = be_ops; 9855 op->ops.dump_node = ia32_dump_node; 9856 op->ops.node_cmp_attr = ia32_compare_x87_attr; 9857 op->ops.copy_attr = ia32_copy_attr; 9858 set_op_tag(op, ia32_op_tag); 9859 ia32_init_op(op, 4); 9860 op_ia32_fadd = op; 9861 op = new_ir_op(cur_opcode + iro_ia32_ShrMem, "ia32_ShrMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 9862 op->ops.be_ops = be_ops; 9863 op->ops.dump_node = ia32_dump_node; 9864 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 9865 op->ops.copy_attr = ia32_copy_attr; 9866 set_op_tag(op, ia32_op_tag); 9867 ia32_init_op(op, 1); 9868 op_ia32_ShrMem = op; 9869 op = new_ir_op(cur_opcode + iro_ia32_Immediate, "ia32_Immediate", op_pin_state_pinned, irop_flag_constlike, oparity_zero, 0, sizeof(ia32_immediate_attr_t)); 9870 op->ops.be_ops = be_ops; 9871 op->ops.dump_node = ia32_dump_node; 9872 op->ops.node_cmp_attr = ia32_compare_immediate_attr; 9873 op->ops.copy_attr = ia32_copy_attr; 9874 op->ops.hash = ia32_hash_Immediate; 9875 set_op_tag(op, ia32_op_tag); 9876 ia32_init_op(op, 0); 9877 op_ia32_Immediate = op; 9878 op = new_ir_op(cur_opcode + iro_ia32_CvtSI2SS, "ia32_CvtSI2SS", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 9879 op->ops.be_ops = be_ops; 9880 op->ops.dump_node = ia32_dump_node; 9881 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 9882 op->ops.copy_attr = ia32_copy_attr; 9883 set_op_tag(op, ia32_op_tag); 9884 ia32_init_op(op, 2); 9885 op_ia32_CvtSI2SS = op; 9886 op = new_ir_op(cur_opcode + iro_ia32_Bsf, "ia32_Bsf", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 9887 op->ops.be_ops = be_ops; 9888 op->ops.dump_node = ia32_dump_node; 9889 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 9890 op->ops.copy_attr = ia32_copy_attr; 9891 set_op_tag(op, ia32_op_tag); 9892 ia32_init_op(op, 1); 9893 op_ia32_Bsf = op; 9894 op = new_ir_op(cur_opcode + iro_ia32_LdTls, "ia32_LdTls", op_pin_state_floats, irop_flag_none, oparity_zero, 0, sizeof(ia32_attr_t)); 9895 op->ops.be_ops = be_ops; 9896 op->ops.dump_node = ia32_dump_node; 9897 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 9898 op->ops.copy_attr = ia32_copy_attr; 9899 set_op_tag(op, ia32_op_tag); 9900 ia32_init_op(op, 1); 9901 op_ia32_LdTls = op; 9902 op = new_ir_op(cur_opcode + iro_ia32_ShlD, "ia32_ShlD", op_pin_state_floats, irop_flag_none, oparity_trinary, 0, sizeof(ia32_attr_t)); 9903 op->ops.be_ops = be_ops; 9904 op->ops.dump_node = ia32_dump_node; 9905 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 9906 op->ops.copy_attr = ia32_copy_attr; 9907 set_op_tag(op, ia32_op_tag); 9908 ia32_init_op(op, 6); 9909 op_ia32_ShlD = op; 9910 op = new_ir_op(cur_opcode + iro_ia32_PopEbp, "ia32_PopEbp", op_pin_state_exc_pinned, irop_flag_none, oparity_binary, 0, sizeof(ia32_attr_t)); 9911 op->ops.be_ops = be_ops; 9912 op->ops.dump_node = ia32_dump_node; 9913 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 9914 op->ops.copy_attr = ia32_copy_attr; 9915 set_op_tag(op, ia32_op_tag); 9916 ia32_init_op(op, 3); 9917 op_ia32_PopEbp = op; 9918 op = new_ir_op(cur_opcode + iro_ia32_Inc, "ia32_Inc", op_pin_state_floats, irop_flag_none, oparity_unary, 0, sizeof(ia32_attr_t)); 9919 op->ops.be_ops = be_ops; 9920 op->ops.dump_node = ia32_dump_node; 9921 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 9922 op->ops.copy_attr = ia32_copy_attr; 9923 set_op_tag(op, ia32_op_tag); 9924 ia32_init_op(op, 1); 9925 op_ia32_Inc = op; 9926 op = new_ir_op(cur_opcode + iro_ia32_xStore, "ia32_xStore", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_any, 0, sizeof(ia32_attr_t)); 9927 op->ops.be_ops = be_ops; 9928 op->ops.dump_node = ia32_dump_node; 9929 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 9930 op->ops.copy_attr = ia32_copy_attr; 9931 ir_op_set_memory_index(op, n_ia32_xStore_mem); 9932 ir_op_set_fragile_indices(op, pn_ia32_xStore_X_regular, pn_ia32_xStore_X_except); 9933 set_op_tag(op, ia32_op_tag); 9934 ia32_init_op(op, 0); 9935 op_ia32_xStore = op; 9936 op = new_ir_op(cur_opcode + iro_ia32_xxLoad, "ia32_xxLoad", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_trinary, 0, sizeof(ia32_attr_t)); 9937 op->ops.be_ops = be_ops; 9938 op->ops.dump_node = ia32_dump_node; 9939 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 9940 op->ops.copy_attr = ia32_copy_attr; 9941 ir_op_set_memory_index(op, n_ia32_xxLoad_mem); 9942 ir_op_set_fragile_indices(op, pn_ia32_xxLoad_X_regular, pn_ia32_xxLoad_X_except); 9943 set_op_tag(op, ia32_op_tag); 9944 ia32_init_op(op, 1); 9945 op_ia32_xxLoad = op; 9946 op = new_ir_op(cur_opcode + iro_ia32_xAnd, "ia32_xAnd", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 9947 op->ops.be_ops = be_ops; 9948 op->ops.dump_node = ia32_dump_node; 9949 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 9950 op->ops.copy_attr = ia32_copy_attr; 9951 set_op_tag(op, ia32_op_tag); 9952 ia32_init_op(op, 3); 9953 op_ia32_xAnd = op; 9954 op = new_ir_op(cur_opcode + iro_ia32_GetEIP, "ia32_GetEIP", op_pin_state_floats, irop_flag_constlike, oparity_zero, 0, sizeof(ia32_attr_t)); 9955 op->ops.be_ops = be_ops; 9956 op->ops.dump_node = ia32_dump_node; 9957 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 9958 op->ops.copy_attr = ia32_copy_attr; 9959 set_op_tag(op, ia32_op_tag); 9960 ia32_init_op(op, 5); 9961 op_ia32_GetEIP = op; 9962 op = new_ir_op(cur_opcode + iro_ia32_xAdd, "ia32_xAdd", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 9963 op->ops.be_ops = be_ops; 9964 op->ops.dump_node = ia32_dump_node; 9965 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 9966 op->ops.copy_attr = ia32_copy_attr; 9967 set_op_tag(op, ia32_op_tag); 9968 ia32_init_op(op, 4); 9969 op_ia32_xAdd = op; 9970 op = new_ir_op(cur_opcode + iro_ia32_xPsllq, "ia32_xPsllq", op_pin_state_floats, irop_flag_none, oparity_binary, 0, sizeof(ia32_attr_t)); 9971 op->ops.be_ops = be_ops; 9972 op->ops.dump_node = ia32_dump_node; 9973 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 9974 op->ops.copy_attr = ia32_copy_attr; 9975 set_op_tag(op, ia32_op_tag); 9976 ia32_init_op(op, 3); 9977 op_ia32_xPsllq = op; 9978 op = new_ir_op(cur_opcode + iro_ia32_xxStore, "ia32_xxStore", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_any, 0, sizeof(ia32_attr_t)); 9979 op->ops.be_ops = be_ops; 9980 op->ops.dump_node = ia32_dump_node; 9981 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 9982 op->ops.copy_attr = ia32_copy_attr; 9983 ir_op_set_memory_index(op, n_ia32_xxStore_mem); 9984 ir_op_set_fragile_indices(op, pn_ia32_xxStore_X_regular, pn_ia32_xxStore_X_except); 9985 set_op_tag(op, ia32_op_tag); 9986 ia32_init_op(op, 1); 9987 op_ia32_xxStore = op; 9988 op = new_ir_op(cur_opcode + iro_ia32_Call, "ia32_Call", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_any, 0, sizeof(ia32_call_attr_t)); 9989 op->ops.be_ops = be_ops; 9990 op->ops.dump_node = ia32_dump_node; 9991 op->ops.node_cmp_attr = ia32_compare_call_attr; 9992 op->ops.copy_attr = ia32_copy_attr; 9993 ir_op_set_memory_index(op, n_ia32_Call_mem); 9994 ir_op_set_fragile_indices(op, pn_ia32_Call_X_regular, pn_ia32_Call_X_except); 9995 set_op_tag(op, ia32_op_tag); 9996 ia32_init_op(op, 4); 9997 op_ia32_Call = op; 9998 op = new_ir_op(cur_opcode + iro_ia32_FnstCWNOP, "ia32_FnstCWNOP", op_pin_state_pinned, irop_flag_uses_memory, oparity_unary, 0, sizeof(ia32_attr_t)); 9999 op->ops.be_ops = be_ops; 10000 op->ops.dump_node = ia32_dump_node; 10001 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10002 op->ops.copy_attr = ia32_copy_attr; 10003 set_op_tag(op, ia32_op_tag); 10004 ia32_init_op(op, 0); 10005 op_ia32_FnstCWNOP = op; 10006 op = new_ir_op(cur_opcode + iro_ia32_XorMem8Bit, "ia32_XorMem8Bit", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10007 op->ops.be_ops = be_ops; 10008 op->ops.dump_node = ia32_dump_node; 10009 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10010 op->ops.copy_attr = ia32_copy_attr; 10011 set_op_tag(op, ia32_op_tag); 10012 ia32_init_op(op, 1); 10013 op_ia32_XorMem8Bit = op; 10014 op = new_ir_op(cur_opcode + iro_ia32_fldl2t, "ia32_fldl2t", op_pin_state_floats, irop_flag_none, oparity_zero, 0, sizeof(ia32_x87_attr_t)); 10015 op->ops.be_ops = be_ops; 10016 op->ops.dump_node = ia32_dump_node; 10017 op->ops.node_cmp_attr = ia32_compare_x87_attr; 10018 op->ops.copy_attr = ia32_copy_attr; 10019 set_op_tag(op, ia32_op_tag); 10020 ia32_init_op(op, 4); 10021 op_ia32_fldl2t = op; 10022 op = new_ir_op(cur_opcode + iro_ia32_fisttp, "ia32_fisttp", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_any, 0, sizeof(ia32_x87_attr_t)); 10023 op->ops.be_ops = be_ops; 10024 op->ops.dump_node = ia32_dump_node; 10025 op->ops.node_cmp_attr = ia32_compare_x87_attr; 10026 op->ops.copy_attr = ia32_copy_attr; 10027 ir_op_set_memory_index(op, n_ia32_fisttp_mem); 10028 ir_op_set_fragile_indices(op, pn_ia32_fisttp_X_regular, pn_ia32_fisttp_X_except); 10029 set_op_tag(op, ia32_op_tag); 10030 ia32_init_op(op, 4); 10031 op_ia32_fisttp = op; 10032 op = new_ir_op(cur_opcode + iro_ia32_DecMem, "ia32_DecMem", op_pin_state_exc_pinned, irop_flag_none, oparity_trinary, 0, sizeof(ia32_attr_t)); 10033 op->ops.be_ops = be_ops; 10034 op->ops.dump_node = ia32_dump_node; 10035 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10036 op->ops.copy_attr = ia32_copy_attr; 10037 set_op_tag(op, ia32_op_tag); 10038 ia32_init_op(op, 1); 10039 op_ia32_DecMem = op; 10040 op = new_ir_op(cur_opcode + iro_ia32_emms, "ia32_emms", op_pin_state_floats, irop_flag_keep, oparity_zero, 0, sizeof(ia32_x87_attr_t)); 10041 op->ops.be_ops = be_ops; 10042 op->ops.dump_node = ia32_dump_node; 10043 op->ops.node_cmp_attr = cmp_attr_ia32_emms; 10044 op->ops.copy_attr = ia32_copy_attr; 10045 set_op_tag(op, ia32_op_tag); 10046 ia32_init_op(op, 3); 10047 op_ia32_emms = op; 10048 op = new_ir_op(cur_opcode + iro_ia32_xLoad, "ia32_xLoad", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_trinary, 0, sizeof(ia32_attr_t)); 10049 op->ops.be_ops = be_ops; 10050 op->ops.dump_node = ia32_dump_node; 10051 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10052 op->ops.copy_attr = ia32_copy_attr; 10053 ir_op_set_memory_index(op, n_ia32_xLoad_mem); 10054 ir_op_set_fragile_indices(op, pn_ia32_xLoad_X_regular, pn_ia32_xLoad_X_except); 10055 set_op_tag(op, ia32_op_tag); 10056 ia32_init_op(op, 0); 10057 op_ia32_xLoad = op; 10058 op = new_ir_op(cur_opcode + iro_ia32_l_FloattoLL, "ia32_l_FloattoLL", op_pin_state_floats, irop_flag_none, oparity_unary, 0, 0); 10059 op->ops.be_ops = be_ops; 10060 op->ops.dump_node = NULL; 10061 op->ops.node_cmp_attr = NULL; 10062 set_op_tag(op, ia32_op_tag); 10063 ia32_init_op(op, 0); 10064 op_ia32_l_FloattoLL = op; 10065 op = new_ir_op(cur_opcode + iro_ia32_CvtSI2SD, "ia32_CvtSI2SD", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10066 op->ops.be_ops = be_ops; 10067 op->ops.dump_node = ia32_dump_node; 10068 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10069 op->ops.copy_attr = ia32_copy_attr; 10070 set_op_tag(op, ia32_op_tag); 10071 ia32_init_op(op, 2); 10072 op_ia32_CvtSI2SD = op; 10073 op = new_ir_op(cur_opcode + iro_ia32_XorMem, "ia32_XorMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10074 op->ops.be_ops = be_ops; 10075 op->ops.dump_node = ia32_dump_node; 10076 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10077 op->ops.copy_attr = ia32_copy_attr; 10078 set_op_tag(op, ia32_op_tag); 10079 ia32_init_op(op, 1); 10080 op_ia32_XorMem = op; 10081 op = new_ir_op(cur_opcode + iro_ia32_CopyB, "ia32_CopyB", op_pin_state_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_any, 0, sizeof(ia32_copyb_attr_t)); 10082 op->ops.be_ops = be_ops; 10083 op->ops.dump_node = ia32_dump_node; 10084 op->ops.node_cmp_attr = ia32_compare_copyb_attr; 10085 op->ops.copy_attr = ia32_copy_attr; 10086 ir_op_set_memory_index(op, n_ia32_CopyB_mem); 10087 ir_op_set_fragile_indices(op, pn_ia32_CopyB_X_regular, pn_ia32_CopyB_X_except); 10088 set_op_tag(op, ia32_op_tag); 10089 ia32_init_op(op, 3); 10090 op_ia32_CopyB = op; 10091 op = new_ir_op(cur_opcode + iro_ia32_Xor0, "ia32_Xor0", op_pin_state_floats, irop_flag_constlike, oparity_zero, 0, sizeof(ia32_attr_t)); 10092 op->ops.be_ops = be_ops; 10093 op->ops.dump_node = ia32_dump_node; 10094 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10095 op->ops.copy_attr = ia32_copy_attr; 10096 set_op_tag(op, ia32_op_tag); 10097 ia32_init_op(op, 1); 10098 op_ia32_Xor0 = op; 10099 op = new_ir_op(cur_opcode + iro_ia32_Sar, "ia32_Sar", op_pin_state_floats, irop_flag_none, oparity_binary, 0, sizeof(ia32_attr_t)); 10100 op->ops.be_ops = be_ops; 10101 op->ops.dump_node = ia32_dump_node; 10102 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10103 op->ops.copy_attr = ia32_copy_attr; 10104 set_op_tag(op, ia32_op_tag); 10105 ia32_init_op(op, 1); 10106 op_ia32_Sar = op; 10107 op = new_ir_op(cur_opcode + iro_ia32_Div, "ia32_Div", op_pin_state_exc_pinned, irop_flag_fragile|irop_flag_uses_memory, oparity_any, 0, sizeof(ia32_attr_t)); 10108 op->ops.be_ops = be_ops; 10109 op->ops.dump_node = ia32_dump_node; 10110 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10111 op->ops.copy_attr = ia32_copy_attr; 10112 ir_op_set_memory_index(op, n_ia32_Div_mem); 10113 ir_op_set_fragile_indices(op, pn_ia32_Div_X_regular, pn_ia32_Div_X_except); 10114 set_op_tag(op, ia32_op_tag); 10115 ia32_init_op(op, 25); 10116 op_ia32_Div = op; 10117 op = new_ir_op(cur_opcode + iro_ia32_fpushCopy, "ia32_fpushCopy", op_pin_state_floats, irop_flag_none, oparity_unary, 0, sizeof(ia32_x87_attr_t)); 10118 op->ops.be_ops = be_ops; 10119 op->ops.dump_node = ia32_dump_node; 10120 op->ops.node_cmp_attr = cmp_attr_ia32_fpushCopy; 10121 op->ops.copy_attr = ia32_copy_attr; 10122 set_op_tag(op, ia32_op_tag); 10123 ia32_init_op(op, 1); 10124 op_ia32_fpushCopy = op; 10125 op = new_ir_op(cur_opcode + iro_ia32_Stc, "ia32_Stc", op_pin_state_floats, irop_flag_none, oparity_zero, 0, sizeof(ia32_attr_t)); 10126 op->ops.be_ops = be_ops; 10127 op->ops.dump_node = ia32_dump_node; 10128 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10129 op->ops.copy_attr = ia32_copy_attr; 10130 set_op_tag(op, ia32_op_tag); 10131 ia32_init_op(op, 1); 10132 op_ia32_Stc = op; 10133 op = new_ir_op(cur_opcode + iro_ia32_Fucomi, "ia32_Fucomi", op_pin_state_floats, irop_flag_none, oparity_binary, 0, sizeof(ia32_x87_attr_t)); 10134 op->ops.be_ops = be_ops; 10135 op->ops.dump_node = ia32_dump_node; 10136 op->ops.node_cmp_attr = ia32_compare_x87_attr; 10137 op->ops.copy_attr = ia32_copy_attr; 10138 set_op_tag(op, ia32_op_tag); 10139 ia32_init_op(op, 3); 10140 op_ia32_Fucomi = op; 10141 op = new_ir_op(cur_opcode + iro_ia32_fldl2e, "ia32_fldl2e", op_pin_state_floats, irop_flag_none, oparity_zero, 0, sizeof(ia32_x87_attr_t)); 10142 op->ops.be_ops = be_ops; 10143 op->ops.dump_node = ia32_dump_node; 10144 op->ops.node_cmp_attr = ia32_compare_x87_attr; 10145 op->ops.copy_attr = ia32_copy_attr; 10146 set_op_tag(op, ia32_op_tag); 10147 ia32_init_op(op, 4); 10148 op_ia32_fldl2e = op; 10149 op = new_ir_op(cur_opcode + iro_ia32_Enter, "ia32_Enter", op_pin_state_floats, irop_flag_none, oparity_unary, 0, sizeof(ia32_attr_t)); 10150 op->ops.be_ops = be_ops; 10151 op->ops.dump_node = ia32_dump_node; 10152 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10153 op->ops.copy_attr = ia32_copy_attr; 10154 set_op_tag(op, ia32_op_tag); 10155 ia32_init_op(op, 15); 10156 op_ia32_Enter = op; 10157 op = new_ir_op(cur_opcode + iro_ia32_fmul, "ia32_fmul", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_x87_attr_t)); 10158 op->ops.be_ops = be_ops; 10159 op->ops.dump_node = ia32_dump_node; 10160 op->ops.node_cmp_attr = ia32_compare_x87_attr; 10161 op->ops.copy_attr = ia32_copy_attr; 10162 set_op_tag(op, ia32_op_tag); 10163 ia32_init_op(op, 4); 10164 op_ia32_fmul = op; 10165 op = new_ir_op(cur_opcode + iro_ia32_l_IMul, "ia32_l_IMul", op_pin_state_floats, irop_flag_none, oparity_binary, 0, 0); 10166 op->ops.be_ops = be_ops; 10167 op->ops.dump_node = NULL; 10168 op->ops.node_cmp_attr = NULL; 10169 set_op_tag(op, ia32_op_tag); 10170 ia32_init_op(op, 0); 10171 op_ia32_l_IMul = op; 10172 op = new_ir_op(cur_opcode + iro_ia32_NoReg_XMM, "ia32_NoReg_XMM", op_pin_state_pinned, irop_flag_constlike|irop_flag_dump_noblock, oparity_zero, 0, sizeof(ia32_attr_t)); 10173 op->ops.be_ops = be_ops; 10174 op->ops.dump_node = ia32_dump_node; 10175 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10176 op->ops.copy_attr = ia32_copy_attr; 10177 set_op_tag(op, ia32_op_tag); 10178 ia32_init_op(op, 0); 10179 op_ia32_NoReg_XMM = op; 10180 op = new_ir_op(cur_opcode + iro_ia32_xMax, "ia32_xMax", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10181 op->ops.be_ops = be_ops; 10182 op->ops.dump_node = ia32_dump_node; 10183 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10184 op->ops.copy_attr = ia32_copy_attr; 10185 set_op_tag(op, ia32_op_tag); 10186 ia32_init_op(op, 2); 10187 op_ia32_xMax = op; 10188 op = new_ir_op(cur_opcode + iro_ia32_OrMem8Bit, "ia32_OrMem8Bit", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10189 op->ops.be_ops = be_ops; 10190 op->ops.dump_node = ia32_dump_node; 10191 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10192 op->ops.copy_attr = ia32_copy_attr; 10193 set_op_tag(op, ia32_op_tag); 10194 ia32_init_op(op, 1); 10195 op_ia32_OrMem8Bit = op; 10196 op = new_ir_op(cur_opcode + iro_ia32_Prefetch1, "ia32_Prefetch1", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_trinary, 0, sizeof(ia32_attr_t)); 10197 op->ops.be_ops = be_ops; 10198 op->ops.dump_node = ia32_dump_node; 10199 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10200 op->ops.copy_attr = ia32_copy_attr; 10201 set_op_tag(op, ia32_op_tag); 10202 ia32_init_op(op, 0); 10203 op_ia32_Prefetch1 = op; 10204 op = new_ir_op(cur_opcode + iro_ia32_fsub, "ia32_fsub", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_x87_attr_t)); 10205 op->ops.be_ops = be_ops; 10206 op->ops.dump_node = ia32_dump_node; 10207 op->ops.node_cmp_attr = ia32_compare_x87_attr; 10208 op->ops.copy_attr = ia32_copy_attr; 10209 set_op_tag(op, ia32_op_tag); 10210 ia32_init_op(op, 4); 10211 op_ia32_fsub = op; 10212 op = new_ir_op(cur_opcode + iro_ia32_Lea, "ia32_Lea", op_pin_state_floats, irop_flag_none, oparity_binary, 0, sizeof(ia32_attr_t)); 10213 op->ops.be_ops = be_ops; 10214 op->ops.dump_node = ia32_dump_node; 10215 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10216 op->ops.copy_attr = ia32_copy_attr; 10217 set_op_tag(op, ia32_op_tag); 10218 ia32_init_op(op, 2); 10219 op_ia32_Lea = op; 10220 op = new_ir_op(cur_opcode + iro_ia32_FtstFnstsw, "ia32_FtstFnstsw", op_pin_state_floats, irop_flag_none, oparity_unary, 0, sizeof(ia32_x87_attr_t)); 10221 op->ops.be_ops = be_ops; 10222 op->ops.dump_node = ia32_dump_node; 10223 op->ops.node_cmp_attr = ia32_compare_x87_attr; 10224 op->ops.copy_attr = ia32_copy_attr; 10225 set_op_tag(op, ia32_op_tag); 10226 ia32_init_op(op, 3); 10227 op_ia32_FtstFnstsw = op; 10228 op = new_ir_op(cur_opcode + iro_ia32_NotMem, "ia32_NotMem", op_pin_state_exc_pinned, irop_flag_none, oparity_trinary, 0, sizeof(ia32_attr_t)); 10229 op->ops.be_ops = be_ops; 10230 op->ops.dump_node = ia32_dump_node; 10231 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10232 op->ops.copy_attr = ia32_copy_attr; 10233 set_op_tag(op, ia32_op_tag); 10234 ia32_init_op(op, 1); 10235 op_ia32_NotMem = op; 10236 op = new_ir_op(cur_opcode + iro_ia32_Sbb0, "ia32_Sbb0", op_pin_state_floats, irop_flag_none, oparity_unary, 0, sizeof(ia32_attr_t)); 10237 op->ops.be_ops = be_ops; 10238 op->ops.dump_node = ia32_dump_node; 10239 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10240 op->ops.copy_attr = ia32_copy_attr; 10241 set_op_tag(op, ia32_op_tag); 10242 ia32_init_op(op, 1); 10243 op_ia32_Sbb0 = op; 10244 op = new_ir_op(cur_opcode + iro_ia32_Bt, "ia32_Bt", op_pin_state_exc_pinned, irop_flag_none, oparity_binary, 0, sizeof(ia32_attr_t)); 10245 op->ops.be_ops = be_ops; 10246 op->ops.dump_node = ia32_dump_node; 10247 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10248 op->ops.copy_attr = ia32_copy_attr; 10249 set_op_tag(op, ia32_op_tag); 10250 ia32_init_op(op, 1); 10251 op_ia32_Bt = op; 10252 op = new_ir_op(cur_opcode + iro_ia32_Or, "ia32_Or", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10253 op->ops.be_ops = be_ops; 10254 op->ops.dump_node = ia32_dump_node; 10255 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10256 op->ops.copy_attr = ia32_copy_attr; 10257 set_op_tag(op, ia32_op_tag); 10258 ia32_init_op(op, 1); 10259 op_ia32_Or = op; 10260 op = new_ir_op(cur_opcode + iro_ia32_Xor, "ia32_Xor", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10261 op->ops.be_ops = be_ops; 10262 op->ops.dump_node = ia32_dump_node; 10263 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10264 op->ops.copy_attr = ia32_copy_attr; 10265 set_op_tag(op, ia32_op_tag); 10266 ia32_init_op(op, 1); 10267 op_ia32_Xor = op; 10268 op = new_ir_op(cur_opcode + iro_ia32_CopyB_i, "ia32_CopyB_i", op_pin_state_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_trinary, 0, sizeof(ia32_copyb_attr_t)); 10269 op->ops.be_ops = be_ops; 10270 op->ops.dump_node = ia32_dump_node; 10271 op->ops.node_cmp_attr = ia32_compare_copyb_attr; 10272 op->ops.copy_attr = ia32_copy_attr; 10273 ir_op_set_memory_index(op, n_ia32_CopyB_i_mem); 10274 ir_op_set_fragile_indices(op, pn_ia32_CopyB_i_X_regular, pn_ia32_CopyB_i_X_except); 10275 set_op_tag(op, ia32_op_tag); 10276 ia32_init_op(op, 3); 10277 op_ia32_CopyB_i = op; 10278 op = new_ir_op(cur_opcode + iro_ia32_IncMem, "ia32_IncMem", op_pin_state_exc_pinned, irop_flag_none, oparity_trinary, 0, sizeof(ia32_attr_t)); 10279 op->ops.be_ops = be_ops; 10280 op->ops.dump_node = ia32_dump_node; 10281 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10282 op->ops.copy_attr = ia32_copy_attr; 10283 set_op_tag(op, ia32_op_tag); 10284 ia32_init_op(op, 1); 10285 op_ia32_IncMem = op; 10286 op = new_ir_op(cur_opcode + iro_ia32_xAllOnes, "ia32_xAllOnes", op_pin_state_floats, irop_flag_none, oparity_zero, 0, sizeof(ia32_attr_t)); 10287 op->ops.be_ops = be_ops; 10288 op->ops.dump_node = ia32_dump_node; 10289 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10290 op->ops.copy_attr = ia32_copy_attr; 10291 set_op_tag(op, ia32_op_tag); 10292 ia32_init_op(op, 3); 10293 op_ia32_xAllOnes = op; 10294 op = new_ir_op(cur_opcode + iro_ia32_Breakpoint, "ia32_Breakpoint", op_pin_state_pinned, irop_flag_none, oparity_unary, 0, sizeof(ia32_attr_t)); 10295 op->ops.be_ops = be_ops; 10296 op->ops.dump_node = ia32_dump_node; 10297 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10298 op->ops.copy_attr = ia32_copy_attr; 10299 set_op_tag(op, ia32_op_tag); 10300 ia32_init_op(op, 0); 10301 op_ia32_Breakpoint = op; 10302 op = new_ir_op(cur_opcode + iro_ia32_ClimbFrame, "ia32_ClimbFrame", op_pin_state_floats, irop_flag_none, oparity_trinary, 0, sizeof(ia32_climbframe_attr_t)); 10303 op->ops.be_ops = be_ops; 10304 op->ops.dump_node = ia32_dump_node; 10305 op->ops.node_cmp_attr = ia32_compare_climbframe_attr; 10306 op->ops.copy_attr = ia32_copy_attr; 10307 set_op_tag(op, ia32_op_tag); 10308 ia32_init_op(op, 4); 10309 op_ia32_ClimbFrame = op; 10310 op = new_ir_op(cur_opcode + iro_ia32_ffreep, "ia32_ffreep", op_pin_state_floats, irop_flag_keep, oparity_zero, 0, sizeof(ia32_x87_attr_t)); 10311 op->ops.be_ops = be_ops; 10312 op->ops.dump_node = ia32_dump_node; 10313 op->ops.node_cmp_attr = cmp_attr_ia32_ffreep; 10314 op->ops.copy_attr = ia32_copy_attr; 10315 set_op_tag(op, ia32_op_tag); 10316 ia32_init_op(op, 1); 10317 op_ia32_ffreep = op; 10318 op = new_ir_op(cur_opcode + iro_ia32_SubMem, "ia32_SubMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10319 op->ops.be_ops = be_ops; 10320 op->ops.dump_node = ia32_dump_node; 10321 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10322 op->ops.copy_attr = ia32_copy_attr; 10323 set_op_tag(op, ia32_op_tag); 10324 ia32_init_op(op, 1); 10325 op_ia32_SubMem = op; 10326 op = new_ir_op(cur_opcode + iro_ia32_AddMem, "ia32_AddMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10327 op->ops.be_ops = be_ops; 10328 op->ops.dump_node = ia32_dump_node; 10329 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10330 op->ops.copy_attr = ia32_copy_attr; 10331 set_op_tag(op, ia32_op_tag); 10332 ia32_init_op(op, 1); 10333 op_ia32_AddMem = op; 10334 op = new_ir_op(cur_opcode + iro_ia32_ShlMem, "ia32_ShlMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10335 op->ops.be_ops = be_ops; 10336 op->ops.dump_node = ia32_dump_node; 10337 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10338 op->ops.copy_attr = ia32_copy_attr; 10339 set_op_tag(op, ia32_op_tag); 10340 ia32_init_op(op, 1); 10341 op_ia32_ShlMem = op; 10342 op = new_ir_op(cur_opcode + iro_ia32_fdiv, "ia32_fdiv", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_x87_attr_t)); 10343 op->ops.be_ops = be_ops; 10344 op->ops.dump_node = ia32_dump_node; 10345 op->ops.node_cmp_attr = ia32_compare_x87_attr; 10346 op->ops.copy_attr = ia32_copy_attr; 10347 set_op_tag(op, ia32_op_tag); 10348 ia32_init_op(op, 20); 10349 op_ia32_fdiv = op; 10350 op = new_ir_op(cur_opcode + iro_ia32_Outport, "ia32_Outport", op_pin_state_pinned, irop_flag_none, oparity_trinary, 0, sizeof(ia32_attr_t)); 10351 op->ops.be_ops = be_ops; 10352 op->ops.dump_node = ia32_dump_node; 10353 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10354 op->ops.copy_attr = ia32_copy_attr; 10355 set_op_tag(op, ia32_op_tag); 10356 ia32_init_op(op, 1); 10357 op_ia32_Outport = op; 10358 op = new_ir_op(cur_opcode + iro_ia32_xMin, "ia32_xMin", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10359 op->ops.be_ops = be_ops; 10360 op->ops.dump_node = ia32_dump_node; 10361 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10362 op->ops.copy_attr = ia32_copy_attr; 10363 set_op_tag(op, ia32_op_tag); 10364 ia32_init_op(op, 2); 10365 op_ia32_xMin = op; 10366 op = new_ir_op(cur_opcode + iro_ia32_fist, "ia32_fist", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_any, 0, sizeof(ia32_x87_attr_t)); 10367 op->ops.be_ops = be_ops; 10368 op->ops.dump_node = ia32_dump_node; 10369 op->ops.node_cmp_attr = ia32_compare_x87_attr; 10370 op->ops.copy_attr = ia32_copy_attr; 10371 ir_op_set_memory_index(op, n_ia32_fist_mem); 10372 ir_op_set_fragile_indices(op, pn_ia32_fist_X_regular, pn_ia32_fist_X_except); 10373 set_op_tag(op, ia32_op_tag); 10374 ia32_init_op(op, 4); 10375 op_ia32_fist = op; 10376 op = new_ir_op(cur_opcode + iro_ia32_xXor, "ia32_xXor", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10377 op->ops.be_ops = be_ops; 10378 op->ops.dump_node = ia32_dump_node; 10379 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10380 op->ops.copy_attr = ia32_copy_attr; 10381 set_op_tag(op, ia32_op_tag); 10382 ia32_init_op(op, 3); 10383 op_ia32_xXor = op; 10384 op = new_ir_op(cur_opcode + iro_ia32_IJmp, "ia32_IJmp", op_pin_state_pinned, irop_flag_cfopcode|irop_flag_unknown_jump, oparity_any, 0, sizeof(ia32_attr_t)); 10385 op->ops.be_ops = be_ops; 10386 op->ops.dump_node = ia32_dump_node; 10387 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10388 op->ops.copy_attr = ia32_copy_attr; 10389 set_op_tag(op, ia32_op_tag); 10390 ia32_init_op(op, 1); 10391 op_ia32_IJmp = op; 10392 op = new_ir_op(cur_opcode + iro_ia32_NegMem, "ia32_NegMem", op_pin_state_exc_pinned, irop_flag_none, oparity_trinary, 0, sizeof(ia32_attr_t)); 10393 op->ops.be_ops = be_ops; 10394 op->ops.dump_node = ia32_dump_node; 10395 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10396 op->ops.copy_attr = ia32_copy_attr; 10397 set_op_tag(op, ia32_op_tag); 10398 ia32_init_op(op, 1); 10399 op_ia32_NegMem = op; 10400 op = new_ir_op(cur_opcode + iro_ia32_CMovcc, "ia32_CMovcc", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_condcode_attr_t)); 10401 op->ops.be_ops = be_ops; 10402 op->ops.dump_node = ia32_dump_node; 10403 op->ops.node_cmp_attr = ia32_compare_condcode_attr; 10404 op->ops.copy_attr = ia32_copy_attr; 10405 set_op_tag(op, ia32_op_tag); 10406 ia32_init_op(op, 1); 10407 op_ia32_CMovcc = op; 10408 op = new_ir_op(cur_opcode + iro_ia32_Mul, "ia32_Mul", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10409 op->ops.be_ops = be_ops; 10410 op->ops.dump_node = ia32_dump_node; 10411 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10412 op->ops.copy_attr = ia32_copy_attr; 10413 set_op_tag(op, ia32_op_tag); 10414 ia32_init_op(op, 10); 10415 op_ia32_Mul = op; 10416 op = new_ir_op(cur_opcode + iro_ia32_Sahf, "ia32_Sahf", op_pin_state_floats, irop_flag_none, oparity_unary, 0, sizeof(ia32_attr_t)); 10417 op->ops.be_ops = be_ops; 10418 op->ops.dump_node = ia32_dump_node; 10419 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10420 op->ops.copy_attr = ia32_copy_attr; 10421 set_op_tag(op, ia32_op_tag); 10422 ia32_init_op(op, 1); 10423 op_ia32_Sahf = op; 10424 op = new_ir_op(cur_opcode + iro_ia32_SubMem8Bit, "ia32_SubMem8Bit", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10425 op->ops.be_ops = be_ops; 10426 op->ops.dump_node = ia32_dump_node; 10427 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10428 op->ops.copy_attr = ia32_copy_attr; 10429 set_op_tag(op, ia32_op_tag); 10430 ia32_init_op(op, 1); 10431 op_ia32_SubMem8Bit = op; 10432 op = new_ir_op(cur_opcode + iro_ia32_AddMem8Bit, "ia32_AddMem8Bit", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10433 op->ops.be_ops = be_ops; 10434 op->ops.dump_node = ia32_dump_node; 10435 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10436 op->ops.copy_attr = ia32_copy_attr; 10437 set_op_tag(op, ia32_op_tag); 10438 ia32_init_op(op, 1); 10439 op_ia32_AddMem8Bit = op; 10440 op = new_ir_op(cur_opcode + iro_ia32_fst, "ia32_fst", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_any, 0, sizeof(ia32_x87_attr_t)); 10441 op->ops.be_ops = be_ops; 10442 op->ops.dump_node = ia32_dump_node; 10443 op->ops.node_cmp_attr = ia32_compare_x87_attr; 10444 op->ops.copy_attr = ia32_copy_attr; 10445 ir_op_set_memory_index(op, n_ia32_fst_mem); 10446 ir_op_set_fragile_indices(op, pn_ia32_fst_X_regular, pn_ia32_fst_X_except); 10447 set_op_tag(op, ia32_op_tag); 10448 ia32_init_op(op, 2); 10449 op_ia32_fst = op; 10450 op = new_ir_op(cur_opcode + iro_ia32_FucomppFnstsw, "ia32_FucomppFnstsw", op_pin_state_floats, irop_flag_none, oparity_binary, 0, sizeof(ia32_x87_attr_t)); 10451 op->ops.be_ops = be_ops; 10452 op->ops.dump_node = ia32_dump_node; 10453 op->ops.node_cmp_attr = ia32_compare_x87_attr; 10454 op->ops.copy_attr = ia32_copy_attr; 10455 set_op_tag(op, ia32_op_tag); 10456 ia32_init_op(op, 3); 10457 op_ia32_FucomppFnstsw = op; 10458 op = new_ir_op(cur_opcode + iro_ia32_RorMem, "ia32_RorMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10459 op->ops.be_ops = be_ops; 10460 op->ops.dump_node = ia32_dump_node; 10461 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10462 op->ops.copy_attr = ia32_copy_attr; 10463 set_op_tag(op, ia32_op_tag); 10464 ia32_init_op(op, 1); 10465 op_ia32_RorMem = op; 10466 op = new_ir_op(cur_opcode + iro_ia32_fpush, "ia32_fpush", op_pin_state_floats, irop_flag_keep, oparity_zero, 0, sizeof(ia32_x87_attr_t)); 10467 op->ops.be_ops = be_ops; 10468 op->ops.dump_node = ia32_dump_node; 10469 op->ops.node_cmp_attr = cmp_attr_ia32_fpush; 10470 op->ops.copy_attr = ia32_copy_attr; 10471 set_op_tag(op, ia32_op_tag); 10472 ia32_init_op(op, 1); 10473 op_ia32_fpush = op; 10474 op = new_ir_op(cur_opcode + iro_ia32_fild, "ia32_fild", op_pin_state_exc_pinned, irop_flag_none, oparity_trinary, 0, sizeof(ia32_x87_attr_t)); 10475 op->ops.be_ops = be_ops; 10476 op->ops.dump_node = ia32_dump_node; 10477 op->ops.node_cmp_attr = ia32_compare_x87_attr; 10478 op->ops.copy_attr = ia32_copy_attr; 10479 set_op_tag(op, ia32_op_tag); 10480 ia32_init_op(op, 4); 10481 op_ia32_fild = op; 10482 op = new_ir_op(cur_opcode + iro_ia32_xOr, "ia32_xOr", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10483 op->ops.be_ops = be_ops; 10484 op->ops.dump_node = ia32_dump_node; 10485 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10486 op->ops.copy_attr = ia32_copy_attr; 10487 set_op_tag(op, ia32_op_tag); 10488 ia32_init_op(op, 3); 10489 op_ia32_xOr = op; 10490 op = new_ir_op(cur_opcode + iro_ia32_Conv_I2I8Bit, "ia32_Conv_I2I8Bit", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_any, 0, sizeof(ia32_attr_t)); 10491 op->ops.be_ops = be_ops; 10492 op->ops.dump_node = ia32_dump_node; 10493 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10494 op->ops.copy_attr = ia32_copy_attr; 10495 ir_op_set_memory_index(op, n_ia32_Conv_I2I8Bit_mem); 10496 ir_op_set_fragile_indices(op, pn_ia32_Conv_I2I8Bit_X_regular, pn_ia32_Conv_I2I8Bit_X_except); 10497 set_op_tag(op, ia32_op_tag); 10498 ia32_init_op(op, 1); 10499 op_ia32_Conv_I2I8Bit = op; 10500 op = new_ir_op(cur_opcode + iro_ia32_Store, "ia32_Store", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_any, 0, sizeof(ia32_attr_t)); 10501 op->ops.be_ops = be_ops; 10502 op->ops.dump_node = ia32_dump_node; 10503 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10504 op->ops.copy_attr = ia32_copy_attr; 10505 ir_op_set_memory_index(op, n_ia32_Store_mem); 10506 ir_op_set_fragile_indices(op, pn_ia32_Store_X_regular, pn_ia32_Store_X_except); 10507 set_op_tag(op, ia32_op_tag); 10508 ia32_init_op(op, 2); 10509 op_ia32_Store = op; 10510 op = new_ir_op(cur_opcode + iro_ia32_fldln2, "ia32_fldln2", op_pin_state_floats, irop_flag_none, oparity_zero, 0, sizeof(ia32_x87_attr_t)); 10511 op->ops.be_ops = be_ops; 10512 op->ops.dump_node = ia32_dump_node; 10513 op->ops.node_cmp_attr = ia32_compare_x87_attr; 10514 op->ops.copy_attr = ia32_copy_attr; 10515 set_op_tag(op, ia32_op_tag); 10516 ia32_init_op(op, 4); 10517 op_ia32_fldln2 = op; 10518 op = new_ir_op(cur_opcode + iro_ia32_SwitchJmp, "ia32_SwitchJmp", op_pin_state_pinned, irop_flag_cfopcode|irop_flag_forking, oparity_binary, 0, sizeof(ia32_switch_attr_t)); 10519 op->ops.be_ops = be_ops; 10520 op->ops.dump_node = ia32_dump_node; 10521 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10522 op->ops.copy_attr = ia32_copy_attr; 10523 set_op_tag(op, ia32_op_tag); 10524 ia32_init_op(op, 2); 10525 op_ia32_SwitchJmp = op; 10526 op = new_ir_op(cur_opcode + iro_ia32_IMul, "ia32_IMul", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10527 op->ops.be_ops = be_ops; 10528 op->ops.dump_node = ia32_dump_node; 10529 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10530 op->ops.copy_attr = ia32_copy_attr; 10531 set_op_tag(op, ia32_op_tag); 10532 ia32_init_op(op, 5); 10533 op_ia32_IMul = op; 10534 op = new_ir_op(cur_opcode + iro_ia32_Ucomi, "ia32_Ucomi", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10535 op->ops.be_ops = be_ops; 10536 op->ops.dump_node = ia32_dump_node; 10537 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10538 op->ops.copy_attr = ia32_copy_attr; 10539 set_op_tag(op, ia32_op_tag); 10540 ia32_init_op(op, 3); 10541 op_ia32_Ucomi = op; 10542 op = new_ir_op(cur_opcode + iro_ia32_fldz, "ia32_fldz", op_pin_state_floats, irop_flag_none, oparity_zero, 0, sizeof(ia32_x87_attr_t)); 10543 op->ops.be_ops = be_ops; 10544 op->ops.dump_node = ia32_dump_node; 10545 op->ops.node_cmp_attr = ia32_compare_x87_attr; 10546 op->ops.copy_attr = ia32_copy_attr; 10547 set_op_tag(op, ia32_op_tag); 10548 ia32_init_op(op, 4); 10549 op_ia32_fldz = op; 10550 op = new_ir_op(cur_opcode + iro_ia32_Store8Bit, "ia32_Store8Bit", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_any, 0, sizeof(ia32_attr_t)); 10551 op->ops.be_ops = be_ops; 10552 op->ops.dump_node = ia32_dump_node; 10553 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10554 op->ops.copy_attr = ia32_copy_attr; 10555 ir_op_set_memory_index(op, n_ia32_Store8Bit_mem); 10556 ir_op_set_fragile_indices(op, pn_ia32_Store8Bit_X_regular, pn_ia32_Store8Bit_X_except); 10557 set_op_tag(op, ia32_op_tag); 10558 ia32_init_op(op, 2); 10559 op_ia32_Store8Bit = op; 10560 op = new_ir_op(cur_opcode + iro_ia32_fpop, "ia32_fpop", op_pin_state_floats, irop_flag_keep, oparity_zero, 0, sizeof(ia32_x87_attr_t)); 10561 op->ops.be_ops = be_ops; 10562 op->ops.dump_node = ia32_dump_node; 10563 op->ops.node_cmp_attr = cmp_attr_ia32_fpop; 10564 op->ops.copy_attr = ia32_copy_attr; 10565 set_op_tag(op, ia32_op_tag); 10566 ia32_init_op(op, 1); 10567 op_ia32_fpop = op; 10568 op = new_ir_op(cur_opcode + iro_ia32_l_Sub, "ia32_l_Sub", op_pin_state_floats, irop_flag_none, oparity_binary, 0, 0); 10569 op->ops.be_ops = be_ops; 10570 op->ops.dump_node = NULL; 10571 op->ops.node_cmp_attr = NULL; 10572 set_op_tag(op, ia32_op_tag); 10573 ia32_init_op(op, 0); 10574 op_ia32_l_Sub = op; 10575 op = new_ir_op(cur_opcode + iro_ia32_Sbb, "ia32_Sbb", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10576 op->ops.be_ops = be_ops; 10577 op->ops.dump_node = ia32_dump_node; 10578 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10579 op->ops.copy_attr = ia32_copy_attr; 10580 set_op_tag(op, ia32_op_tag); 10581 ia32_init_op(op, 1); 10582 op_ia32_Sbb = op; 10583 op = new_ir_op(cur_opcode + iro_ia32_FucomFnstsw, "ia32_FucomFnstsw", op_pin_state_floats, irop_flag_none, oparity_binary, 0, sizeof(ia32_x87_attr_t)); 10584 op->ops.be_ops = be_ops; 10585 op->ops.dump_node = ia32_dump_node; 10586 op->ops.node_cmp_attr = ia32_compare_x87_attr; 10587 op->ops.copy_attr = ia32_copy_attr; 10588 set_op_tag(op, ia32_op_tag); 10589 ia32_init_op(op, 3); 10590 op_ia32_FucomFnstsw = op; 10591 op = new_ir_op(cur_opcode + iro_ia32_xMul, "ia32_xMul", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10592 op->ops.be_ops = be_ops; 10593 op->ops.dump_node = ia32_dump_node; 10594 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10595 op->ops.copy_attr = ia32_copy_attr; 10596 set_op_tag(op, ia32_op_tag); 10597 ia32_init_op(op, 4); 10598 op_ia32_xMul = op; 10599 op = new_ir_op(cur_opcode + iro_ia32_Push, "ia32_Push", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10600 op->ops.be_ops = be_ops; 10601 op->ops.dump_node = ia32_dump_node; 10602 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10603 op->ops.copy_attr = ia32_copy_attr; 10604 set_op_tag(op, ia32_op_tag); 10605 ia32_init_op(op, 2); 10606 op_ia32_Push = op; 10607 op = new_ir_op(cur_opcode + iro_ia32_xPslld, "ia32_xPslld", op_pin_state_floats, irop_flag_none, oparity_binary, 0, sizeof(ia32_attr_t)); 10608 op->ops.be_ops = be_ops; 10609 op->ops.dump_node = ia32_dump_node; 10610 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10611 op->ops.copy_attr = ia32_copy_attr; 10612 set_op_tag(op, ia32_op_tag); 10613 ia32_init_op(op, 3); 10614 op_ia32_xPslld = op; 10615 op = new_ir_op(cur_opcode + iro_ia32_Cmp, "ia32_Cmp", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10616 op->ops.be_ops = be_ops; 10617 op->ops.dump_node = ia32_dump_node; 10618 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10619 op->ops.copy_attr = ia32_copy_attr; 10620 set_op_tag(op, ia32_op_tag); 10621 ia32_init_op(op, 1); 10622 op_ia32_Cmp = op; 10623 op = new_ir_op(cur_opcode + iro_ia32_xSub, "ia32_xSub", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10624 op->ops.be_ops = be_ops; 10625 op->ops.dump_node = ia32_dump_node; 10626 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10627 op->ops.copy_attr = ia32_copy_attr; 10628 set_op_tag(op, ia32_op_tag); 10629 ia32_init_op(op, 4); 10630 op_ia32_xSub = op; 10631 op = new_ir_op(cur_opcode + iro_ia32_xMovd, "ia32_xMovd", op_pin_state_floats, irop_flag_none, oparity_unary, 0, sizeof(ia32_attr_t)); 10632 op->ops.be_ops = be_ops; 10633 op->ops.dump_node = ia32_dump_node; 10634 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10635 op->ops.copy_attr = ia32_copy_attr; 10636 set_op_tag(op, ia32_op_tag); 10637 ia32_init_op(op, 1); 10638 op_ia32_xMovd = op; 10639 op = new_ir_op(cur_opcode + iro_ia32_Cltd, "ia32_Cltd", op_pin_state_floats, irop_flag_none, oparity_binary, 0, sizeof(ia32_attr_t)); 10640 op->ops.be_ops = be_ops; 10641 op->ops.dump_node = ia32_dump_node; 10642 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10643 op->ops.copy_attr = ia32_copy_attr; 10644 set_op_tag(op, ia32_op_tag); 10645 ia32_init_op(op, 1); 10646 op_ia32_Cltd = op; 10647 op = new_ir_op(cur_opcode + iro_ia32_xPsrld, "ia32_xPsrld", op_pin_state_floats, irop_flag_none, oparity_binary, 0, sizeof(ia32_attr_t)); 10648 op->ops.be_ops = be_ops; 10649 op->ops.dump_node = ia32_dump_node; 10650 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10651 op->ops.copy_attr = ia32_copy_attr; 10652 set_op_tag(op, ia32_op_tag); 10653 ia32_init_op(op, 1); 10654 op_ia32_xPsrld = op; 10655 op = new_ir_op(cur_opcode + iro_ia32_PushEax, "ia32_PushEax", op_pin_state_exc_pinned, irop_flag_none, oparity_unary, 0, sizeof(ia32_attr_t)); 10656 op->ops.be_ops = be_ops; 10657 op->ops.dump_node = ia32_dump_node; 10658 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10659 op->ops.copy_attr = ia32_copy_attr; 10660 set_op_tag(op, ia32_op_tag); 10661 ia32_init_op(op, 2); 10662 op_ia32_PushEax = op; 10663 op = new_ir_op(cur_opcode + iro_ia32_XorHighLow, "ia32_XorHighLow", op_pin_state_exc_pinned, irop_flag_none, oparity_unary, 0, sizeof(ia32_attr_t)); 10664 op->ops.be_ops = be_ops; 10665 op->ops.dump_node = ia32_dump_node; 10666 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10667 op->ops.copy_attr = ia32_copy_attr; 10668 set_op_tag(op, ia32_op_tag); 10669 ia32_init_op(op, 1); 10670 op_ia32_XorHighLow = op; 10671 op = new_ir_op(cur_opcode + iro_ia32_xPzero, "ia32_xPzero", op_pin_state_floats, irop_flag_none, oparity_zero, 0, sizeof(ia32_attr_t)); 10672 op->ops.be_ops = be_ops; 10673 op->ops.dump_node = ia32_dump_node; 10674 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10675 op->ops.copy_attr = ia32_copy_attr; 10676 set_op_tag(op, ia32_op_tag); 10677 ia32_init_op(op, 3); 10678 op_ia32_xPzero = op; 10679 op = new_ir_op(cur_opcode + iro_ia32_Rol, "ia32_Rol", op_pin_state_floats, irop_flag_none, oparity_binary, 0, sizeof(ia32_attr_t)); 10680 op->ops.be_ops = be_ops; 10681 op->ops.dump_node = ia32_dump_node; 10682 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10683 op->ops.copy_attr = ia32_copy_attr; 10684 set_op_tag(op, ia32_op_tag); 10685 ia32_init_op(op, 1); 10686 op_ia32_Rol = op; 10687 op = new_ir_op(cur_opcode + iro_ia32_Cmc, "ia32_Cmc", op_pin_state_floats, irop_flag_none, oparity_unary, 0, sizeof(ia32_attr_t)); 10688 op->ops.be_ops = be_ops; 10689 op->ops.dump_node = ia32_dump_node; 10690 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10691 op->ops.copy_attr = ia32_copy_attr; 10692 set_op_tag(op, ia32_op_tag); 10693 ia32_init_op(op, 1); 10694 op_ia32_Cmc = op; 10695 op = new_ir_op(cur_opcode + iro_ia32_Cmp8Bit, "ia32_Cmp8Bit", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10696 op->ops.be_ops = be_ops; 10697 op->ops.dump_node = ia32_dump_node; 10698 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10699 op->ops.copy_attr = ia32_copy_attr; 10700 set_op_tag(op, ia32_op_tag); 10701 ia32_init_op(op, 1); 10702 op_ia32_Cmp8Bit = op; 10703 op = new_ir_op(cur_opcode + iro_ia32_xDiv, "ia32_xDiv", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10704 op->ops.be_ops = be_ops; 10705 op->ops.dump_node = ia32_dump_node; 10706 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10707 op->ops.copy_attr = ia32_copy_attr; 10708 set_op_tag(op, ia32_op_tag); 10709 ia32_init_op(op, 16); 10710 op_ia32_xDiv = op; 10711 op = new_ir_op(cur_opcode + iro_ia32_xUnknown, "ia32_xUnknown", op_pin_state_floats, irop_flag_constlike, oparity_zero, 0, sizeof(ia32_attr_t)); 10712 op->ops.be_ops = be_ops; 10713 op->ops.dump_node = ia32_dump_node; 10714 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10715 op->ops.copy_attr = ia32_copy_attr; 10716 set_op_tag(op, ia32_op_tag); 10717 ia32_init_op(op, 0); 10718 op_ia32_xUnknown = op; 10719 op = new_ir_op(cur_opcode + iro_ia32_Test8Bit, "ia32_Test8Bit", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10720 op->ops.be_ops = be_ops; 10721 op->ops.dump_node = ia32_dump_node; 10722 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10723 op->ops.copy_attr = ia32_copy_attr; 10724 set_op_tag(op, ia32_op_tag); 10725 ia32_init_op(op, 1); 10726 op_ia32_Test8Bit = op; 10727 op = new_ir_op(cur_opcode + iro_ia32_Sub, "ia32_Sub", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10728 op->ops.be_ops = be_ops; 10729 op->ops.dump_node = ia32_dump_node; 10730 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10731 op->ops.copy_attr = ia32_copy_attr; 10732 set_op_tag(op, ia32_op_tag); 10733 ia32_init_op(op, 1); 10734 op_ia32_Sub = op; 10735 op = new_ir_op(cur_opcode + iro_ia32_PrefetchNTA, "ia32_PrefetchNTA", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_trinary, 0, sizeof(ia32_attr_t)); 10736 op->ops.be_ops = be_ops; 10737 op->ops.dump_node = ia32_dump_node; 10738 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10739 op->ops.copy_attr = ia32_copy_attr; 10740 set_op_tag(op, ia32_op_tag); 10741 ia32_init_op(op, 0); 10742 op_ia32_PrefetchNTA = op; 10743 op = new_ir_op(cur_opcode + iro_ia32_Shr, "ia32_Shr", op_pin_state_floats, irop_flag_none, oparity_binary, 0, sizeof(ia32_attr_t)); 10744 op->ops.be_ops = be_ops; 10745 op->ops.dump_node = ia32_dump_node; 10746 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10747 op->ops.copy_attr = ia32_copy_attr; 10748 set_op_tag(op, ia32_op_tag); 10749 ia32_init_op(op, 1); 10750 op_ia32_Shr = op; 10751 op = new_ir_op(cur_opcode + iro_ia32_fprem, "ia32_fprem", op_pin_state_floats, irop_flag_none, oparity_trinary, 0, sizeof(ia32_x87_attr_t)); 10752 op->ops.be_ops = be_ops; 10753 op->ops.dump_node = ia32_dump_node; 10754 op->ops.node_cmp_attr = ia32_compare_x87_attr; 10755 op->ops.copy_attr = ia32_copy_attr; 10756 set_op_tag(op, ia32_op_tag); 10757 ia32_init_op(op, 20); 10758 op_ia32_fprem = op; 10759 op = new_ir_op(cur_opcode + iro_ia32_IDiv, "ia32_IDiv", op_pin_state_exc_pinned, irop_flag_fragile|irop_flag_uses_memory, oparity_any, 0, sizeof(ia32_attr_t)); 10760 op->ops.be_ops = be_ops; 10761 op->ops.dump_node = ia32_dump_node; 10762 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10763 op->ops.copy_attr = ia32_copy_attr; 10764 ir_op_set_memory_index(op, n_ia32_IDiv_mem); 10765 ir_op_set_fragile_indices(op, pn_ia32_IDiv_X_regular, pn_ia32_IDiv_X_except); 10766 set_op_tag(op, ia32_op_tag); 10767 ia32_init_op(op, 25); 10768 op_ia32_IDiv = op; 10769 op = new_ir_op(cur_opcode + iro_ia32_l_Adc, "ia32_l_Adc", op_pin_state_floats, irop_flag_none, oparity_trinary, 0, 0); 10770 op->ops.be_ops = be_ops; 10771 op->ops.dump_node = NULL; 10772 op->ops.node_cmp_attr = NULL; 10773 set_op_tag(op, ia32_op_tag); 10774 ia32_init_op(op, 0); 10775 op_ia32_l_Adc = op; 10776 op = new_ir_op(cur_opcode + iro_ia32_Setcc, "ia32_Setcc", op_pin_state_floats, irop_flag_none, oparity_unary, 0, sizeof(ia32_condcode_attr_t)); 10777 op->ops.be_ops = be_ops; 10778 op->ops.dump_node = ia32_dump_node; 10779 op->ops.node_cmp_attr = ia32_compare_condcode_attr; 10780 op->ops.copy_attr = ia32_copy_attr; 10781 set_op_tag(op, ia32_op_tag); 10782 ia32_init_op(op, 1); 10783 op_ia32_Setcc = op; 10784 op = new_ir_op(cur_opcode + iro_ia32_l_LLtoFloat, "ia32_l_LLtoFloat", op_pin_state_floats, irop_flag_none, oparity_binary, 0, 0); 10785 op->ops.be_ops = be_ops; 10786 op->ops.dump_node = NULL; 10787 op->ops.node_cmp_attr = NULL; 10788 set_op_tag(op, ia32_op_tag); 10789 ia32_init_op(op, 0); 10790 op_ia32_l_LLtoFloat = op; 10791 op = new_ir_op(cur_opcode + iro_ia32_ProduceVal, "ia32_ProduceVal", op_pin_state_floats, irop_flag_constlike|irop_flag_cse_neutral, oparity_zero, 0, sizeof(ia32_attr_t)); 10792 op->ops.be_ops = be_ops; 10793 op->ops.dump_node = ia32_dump_node; 10794 op->ops.node_cmp_attr = cmp_attr_ia32_ProduceVal; 10795 op->ops.copy_attr = ia32_copy_attr; 10796 set_op_tag(op, ia32_op_tag); 10797 ia32_init_op(op, 0); 10798 op_ia32_ProduceVal = op; 10799 op = new_ir_op(cur_opcode + iro_ia32_Bswap, "ia32_Bswap", op_pin_state_floats, irop_flag_none, oparity_unary, 0, sizeof(ia32_attr_t)); 10800 op->ops.be_ops = be_ops; 10801 op->ops.dump_node = ia32_dump_node; 10802 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10803 op->ops.copy_attr = ia32_copy_attr; 10804 set_op_tag(op, ia32_op_tag); 10805 ia32_init_op(op, 1); 10806 op_ia32_Bswap = op; 10807 op = new_ir_op(cur_opcode + iro_ia32_SetccMem, "ia32_SetccMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_condcode_attr_t)); 10808 op->ops.be_ops = be_ops; 10809 op->ops.dump_node = ia32_dump_node; 10810 op->ops.node_cmp_attr = ia32_compare_condcode_attr; 10811 op->ops.copy_attr = ia32_copy_attr; 10812 set_op_tag(op, ia32_op_tag); 10813 ia32_init_op(op, 1); 10814 op_ia32_SetccMem = op; 10815 op = new_ir_op(cur_opcode + iro_ia32_Test, "ia32_Test", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10816 op->ops.be_ops = be_ops; 10817 op->ops.dump_node = ia32_dump_node; 10818 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10819 op->ops.copy_attr = ia32_copy_attr; 10820 set_op_tag(op, ia32_op_tag); 10821 ia32_init_op(op, 1); 10822 op_ia32_Test = op; 10823 op = new_ir_op(cur_opcode + iro_ia32_l_Add, "ia32_l_Add", op_pin_state_floats, irop_flag_none, oparity_binary, 0, 0); 10824 op->ops.be_ops = be_ops; 10825 op->ops.dump_node = NULL; 10826 op->ops.node_cmp_attr = NULL; 10827 set_op_tag(op, ia32_op_tag); 10828 ia32_init_op(op, 0); 10829 op_ia32_l_Add = op; 10830 op = new_ir_op(cur_opcode + iro_ia32_AddSP, "ia32_AddSP", op_pin_state_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10831 op->ops.be_ops = be_ops; 10832 op->ops.dump_node = ia32_dump_node; 10833 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10834 op->ops.copy_attr = ia32_copy_attr; 10835 set_op_tag(op, ia32_op_tag); 10836 ia32_init_op(op, 1); 10837 op_ia32_AddSP = op; 10838 op = new_ir_op(cur_opcode + iro_ia32_RolMem, "ia32_RolMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10839 op->ops.be_ops = be_ops; 10840 op->ops.dump_node = ia32_dump_node; 10841 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10842 op->ops.copy_attr = ia32_copy_attr; 10843 set_op_tag(op, ia32_op_tag); 10844 ia32_init_op(op, 1); 10845 op_ia32_RolMem = op; 10846 op = new_ir_op(cur_opcode + iro_ia32_Conv_I2FP, "ia32_Conv_I2FP", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10847 op->ops.be_ops = be_ops; 10848 op->ops.dump_node = ia32_dump_node; 10849 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10850 op->ops.copy_attr = ia32_copy_attr; 10851 set_op_tag(op, ia32_op_tag); 10852 ia32_init_op(op, 10); 10853 op_ia32_Conv_I2FP = op; 10854 op = new_ir_op(cur_opcode + iro_ia32_Conv_FP2FP, "ia32_Conv_FP2FP", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10855 op->ops.be_ops = be_ops; 10856 op->ops.dump_node = ia32_dump_node; 10857 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10858 op->ops.copy_attr = ia32_copy_attr; 10859 set_op_tag(op, ia32_op_tag); 10860 ia32_init_op(op, 8); 10861 op_ia32_Conv_FP2FP = op; 10862 op = new_ir_op(cur_opcode + iro_ia32_ChangeCW, "ia32_ChangeCW", op_pin_state_pinned, irop_flag_constlike, oparity_zero, 0, sizeof(ia32_attr_t)); 10863 op->ops.be_ops = be_ops; 10864 op->ops.dump_node = ia32_dump_node; 10865 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10866 op->ops.copy_attr = ia32_copy_attr; 10867 set_op_tag(op, ia32_op_tag); 10868 ia32_init_op(op, 3); 10869 op_ia32_ChangeCW = op; 10870 op = new_ir_op(cur_opcode + iro_ia32_Prefetch2, "ia32_Prefetch2", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_trinary, 0, sizeof(ia32_attr_t)); 10871 op->ops.be_ops = be_ops; 10872 op->ops.dump_node = ia32_dump_node; 10873 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10874 op->ops.copy_attr = ia32_copy_attr; 10875 set_op_tag(op, ia32_op_tag); 10876 ia32_init_op(op, 0); 10877 op_ia32_Prefetch2 = op; 10878 op = new_ir_op(cur_opcode + iro_ia32_NoReg_GP, "ia32_NoReg_GP", op_pin_state_pinned, irop_flag_constlike|irop_flag_dump_noblock, oparity_zero, 0, sizeof(ia32_attr_t)); 10879 op->ops.be_ops = be_ops; 10880 op->ops.dump_node = ia32_dump_node; 10881 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10882 op->ops.copy_attr = ia32_copy_attr; 10883 set_op_tag(op, ia32_op_tag); 10884 ia32_init_op(op, 0); 10885 op_ia32_NoReg_GP = op; 10886 op = new_ir_op(cur_opcode + iro_ia32_Const, "ia32_Const", op_pin_state_floats, irop_flag_constlike, oparity_zero, 0, sizeof(ia32_immediate_attr_t)); 10887 op->ops.be_ops = be_ops; 10888 op->ops.dump_node = ia32_dump_node; 10889 op->ops.node_cmp_attr = ia32_compare_immediate_attr; 10890 op->ops.copy_attr = ia32_copy_attr; 10891 set_op_tag(op, ia32_op_tag); 10892 ia32_init_op(op, 1); 10893 op_ia32_Const = op; 10894 op = new_ir_op(cur_opcode + iro_ia32_Minus64Bit, "ia32_Minus64Bit", op_pin_state_floats, irop_flag_none, oparity_binary, 0, sizeof(ia32_attr_t)); 10895 op->ops.be_ops = be_ops; 10896 op->ops.dump_node = ia32_dump_node; 10897 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10898 op->ops.copy_attr = ia32_copy_attr; 10899 set_op_tag(op, ia32_op_tag); 10900 ia32_init_op(op, 3); 10901 op_ia32_Minus64Bit = op; 10902 op = new_ir_op(cur_opcode + iro_ia32_Jmp, "ia32_Jmp", op_pin_state_pinned, irop_flag_cfopcode, oparity_zero, 0, sizeof(ia32_attr_t)); 10903 op->ops.be_ops = be_ops; 10904 op->ops.dump_node = ia32_dump_node; 10905 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10906 op->ops.copy_attr = ia32_copy_attr; 10907 set_op_tag(op, ia32_op_tag); 10908 ia32_init_op(op, 1); 10909 op_ia32_Jmp = op; 10910 op = new_ir_op(cur_opcode + iro_ia32_FnstCW, "ia32_FnstCW", op_pin_state_pinned, irop_flag_uses_memory, oparity_any, 0, sizeof(ia32_attr_t)); 10911 op->ops.be_ops = be_ops; 10912 op->ops.dump_node = ia32_dump_node; 10913 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10914 op->ops.copy_attr = ia32_copy_attr; 10915 set_op_tag(op, ia32_op_tag); 10916 ia32_init_op(op, 5); 10917 op_ia32_FnstCW = op; 10918 op = new_ir_op(cur_opcode + iro_ia32_Prefetch0, "ia32_Prefetch0", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_trinary, 0, sizeof(ia32_attr_t)); 10919 op->ops.be_ops = be_ops; 10920 op->ops.dump_node = ia32_dump_node; 10921 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10922 op->ops.copy_attr = ia32_copy_attr; 10923 set_op_tag(op, ia32_op_tag); 10924 ia32_init_op(op, 0); 10925 op_ia32_Prefetch0 = op; 10926 op = new_ir_op(cur_opcode + iro_ia32_OrMem, "ia32_OrMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10927 op->ops.be_ops = be_ops; 10928 op->ops.dump_node = ia32_dump_node; 10929 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10930 op->ops.copy_attr = ia32_copy_attr; 10931 set_op_tag(op, ia32_op_tag); 10932 ia32_init_op(op, 1); 10933 op_ia32_OrMem = op; 10934 op = new_ir_op(cur_opcode + iro_ia32_fldlg2, "ia32_fldlg2", op_pin_state_floats, irop_flag_none, oparity_zero, 0, sizeof(ia32_x87_attr_t)); 10935 op->ops.be_ops = be_ops; 10936 op->ops.dump_node = ia32_dump_node; 10937 op->ops.node_cmp_attr = ia32_compare_x87_attr; 10938 op->ops.copy_attr = ia32_copy_attr; 10939 set_op_tag(op, ia32_op_tag); 10940 ia32_init_op(op, 4); 10941 op_ia32_fldlg2 = op; 10942 op = new_ir_op(cur_opcode + iro_ia32_fld1, "ia32_fld1", op_pin_state_floats, irop_flag_none, oparity_zero, 0, sizeof(ia32_x87_attr_t)); 10943 op->ops.be_ops = be_ops; 10944 op->ops.dump_node = ia32_dump_node; 10945 op->ops.node_cmp_attr = ia32_compare_x87_attr; 10946 op->ops.copy_attr = ia32_copy_attr; 10947 set_op_tag(op, ia32_op_tag); 10948 ia32_init_op(op, 4); 10949 op_ia32_fld1 = op; 10950 op = new_ir_op(cur_opcode + iro_ia32_Conv_FP2I, "ia32_Conv_FP2I", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10951 op->ops.be_ops = be_ops; 10952 op->ops.dump_node = ia32_dump_node; 10953 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10954 op->ops.copy_attr = ia32_copy_attr; 10955 set_op_tag(op, ia32_op_tag); 10956 ia32_init_op(op, 10); 10957 op_ia32_Conv_FP2I = op; 10958 op = new_ir_op(cur_opcode + iro_ia32_Popcnt, "ia32_Popcnt", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10959 op->ops.be_ops = be_ops; 10960 op->ops.dump_node = ia32_dump_node; 10961 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10962 op->ops.copy_attr = ia32_copy_attr; 10963 set_op_tag(op, ia32_op_tag); 10964 ia32_init_op(op, 1); 10965 op_ia32_Popcnt = op; 10966 op = new_ir_op(cur_opcode + iro_ia32_Ror, "ia32_Ror", op_pin_state_floats, irop_flag_none, oparity_binary, 0, sizeof(ia32_attr_t)); 10967 op->ops.be_ops = be_ops; 10968 op->ops.dump_node = ia32_dump_node; 10969 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10970 op->ops.copy_attr = ia32_copy_attr; 10971 set_op_tag(op, ia32_op_tag); 10972 ia32_init_op(op, 1); 10973 op_ia32_Ror = op; 10974 op = new_ir_op(cur_opcode + iro_ia32_Shl, "ia32_Shl", op_pin_state_floats, irop_flag_none, oparity_binary, 0, sizeof(ia32_attr_t)); 10975 op->ops.be_ops = be_ops; 10976 op->ops.dump_node = ia32_dump_node; 10977 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10978 op->ops.copy_attr = ia32_copy_attr; 10979 set_op_tag(op, ia32_op_tag); 10980 ia32_init_op(op, 1); 10981 op_ia32_Shl = op; 10982 op = new_ir_op(cur_opcode + iro_ia32_AndMem8Bit, "ia32_AndMem8Bit", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10983 op->ops.be_ops = be_ops; 10984 op->ops.dump_node = ia32_dump_node; 10985 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10986 op->ops.copy_attr = ia32_copy_attr; 10987 set_op_tag(op, ia32_op_tag); 10988 ia32_init_op(op, 1); 10989 op_ia32_AndMem8Bit = op; 10990 op = new_ir_op(cur_opcode + iro_ia32_Add, "ia32_Add", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10991 op->ops.be_ops = be_ops; 10992 op->ops.dump_node = ia32_dump_node; 10993 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 10994 op->ops.copy_attr = ia32_copy_attr; 10995 set_op_tag(op, ia32_op_tag); 10996 ia32_init_op(op, 1); 10997 op_ia32_Add = op; 10998 op = new_ir_op(cur_opcode + iro_ia32_SubSP, "ia32_SubSP", op_pin_state_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 10999 op->ops.be_ops = be_ops; 11000 op->ops.dump_node = ia32_dump_node; 11001 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11002 op->ops.copy_attr = ia32_copy_attr; 11003 set_op_tag(op, ia32_op_tag); 11004 ia32_init_op(op, 2); 11005 op_ia32_SubSP = op; 11006 op = new_ir_op(cur_opcode + iro_ia32_PrefetchW, "ia32_PrefetchW", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_trinary, 0, sizeof(ia32_attr_t)); 11007 op->ops.be_ops = be_ops; 11008 op->ops.dump_node = ia32_dump_node; 11009 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11010 op->ops.copy_attr = ia32_copy_attr; 11011 set_op_tag(op, ia32_op_tag); 11012 ia32_init_op(op, 0); 11013 op_ia32_PrefetchW = op; 11014 op = new_ir_op(cur_opcode + iro_ia32_Conv_I2I, "ia32_Conv_I2I", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_any, 0, sizeof(ia32_attr_t)); 11015 op->ops.be_ops = be_ops; 11016 op->ops.dump_node = ia32_dump_node; 11017 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11018 op->ops.copy_attr = ia32_copy_attr; 11019 ir_op_set_memory_index(op, n_ia32_Conv_I2I_mem); 11020 ir_op_set_fragile_indices(op, pn_ia32_Conv_I2I_X_regular, pn_ia32_Conv_I2I_X_except); 11021 set_op_tag(op, ia32_op_tag); 11022 ia32_init_op(op, 1); 11023 op_ia32_Conv_I2I = op; 11024 op = new_ir_op(cur_opcode + iro_ia32_fxch, "ia32_fxch", op_pin_state_floats, irop_flag_keep, oparity_zero, 0, sizeof(ia32_x87_attr_t)); 11025 op->ops.be_ops = be_ops; 11026 op->ops.dump_node = ia32_dump_node; 11027 op->ops.node_cmp_attr = cmp_attr_ia32_fxch; 11028 op->ops.copy_attr = ia32_copy_attr; 11029 set_op_tag(op, ia32_op_tag); 11030 ia32_init_op(op, 1); 11031 op_ia32_fxch = op; 11032 op = new_ir_op(cur_opcode + iro_ia32_fchs, "ia32_fchs", op_pin_state_floats, irop_flag_none, oparity_unary, 0, sizeof(ia32_x87_attr_t)); 11033 op->ops.be_ops = be_ops; 11034 op->ops.dump_node = ia32_dump_node; 11035 op->ops.node_cmp_attr = ia32_compare_x87_attr; 11036 op->ops.copy_attr = ia32_copy_attr; 11037 set_op_tag(op, ia32_op_tag); 11038 ia32_init_op(op, 2); 11039 op_ia32_fchs = op; 11040 op = new_ir_op(cur_opcode + iro_ia32_ShrD, "ia32_ShrD", op_pin_state_floats, irop_flag_none, oparity_trinary, 0, sizeof(ia32_attr_t)); 11041 op->ops.be_ops = be_ops; 11042 op->ops.dump_node = ia32_dump_node; 11043 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11044 op->ops.copy_attr = ia32_copy_attr; 11045 set_op_tag(op, ia32_op_tag); 11046 ia32_init_op(op, 6); 11047 op_ia32_ShrD = op; 11048 op = new_ir_op(cur_opcode + iro_ia32_Unknown, "ia32_Unknown", op_pin_state_floats, irop_flag_constlike, oparity_zero, 0, sizeof(ia32_attr_t)); 11049 op->ops.be_ops = be_ops; 11050 op->ops.dump_node = ia32_dump_node; 11051 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11052 op->ops.copy_attr = ia32_copy_attr; 11053 set_op_tag(op, ia32_op_tag); 11054 ia32_init_op(op, 0); 11055 op_ia32_Unknown = op; 11056 op = new_ir_op(cur_opcode + iro_ia32_UD2, "ia32_UD2", op_pin_state_pinned, irop_flag_none, oparity_unary, 0, sizeof(ia32_attr_t)); 11057 op->ops.be_ops = be_ops; 11058 op->ops.dump_node = ia32_dump_node; 11059 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11060 op->ops.copy_attr = ia32_copy_attr; 11061 set_op_tag(op, ia32_op_tag); 11062 ia32_init_op(op, 0); 11063 op_ia32_UD2 = op; 11064 op = new_ir_op(cur_opcode + iro_ia32_Cwtl, "ia32_Cwtl", op_pin_state_exc_pinned, irop_flag_none, oparity_unary, 0, sizeof(ia32_attr_t)); 11065 op->ops.be_ops = be_ops; 11066 op->ops.dump_node = ia32_dump_node; 11067 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11068 op->ops.copy_attr = ia32_copy_attr; 11069 set_op_tag(op, ia32_op_tag); 11070 ia32_init_op(op, 1); 11071 op_ia32_Cwtl = op; 11072 op = new_ir_op(cur_opcode + iro_ia32_fabs, "ia32_fabs", op_pin_state_floats, irop_flag_none, oparity_unary, 0, sizeof(ia32_x87_attr_t)); 11073 op->ops.be_ops = be_ops; 11074 op->ops.dump_node = ia32_dump_node; 11075 op->ops.node_cmp_attr = ia32_compare_x87_attr; 11076 op->ops.copy_attr = ia32_copy_attr; 11077 set_op_tag(op, ia32_op_tag); 11078 ia32_init_op(op, 2); 11079 op_ia32_fabs = op; 11080 op = new_ir_op(cur_opcode + iro_ia32_fldpi, "ia32_fldpi", op_pin_state_floats, irop_flag_none, oparity_zero, 0, sizeof(ia32_x87_attr_t)); 11081 op->ops.be_ops = be_ops; 11082 op->ops.dump_node = ia32_dump_node; 11083 op->ops.node_cmp_attr = ia32_compare_x87_attr; 11084 op->ops.copy_attr = ia32_copy_attr; 11085 set_op_tag(op, ia32_op_tag); 11086 ia32_init_op(op, 4); 11087 op_ia32_fldpi = op; 11088 op = new_ir_op(cur_opcode + iro_ia32_Leave, "ia32_Leave", op_pin_state_exc_pinned, irop_flag_none, oparity_unary, 0, sizeof(ia32_attr_t)); 11089 op->ops.be_ops = be_ops; 11090 op->ops.dump_node = ia32_dump_node; 11091 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11092 op->ops.copy_attr = ia32_copy_attr; 11093 set_op_tag(op, ia32_op_tag); 11094 ia32_init_op(op, 3); 11095 op_ia32_Leave = op; 11096 op = new_ir_op(cur_opcode + iro_ia32_Neg, "ia32_Neg", op_pin_state_floats, irop_flag_none, oparity_unary, 0, sizeof(ia32_attr_t)); 11097 op->ops.be_ops = be_ops; 11098 op->ops.dump_node = ia32_dump_node; 11099 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11100 op->ops.copy_attr = ia32_copy_attr; 11101 set_op_tag(op, ia32_op_tag); 11102 ia32_init_op(op, 1); 11103 op_ia32_Neg = op; 11104 op = new_ir_op(cur_opcode + iro_ia32_IMul1OP, "ia32_IMul1OP", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 11105 op->ops.be_ops = be_ops; 11106 op->ops.dump_node = ia32_dump_node; 11107 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11108 op->ops.copy_attr = ia32_copy_attr; 11109 set_op_tag(op, ia32_op_tag); 11110 ia32_init_op(op, 5); 11111 op_ia32_IMul1OP = op; 11112 op = new_ir_op(cur_opcode + iro_ia32_PopMem, "ia32_PopMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 11113 op->ops.be_ops = be_ops; 11114 op->ops.dump_node = ia32_dump_node; 11115 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11116 op->ops.copy_attr = ia32_copy_attr; 11117 set_op_tag(op, ia32_op_tag); 11118 ia32_init_op(op, 3); 11119 op_ia32_PopMem = op; 11120 op = new_ir_op(cur_opcode + iro_ia32_fld, "ia32_fld", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_trinary, 0, sizeof(ia32_x87_attr_t)); 11121 op->ops.be_ops = be_ops; 11122 op->ops.dump_node = ia32_dump_node; 11123 op->ops.node_cmp_attr = ia32_compare_x87_attr; 11124 op->ops.copy_attr = ia32_copy_attr; 11125 ir_op_set_memory_index(op, n_ia32_fld_mem); 11126 ir_op_set_fragile_indices(op, pn_ia32_fld_X_regular, pn_ia32_fld_X_except); 11127 set_op_tag(op, ia32_op_tag); 11128 ia32_init_op(op, 2); 11129 op_ia32_fld = op; 11130 op = new_ir_op(cur_opcode + iro_ia32_Dec, "ia32_Dec", op_pin_state_floats, irop_flag_none, oparity_unary, 0, sizeof(ia32_attr_t)); 11131 op->ops.be_ops = be_ops; 11132 op->ops.dump_node = ia32_dump_node; 11133 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11134 op->ops.copy_attr = ia32_copy_attr; 11135 set_op_tag(op, ia32_op_tag); 11136 ia32_init_op(op, 1); 11137 op_ia32_Dec = op; 11138 op = new_ir_op(cur_opcode + iro_ia32_Pop, "ia32_Pop", op_pin_state_exc_pinned, irop_flag_none, oparity_binary, 0, sizeof(ia32_attr_t)); 11139 op->ops.be_ops = be_ops; 11140 op->ops.dump_node = ia32_dump_node; 11141 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11142 op->ops.copy_attr = ia32_copy_attr; 11143 set_op_tag(op, ia32_op_tag); 11144 ia32_init_op(op, 3); 11145 op_ia32_Pop = op; 11146 op = new_ir_op(cur_opcode + iro_ia32_CopyEbpEsp, "ia32_CopyEbpEsp", op_pin_state_exc_pinned, irop_flag_none, oparity_unary, 0, sizeof(ia32_attr_t)); 11147 op->ops.be_ops = be_ops; 11148 op->ops.dump_node = ia32_dump_node; 11149 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11150 op->ops.copy_attr = ia32_copy_attr; 11151 set_op_tag(op, ia32_op_tag); 11152 ia32_init_op(op, 1); 11153 op_ia32_CopyEbpEsp = op; 11154 op = new_ir_op(cur_opcode + iro_ia32_Not, "ia32_Not", op_pin_state_floats, irop_flag_none, oparity_unary, 0, sizeof(ia32_attr_t)); 11155 op->ops.be_ops = be_ops; 11156 op->ops.dump_node = ia32_dump_node; 11157 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11158 op->ops.copy_attr = ia32_copy_attr; 11159 set_op_tag(op, ia32_op_tag); 11160 ia32_init_op(op, 1); 11161 op_ia32_Not = op; 11162 op = new_ir_op(cur_opcode + iro_ia32_NoReg_FP, "ia32_NoReg_FP", op_pin_state_pinned, irop_flag_constlike|irop_flag_dump_noblock, oparity_zero, 0, sizeof(ia32_x87_attr_t)); 11163 op->ops.be_ops = be_ops; 11164 op->ops.dump_node = ia32_dump_node; 11165 op->ops.node_cmp_attr = ia32_compare_x87_attr; 11166 op->ops.copy_attr = ia32_copy_attr; 11167 set_op_tag(op, ia32_op_tag); 11168 ia32_init_op(op, 0); 11169 op_ia32_NoReg_FP = op; 11170 op = new_ir_op(cur_opcode + iro_ia32_AndMem, "ia32_AndMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 11171 op->ops.be_ops = be_ops; 11172 op->ops.dump_node = ia32_dump_node; 11173 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11174 op->ops.copy_attr = ia32_copy_attr; 11175 set_op_tag(op, ia32_op_tag); 11176 ia32_init_op(op, 1); 11177 op_ia32_AndMem = op; 11178 op = new_ir_op(cur_opcode + iro_ia32_femms, "ia32_femms", op_pin_state_floats, irop_flag_keep, oparity_zero, 0, sizeof(ia32_x87_attr_t)); 11179 op->ops.be_ops = be_ops; 11180 op->ops.dump_node = ia32_dump_node; 11181 op->ops.node_cmp_attr = cmp_attr_ia32_femms; 11182 op->ops.copy_attr = ia32_copy_attr; 11183 set_op_tag(op, ia32_op_tag); 11184 ia32_init_op(op, 3); 11185 op_ia32_femms = op; 11186 op = new_ir_op(cur_opcode + iro_ia32_xStoreSimple, "ia32_xStoreSimple", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_any, 0, sizeof(ia32_attr_t)); 11187 op->ops.be_ops = be_ops; 11188 op->ops.dump_node = ia32_dump_node; 11189 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11190 op->ops.copy_attr = ia32_copy_attr; 11191 ir_op_set_memory_index(op, n_ia32_xStoreSimple_mem); 11192 ir_op_set_fragile_indices(op, pn_ia32_xStoreSimple_X_regular, pn_ia32_xStoreSimple_X_except); 11193 set_op_tag(op, ia32_op_tag); 11194 ia32_init_op(op, 0); 11195 op_ia32_xStoreSimple = op; 11196 op = new_ir_op(cur_opcode + iro_ia32_And, "ia32_And", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 11197 op->ops.be_ops = be_ops; 11198 op->ops.dump_node = ia32_dump_node; 11199 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11200 op->ops.copy_attr = ia32_copy_attr; 11201 set_op_tag(op, ia32_op_tag); 11202 ia32_init_op(op, 1); 11203 op_ia32_And = op; 11204 op = new_ir_op(cur_opcode + iro_ia32_Jcc, "ia32_Jcc", op_pin_state_pinned, irop_flag_cfopcode|irop_flag_forking, oparity_unary, 0, sizeof(ia32_condcode_attr_t)); 11205 op->ops.be_ops = be_ops; 11206 op->ops.dump_node = ia32_dump_node; 11207 op->ops.node_cmp_attr = ia32_compare_condcode_attr; 11208 op->ops.copy_attr = ia32_copy_attr; 11209 set_op_tag(op, ia32_op_tag); 11210 ia32_init_op(op, 2); 11211 op_ia32_Jcc = op; 11212 op = new_ir_op(cur_opcode + iro_ia32_Asm, "ia32_Asm", op_pin_state_floats, irop_flag_none, oparity_variable, 0, sizeof(ia32_asm_attr_t)); 11213 op->ops.be_ops = be_ops; 11214 op->ops.dump_node = ia32_dump_node; 11215 op->ops.node_cmp_attr = ia32_compare_asm_attr; 11216 op->ops.copy_attr = ia32_copy_attr; 11217 set_op_tag(op, ia32_op_tag); 11218 ia32_init_op(op, 10); 11219 op_ia32_Asm = op; 11220 op = new_ir_op(cur_opcode + iro_ia32_l_Sbb, "ia32_l_Sbb", op_pin_state_floats, irop_flag_none, oparity_trinary, 0, 0); 11221 op->ops.be_ops = be_ops; 11222 op->ops.dump_node = NULL; 11223 op->ops.node_cmp_attr = NULL; 11224 set_op_tag(op, ia32_op_tag); 11225 ia32_init_op(op, 0); 11226 op_ia32_l_Sbb = op; 11227 op = new_ir_op(cur_opcode + iro_ia32_Bsr, "ia32_Bsr", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 11228 op->ops.be_ops = be_ops; 11229 op->ops.dump_node = ia32_dump_node; 11230 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11231 op->ops.copy_attr = ia32_copy_attr; 11232 set_op_tag(op, ia32_op_tag); 11233 ia32_init_op(op, 1); 11234 op_ia32_Bsr = op; 11235 op = new_ir_op(cur_opcode + iro_ia32_Bswap16, "ia32_Bswap16", op_pin_state_floats, irop_flag_none, oparity_unary, 0, sizeof(ia32_attr_t)); 11236 op->ops.be_ops = be_ops; 11237 op->ops.dump_node = ia32_dump_node; 11238 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11239 op->ops.copy_attr = ia32_copy_attr; 11240 set_op_tag(op, ia32_op_tag); 11241 ia32_init_op(op, 1); 11242 op_ia32_Bswap16 = op; 11243 op = new_ir_op(cur_opcode + iro_ia32_Inport, "ia32_Inport", op_pin_state_pinned, irop_flag_none, oparity_binary, 0, sizeof(ia32_attr_t)); 11244 op->ops.be_ops = be_ops; 11245 op->ops.dump_node = ia32_dump_node; 11246 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11247 op->ops.copy_attr = ia32_copy_attr; 11248 set_op_tag(op, ia32_op_tag); 11249 ia32_init_op(op, 1); 11250 op_ia32_Inport = op; 11251 op = new_ir_op(cur_opcode + iro_ia32_SarMem, "ia32_SarMem", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 11252 op->ops.be_ops = be_ops; 11253 op->ops.dump_node = ia32_dump_node; 11254 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11255 op->ops.copy_attr = ia32_copy_attr; 11256 set_op_tag(op, ia32_op_tag); 11257 ia32_init_op(op, 1); 11258 op_ia32_SarMem = op; 11259 op = new_ir_op(cur_opcode + iro_ia32_RepPrefix, "ia32_RepPrefix", op_pin_state_pinned, irop_flag_keep, oparity_zero, 0, sizeof(ia32_attr_t)); 11260 op->ops.be_ops = be_ops; 11261 op->ops.dump_node = ia32_dump_node; 11262 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11263 op->ops.copy_attr = ia32_copy_attr; 11264 set_op_tag(op, ia32_op_tag); 11265 ia32_init_op(op, 0); 11266 op_ia32_RepPrefix = op; 11267 op = new_ir_op(cur_opcode + iro_ia32_Adc, "ia32_Adc", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 11268 op->ops.be_ops = be_ops; 11269 op->ops.dump_node = ia32_dump_node; 11270 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11271 op->ops.copy_attr = ia32_copy_attr; 11272 set_op_tag(op, ia32_op_tag); 11273 ia32_init_op(op, 1); 11274 op_ia32_Adc = op; 11275 op = new_ir_op(cur_opcode + iro_ia32_l_Mul, "ia32_l_Mul", op_pin_state_floats, irop_flag_none, oparity_binary, 0, 0); 11276 op->ops.be_ops = be_ops; 11277 op->ops.dump_node = NULL; 11278 op->ops.node_cmp_attr = NULL; 11279 set_op_tag(op, ia32_op_tag); 11280 ia32_init_op(op, 0); 11281 op_ia32_l_Mul = op; 11282 op = new_ir_op(cur_opcode + iro_ia32_xAndNot, "ia32_xAndNot", op_pin_state_exc_pinned, irop_flag_none, oparity_any, 0, sizeof(ia32_attr_t)); 11283 op->ops.be_ops = be_ops; 11284 op->ops.dump_node = ia32_dump_node; 11285 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11286 op->ops.copy_attr = ia32_copy_attr; 11287 set_op_tag(op, ia32_op_tag); 11288 ia32_init_op(op, 3); 11289 op_ia32_xAndNot = op; 11290 op = new_ir_op(cur_opcode + iro_ia32_Load, "ia32_Load", op_pin_state_exc_pinned, irop_flag_uses_memory|irop_flag_fragile, oparity_trinary, 0, sizeof(ia32_attr_t)); 11291 op->ops.be_ops = be_ops; 11292 op->ops.dump_node = ia32_dump_node; 11293 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11294 op->ops.copy_attr = ia32_copy_attr; 11295 ir_op_set_memory_index(op, n_ia32_Load_mem); 11296 ir_op_set_fragile_indices(op, pn_ia32_Load_X_regular, pn_ia32_Load_X_except); 11297 set_op_tag(op, ia32_op_tag); 11298 ia32_init_op(op, 0); 11299 op_ia32_Load = op; 11300 op = new_ir_op(cur_opcode + iro_ia32_Prefetch, "ia32_Prefetch", op_pin_state_exc_pinned, irop_flag_uses_memory, oparity_trinary, 0, sizeof(ia32_attr_t)); 11301 op->ops.be_ops = be_ops; 11302 op->ops.dump_node = ia32_dump_node; 11303 op->ops.node_cmp_attr = ia32_compare_nodes_attr; 11304 op->ops.copy_attr = ia32_copy_attr; 11305 set_op_tag(op, ia32_op_tag); 11306 ia32_init_op(op, 0); 11307 op_ia32_Prefetch = op; 11308 11309 ia32_opcode_end = cur_opcode + iro_ia32_last; 11310} 11311 11312void ia32_free_opcodes(void) 11313{ 11314 free_ir_op(op_ia32_xZero); op_ia32_xZero = NULL; 11315 free_ir_op(op_ia32_FldCW); op_ia32_FldCW = NULL; 11316 free_ir_op(op_ia32_fadd); op_ia32_fadd = NULL; 11317 free_ir_op(op_ia32_ShrMem); op_ia32_ShrMem = NULL; 11318 free_ir_op(op_ia32_Immediate); op_ia32_Immediate = NULL; 11319 free_ir_op(op_ia32_CvtSI2SS); op_ia32_CvtSI2SS = NULL; 11320 free_ir_op(op_ia32_Bsf); op_ia32_Bsf = NULL; 11321 free_ir_op(op_ia32_LdTls); op_ia32_LdTls = NULL; 11322 free_ir_op(op_ia32_ShlD); op_ia32_ShlD = NULL; 11323 free_ir_op(op_ia32_PopEbp); op_ia32_PopEbp = NULL; 11324 free_ir_op(op_ia32_Inc); op_ia32_Inc = NULL; 11325 free_ir_op(op_ia32_xStore); op_ia32_xStore = NULL; 11326 free_ir_op(op_ia32_xxLoad); op_ia32_xxLoad = NULL; 11327 free_ir_op(op_ia32_xAnd); op_ia32_xAnd = NULL; 11328 free_ir_op(op_ia32_GetEIP); op_ia32_GetEIP = NULL; 11329 free_ir_op(op_ia32_xAdd); op_ia32_xAdd = NULL; 11330 free_ir_op(op_ia32_xPsllq); op_ia32_xPsllq = NULL; 11331 free_ir_op(op_ia32_xxStore); op_ia32_xxStore = NULL; 11332 free_ir_op(op_ia32_Call); op_ia32_Call = NULL; 11333 free_ir_op(op_ia32_FnstCWNOP); op_ia32_FnstCWNOP = NULL; 11334 free_ir_op(op_ia32_XorMem8Bit); op_ia32_XorMem8Bit = NULL; 11335 free_ir_op(op_ia32_fldl2t); op_ia32_fldl2t = NULL; 11336 free_ir_op(op_ia32_fisttp); op_ia32_fisttp = NULL; 11337 free_ir_op(op_ia32_DecMem); op_ia32_DecMem = NULL; 11338 free_ir_op(op_ia32_emms); op_ia32_emms = NULL; 11339 free_ir_op(op_ia32_xLoad); op_ia32_xLoad = NULL; 11340 free_ir_op(op_ia32_l_FloattoLL); op_ia32_l_FloattoLL = NULL; 11341 free_ir_op(op_ia32_CvtSI2SD); op_ia32_CvtSI2SD = NULL; 11342 free_ir_op(op_ia32_XorMem); op_ia32_XorMem = NULL; 11343 free_ir_op(op_ia32_CopyB); op_ia32_CopyB = NULL; 11344 free_ir_op(op_ia32_Xor0); op_ia32_Xor0 = NULL; 11345 free_ir_op(op_ia32_Sar); op_ia32_Sar = NULL; 11346 free_ir_op(op_ia32_Div); op_ia32_Div = NULL; 11347 free_ir_op(op_ia32_fpushCopy); op_ia32_fpushCopy = NULL; 11348 free_ir_op(op_ia32_Stc); op_ia32_Stc = NULL; 11349 free_ir_op(op_ia32_Fucomi); op_ia32_Fucomi = NULL; 11350 free_ir_op(op_ia32_fldl2e); op_ia32_fldl2e = NULL; 11351 free_ir_op(op_ia32_Enter); op_ia32_Enter = NULL; 11352 free_ir_op(op_ia32_fmul); op_ia32_fmul = NULL; 11353 free_ir_op(op_ia32_l_IMul); op_ia32_l_IMul = NULL; 11354 free_ir_op(op_ia32_NoReg_XMM); op_ia32_NoReg_XMM = NULL; 11355 free_ir_op(op_ia32_xMax); op_ia32_xMax = NULL; 11356 free_ir_op(op_ia32_OrMem8Bit); op_ia32_OrMem8Bit = NULL; 11357 free_ir_op(op_ia32_Prefetch1); op_ia32_Prefetch1 = NULL; 11358 free_ir_op(op_ia32_fsub); op_ia32_fsub = NULL; 11359 free_ir_op(op_ia32_Lea); op_ia32_Lea = NULL; 11360 free_ir_op(op_ia32_FtstFnstsw); op_ia32_FtstFnstsw = NULL; 11361 free_ir_op(op_ia32_NotMem); op_ia32_NotMem = NULL; 11362 free_ir_op(op_ia32_Sbb0); op_ia32_Sbb0 = NULL; 11363 free_ir_op(op_ia32_Bt); op_ia32_Bt = NULL; 11364 free_ir_op(op_ia32_Or); op_ia32_Or = NULL; 11365 free_ir_op(op_ia32_Xor); op_ia32_Xor = NULL; 11366 free_ir_op(op_ia32_CopyB_i); op_ia32_CopyB_i = NULL; 11367 free_ir_op(op_ia32_IncMem); op_ia32_IncMem = NULL; 11368 free_ir_op(op_ia32_xAllOnes); op_ia32_xAllOnes = NULL; 11369 free_ir_op(op_ia32_Breakpoint); op_ia32_Breakpoint = NULL; 11370 free_ir_op(op_ia32_ClimbFrame); op_ia32_ClimbFrame = NULL; 11371 free_ir_op(op_ia32_ffreep); op_ia32_ffreep = NULL; 11372 free_ir_op(op_ia32_SubMem); op_ia32_SubMem = NULL; 11373 free_ir_op(op_ia32_AddMem); op_ia32_AddMem = NULL; 11374 free_ir_op(op_ia32_ShlMem); op_ia32_ShlMem = NULL; 11375 free_ir_op(op_ia32_fdiv); op_ia32_fdiv = NULL; 11376 free_ir_op(op_ia32_Outport); op_ia32_Outport = NULL; 11377 free_ir_op(op_ia32_xMin); op_ia32_xMin = NULL; 11378 free_ir_op(op_ia32_fist); op_ia32_fist = NULL; 11379 free_ir_op(op_ia32_xXor); op_ia32_xXor = NULL; 11380 free_ir_op(op_ia32_IJmp); op_ia32_IJmp = NULL; 11381 free_ir_op(op_ia32_NegMem); op_ia32_NegMem = NULL; 11382 free_ir_op(op_ia32_CMovcc); op_ia32_CMovcc = NULL; 11383 free_ir_op(op_ia32_Mul); op_ia32_Mul = NULL; 11384 free_ir_op(op_ia32_Sahf); op_ia32_Sahf = NULL; 11385 free_ir_op(op_ia32_SubMem8Bit); op_ia32_SubMem8Bit = NULL; 11386 free_ir_op(op_ia32_AddMem8Bit); op_ia32_AddMem8Bit = NULL; 11387 free_ir_op(op_ia32_fst); op_ia32_fst = NULL; 11388 free_ir_op(op_ia32_FucomppFnstsw); op_ia32_FucomppFnstsw = NULL; 11389 free_ir_op(op_ia32_RorMem); op_ia32_RorMem = NULL; 11390 free_ir_op(op_ia32_fpush); op_ia32_fpush = NULL; 11391 free_ir_op(op_ia32_fild); op_ia32_fild = NULL; 11392 free_ir_op(op_ia32_xOr); op_ia32_xOr = NULL; 11393 free_ir_op(op_ia32_Conv_I2I8Bit); op_ia32_Conv_I2I8Bit = NULL; 11394 free_ir_op(op_ia32_Store); op_ia32_Store = NULL; 11395 free_ir_op(op_ia32_fldln2); op_ia32_fldln2 = NULL; 11396 free_ir_op(op_ia32_SwitchJmp); op_ia32_SwitchJmp = NULL; 11397 free_ir_op(op_ia32_IMul); op_ia32_IMul = NULL; 11398 free_ir_op(op_ia32_Ucomi); op_ia32_Ucomi = NULL; 11399 free_ir_op(op_ia32_fldz); op_ia32_fldz = NULL; 11400 free_ir_op(op_ia32_Store8Bit); op_ia32_Store8Bit = NULL; 11401 free_ir_op(op_ia32_fpop); op_ia32_fpop = NULL; 11402 free_ir_op(op_ia32_l_Sub); op_ia32_l_Sub = NULL; 11403 free_ir_op(op_ia32_Sbb); op_ia32_Sbb = NULL; 11404 free_ir_op(op_ia32_FucomFnstsw); op_ia32_FucomFnstsw = NULL; 11405 free_ir_op(op_ia32_xMul); op_ia32_xMul = NULL; 11406 free_ir_op(op_ia32_Push); op_ia32_Push = NULL; 11407 free_ir_op(op_ia32_xPslld); op_ia32_xPslld = NULL; 11408 free_ir_op(op_ia32_Cmp); op_ia32_Cmp = NULL; 11409 free_ir_op(op_ia32_xSub); op_ia32_xSub = NULL; 11410 free_ir_op(op_ia32_xMovd); op_ia32_xMovd = NULL; 11411 free_ir_op(op_ia32_Cltd); op_ia32_Cltd = NULL; 11412 free_ir_op(op_ia32_xPsrld); op_ia32_xPsrld = NULL; 11413 free_ir_op(op_ia32_PushEax); op_ia32_PushEax = NULL; 11414 free_ir_op(op_ia32_XorHighLow); op_ia32_XorHighLow = NULL; 11415 free_ir_op(op_ia32_xPzero); op_ia32_xPzero = NULL; 11416 free_ir_op(op_ia32_Rol); op_ia32_Rol = NULL; 11417 free_ir_op(op_ia32_Cmc); op_ia32_Cmc = NULL; 11418 free_ir_op(op_ia32_Cmp8Bit); op_ia32_Cmp8Bit = NULL; 11419 free_ir_op(op_ia32_xDiv); op_ia32_xDiv = NULL; 11420 free_ir_op(op_ia32_xUnknown); op_ia32_xUnknown = NULL; 11421 free_ir_op(op_ia32_Test8Bit); op_ia32_Test8Bit = NULL; 11422 free_ir_op(op_ia32_Sub); op_ia32_Sub = NULL; 11423 free_ir_op(op_ia32_PrefetchNTA); op_ia32_PrefetchNTA = NULL; 11424 free_ir_op(op_ia32_Shr); op_ia32_Shr = NULL; 11425 free_ir_op(op_ia32_fprem); op_ia32_fprem = NULL; 11426 free_ir_op(op_ia32_IDiv); op_ia32_IDiv = NULL; 11427 free_ir_op(op_ia32_l_Adc); op_ia32_l_Adc = NULL; 11428 free_ir_op(op_ia32_Setcc); op_ia32_Setcc = NULL; 11429 free_ir_op(op_ia32_l_LLtoFloat); op_ia32_l_LLtoFloat = NULL; 11430 free_ir_op(op_ia32_ProduceVal); op_ia32_ProduceVal = NULL; 11431 free_ir_op(op_ia32_Bswap); op_ia32_Bswap = NULL; 11432 free_ir_op(op_ia32_SetccMem); op_ia32_SetccMem = NULL; 11433 free_ir_op(op_ia32_Test); op_ia32_Test = NULL; 11434 free_ir_op(op_ia32_l_Add); op_ia32_l_Add = NULL; 11435 free_ir_op(op_ia32_AddSP); op_ia32_AddSP = NULL; 11436 free_ir_op(op_ia32_RolMem); op_ia32_RolMem = NULL; 11437 free_ir_op(op_ia32_Conv_I2FP); op_ia32_Conv_I2FP = NULL; 11438 free_ir_op(op_ia32_Conv_FP2FP); op_ia32_Conv_FP2FP = NULL; 11439 free_ir_op(op_ia32_ChangeCW); op_ia32_ChangeCW = NULL; 11440 free_ir_op(op_ia32_Prefetch2); op_ia32_Prefetch2 = NULL; 11441 free_ir_op(op_ia32_NoReg_GP); op_ia32_NoReg_GP = NULL; 11442 free_ir_op(op_ia32_Const); op_ia32_Const = NULL; 11443 free_ir_op(op_ia32_Minus64Bit); op_ia32_Minus64Bit = NULL; 11444 free_ir_op(op_ia32_Jmp); op_ia32_Jmp = NULL; 11445 free_ir_op(op_ia32_FnstCW); op_ia32_FnstCW = NULL; 11446 free_ir_op(op_ia32_Prefetch0); op_ia32_Prefetch0 = NULL; 11447 free_ir_op(op_ia32_OrMem); op_ia32_OrMem = NULL; 11448 free_ir_op(op_ia32_fldlg2); op_ia32_fldlg2 = NULL; 11449 free_ir_op(op_ia32_fld1); op_ia32_fld1 = NULL; 11450 free_ir_op(op_ia32_Conv_FP2I); op_ia32_Conv_FP2I = NULL; 11451 free_ir_op(op_ia32_Popcnt); op_ia32_Popcnt = NULL; 11452 free_ir_op(op_ia32_Ror); op_ia32_Ror = NULL; 11453 free_ir_op(op_ia32_Shl); op_ia32_Shl = NULL; 11454 free_ir_op(op_ia32_AndMem8Bit); op_ia32_AndMem8Bit = NULL; 11455 free_ir_op(op_ia32_Add); op_ia32_Add = NULL; 11456 free_ir_op(op_ia32_SubSP); op_ia32_SubSP = NULL; 11457 free_ir_op(op_ia32_PrefetchW); op_ia32_PrefetchW = NULL; 11458 free_ir_op(op_ia32_Conv_I2I); op_ia32_Conv_I2I = NULL; 11459 free_ir_op(op_ia32_fxch); op_ia32_fxch = NULL; 11460 free_ir_op(op_ia32_fchs); op_ia32_fchs = NULL; 11461 free_ir_op(op_ia32_ShrD); op_ia32_ShrD = NULL; 11462 free_ir_op(op_ia32_Unknown); op_ia32_Unknown = NULL; 11463 free_ir_op(op_ia32_UD2); op_ia32_UD2 = NULL; 11464 free_ir_op(op_ia32_Cwtl); op_ia32_Cwtl = NULL; 11465 free_ir_op(op_ia32_fabs); op_ia32_fabs = NULL; 11466 free_ir_op(op_ia32_fldpi); op_ia32_fldpi = NULL; 11467 free_ir_op(op_ia32_Leave); op_ia32_Leave = NULL; 11468 free_ir_op(op_ia32_Neg); op_ia32_Neg = NULL; 11469 free_ir_op(op_ia32_IMul1OP); op_ia32_IMul1OP = NULL; 11470 free_ir_op(op_ia32_PopMem); op_ia32_PopMem = NULL; 11471 free_ir_op(op_ia32_fld); op_ia32_fld = NULL; 11472 free_ir_op(op_ia32_Dec); op_ia32_Dec = NULL; 11473 free_ir_op(op_ia32_Pop); op_ia32_Pop = NULL; 11474 free_ir_op(op_ia32_CopyEbpEsp); op_ia32_CopyEbpEsp = NULL; 11475 free_ir_op(op_ia32_Not); op_ia32_Not = NULL; 11476 free_ir_op(op_ia32_NoReg_FP); op_ia32_NoReg_FP = NULL; 11477 free_ir_op(op_ia32_AndMem); op_ia32_AndMem = NULL; 11478 free_ir_op(op_ia32_femms); op_ia32_femms = NULL; 11479 free_ir_op(op_ia32_xStoreSimple); op_ia32_xStoreSimple = NULL; 11480 free_ir_op(op_ia32_And); op_ia32_And = NULL; 11481 free_ir_op(op_ia32_Jcc); op_ia32_Jcc = NULL; 11482 free_ir_op(op_ia32_Asm); op_ia32_Asm = NULL; 11483 free_ir_op(op_ia32_l_Sbb); op_ia32_l_Sbb = NULL; 11484 free_ir_op(op_ia32_Bsr); op_ia32_Bsr = NULL; 11485 free_ir_op(op_ia32_Bswap16); op_ia32_Bswap16 = NULL; 11486 free_ir_op(op_ia32_Inport); op_ia32_Inport = NULL; 11487 free_ir_op(op_ia32_SarMem); op_ia32_SarMem = NULL; 11488 free_ir_op(op_ia32_RepPrefix); op_ia32_RepPrefix = NULL; 11489 free_ir_op(op_ia32_Adc); op_ia32_Adc = NULL; 11490 free_ir_op(op_ia32_l_Mul); op_ia32_l_Mul = NULL; 11491 free_ir_op(op_ia32_xAndNot); op_ia32_xAndNot = NULL; 11492 free_ir_op(op_ia32_Load); op_ia32_Load = NULL; 11493 free_ir_op(op_ia32_Prefetch); op_ia32_Prefetch = NULL; 11494} 11495