1 // REQUIRES: powerpc-registered-target
2 // RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s
3 // RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-LE
4 #include <altivec.h>
5 
6 vector bool char vbc = { 0, 1, 0, 1, 0, 1, 0, 1,
7                          0, 1, 0, 1, 0, 1, 0, 1 };
8 vector signed char vsc = { -8,  9, -10, 11, -12, 13, -14, 15,
9                            -0,  1,  -2,  3,  -4,  5,  -6,  7};
10 vector unsigned char vuc = { 8,  9, 10, 11, 12, 13, 14, 15,
11                              0,  1,  2,  3,  4,  5,  6,  7};
12 vector float vf = { -1.5, 2.5, -3.5, 4.5 };
13 vector double vd = { 3.5, -7.5 };
14 vector bool short vbs = { 0, 1, 0, 1, 0, 1, 0, 1 };
15 vector signed short vss = { -1, 2, -3, 4, -5, 6, -7, 8 };
16 vector unsigned short vus = { 0, 1, 2, 3, 4, 5, 6, 7 };
17 vector bool int vbi = { 0, 1, 0, 1 };
18 vector signed int vsi = { -1, 2, -3, 4 };
19 vector unsigned int vui = { 0, 1, 2, 3 };
20 vector bool long long vbll = { 1, 0 };
21 vector signed long long vsll = { 255LL, -937LL };
22 vector unsigned long long vull = { 1447LL, 2894LL };
23 double d = 23.4;
24 signed long long sll = 618LL;
25 float af[4] = {23.4f, 56.7f, 89.0f, 12.3f};
26 double ad[2] = {23.4, 56.7};
27 signed char asc[16] = { -8,  9, -10, 11, -12, 13, -14, 15,
28                         -0,  1,  -2,  3,  -4,  5,  -6,  7};
29 unsigned char auc[16] = { 8,  9, 10, 11, 12, 13, 14, 15,
30                           0,  1,  2,  3,  4,  5,  6,  7};
31 signed short ass[8] = { -1, 2, -3, 4, -5, 6, -7, 8 };
32 unsigned short aus[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
33 signed int asi[4] = { -1, 2, -3, 4 };
34 unsigned int aui[4] = { 0, 1, 2, 3 };
35 signed long long asll[2] = { -1L, 2L };
36 unsigned long long aull[2] = { 1L, 2L };
37 
38 vector float res_vf;
39 vector double res_vd;
40 vector bool char res_vbc;
41 vector signed char res_vsc;
42 vector unsigned char res_vuc;
43 vector bool short res_vbs;
44 vector signed short res_vss;
45 vector unsigned short res_vus;
46 vector bool int res_vbi;
47 vector signed int res_vsi;
48 vector unsigned int res_vui;
49 vector bool long long res_vbll;
50 vector signed long long res_vsll;
51 vector unsigned long long res_vull;
52 vector signed __int128 res_vslll;
53 
54 double res_d;
55 float res_af[4];
56 double res_ad[2];
57 signed char res_asc[16];
58 unsigned char res_auc[16];
59 signed short res_ass[8];
60 unsigned short res_aus[8];
61 signed int res_asi[4];
62 unsigned int res_aui[4];
63 
dummy()64 void dummy() { }
65 
test1()66 void test1() {
67 // CHECK-LABEL: define void @test1
68 // CHECK-LE-LABEL: define void @test1
69 
70   res_vf = vec_abs(vf);
71 // CHECK: call <4 x float> @llvm.fabs.v4f32(<4 x float> %{{[0-9]*}})
72 // CHECK-LE: call <4 x float> @llvm.fabs.v4f32(<4 x float> %{{[0-9]*}})
73 
74   res_vd = vec_abs(vd);
75 // CHECK: call <2 x double> @llvm.fabs.v2f64(<2 x double> %{{[0-9]*}})
76 // CHECK-LE: call <2 x double> @llvm.fabs.v2f64(<2 x double> %{{[0-9]*}})
77 
78   res_vf = vec_nabs(vf);
79 // CHECK: [[VEC:%[0-9]+]] = call <4 x float> @llvm.fabs.v4f32(<4 x float> %{{[0-9]*}})
80 // CHECK-NEXT: fneg <4 x float> [[VEC]]
81 
82   res_vd = vec_nabs(vd);
83 // CHECK: [[VECD:%[0-9]+]] = call <2 x double> @llvm.fabs.v2f64(<2 x double> %{{[0-9]*}})
84 // CHECK: fneg <2 x double> [[VECD]]
85 
86   dummy();
87 // CHECK: call void @dummy()
88 // CHECK-LE: call void @dummy()
89 
90   res_vd = vec_add(vd, vd);
91 // CHECK: fadd <2 x double>
92 // CHECK-LE: fadd <2 x double>
93 
94   res_vd = vec_and(vbll, vd);
95 // CHECK: and <2 x i64>
96 // CHECK: bitcast <2 x i64> %{{[0-9]*}} to <2 x double>
97 // CHECK-LE: and <2 x i64>
98 // CHECK-LE: bitcast <2 x i64> %{{[0-9]*}} to <2 x double>
99 
100   res_vd = vec_and(vd, vbll);
101 // CHECK: and <2 x i64>
102 // CHECK: bitcast <2 x i64> %{{[0-9]*}} to <2 x double>
103 // CHECK-LE: and <2 x i64>
104 // CHECK-LE: bitcast <2 x i64> %{{[0-9]*}} to <2 x double>
105 
106   res_vd = vec_and(vd, vd);
107 // CHECK: and <2 x i64>
108 // CHECK: bitcast <2 x i64> %{{[0-9]*}} to <2 x double>
109 // CHECK-LE: and <2 x i64>
110 // CHECK-LE: bitcast <2 x i64> %{{[0-9]*}} to <2 x double>
111 
112   dummy();
113 // CHECK: call void @dummy()
114 // CHECK-LE: call void @dummy()
115 
116   res_vd = vec_andc(vbll, vd);
117 // CHECK: bitcast <2 x double> %{{[0-9]*}} to <2 x i64>
118 // CHECK: xor <2 x i64> %{{[0-9]*}}, <i64 -1, i64 -1>
119 // CHECK: and <2 x i64>
120 // CHECK: bitcast <2 x i64> %{{[0-9]*}} to <2 x double>
121 // CHECK-LE: bitcast <2 x double> %{{[0-9]*}} to <2 x i64>
122 // CHECK-LE: xor <2 x i64> %{{[0-9]*}}, <i64 -1, i64 -1>
123 // CHECK-LE: and <2 x i64>
124 // CHECK-LE: bitcast <2 x i64> %{{[0-9]*}} to <2 x double>
125 
126   dummy();
127 // CHECK: call void @dummy()
128 // CHECK-LE: call void @dummy()
129 
130   res_vd = vec_andc(vd, vbll);
131 // CHECK: bitcast <2 x double> %{{[0-9]*}} to <2 x i64>
132 // CHECK: xor <2 x i64> %{{[0-9]*}}, <i64 -1, i64 -1>
133 // CHECK: and <2 x i64>
134 // CHECK: bitcast <2 x i64> %{{[0-9]*}} to <2 x double>
135 // CHECK-LE: bitcast <2 x double> %{{[0-9]*}} to <2 x i64>
136 // CHECK-LE: xor <2 x i64> %{{[0-9]*}}, <i64 -1, i64 -1>
137 // CHECK-LE: and <2 x i64>
138 // CHECK-LE: bitcast <2 x i64> %{{[0-9]*}} to <2 x double>
139 
140   dummy();
141 // CHECK: call void @dummy()
142 
143   res_vd = vec_andc(vd, vd);
144 // CHECK: bitcast <2 x double> %{{[0-9]*}} to <2 x i64>
145 // CHECK: xor <2 x i64> %{{[0-9]*}}, <i64 -1, i64 -1>
146 // CHECK: and <2 x i64>
147 // CHECK: bitcast <2 x i64> %{{[0-9]*}} to <2 x double>
148 
149   dummy();
150 // CHECK: call void @dummy()
151 // CHECK-LE: call void @dummy()
152 
153   res_vd = vec_ceil(vd);
154 // CHECK: call <2 x double> @llvm.ceil.v2f64(<2 x double> %{{[0-9]*}})
155 // CHECK-LE: call <2 x double> @llvm.ceil.v2f64(<2 x double> %{{[0-9]*}})
156 
157   res_vf = vec_ceil(vf);
158 // CHECK: call <4 x float> @llvm.ceil.v4f32(<4 x float> %{{[0-9]*}})
159 // CHECK-LE: call <4 x float> @llvm.ceil.v4f32(<4 x float> %{{[0-9]*}})
160 
161   res_vbll = vec_cmpeq(vd, vd);
162 // CHECK: call <2 x i64> @llvm.ppc.vsx.xvcmpeqdp(<2 x double> %{{[0-9]*}}, <2 x double> %{{[0-9]*}})
163 // CHECK-LE: call <2 x i64> @llvm.ppc.vsx.xvcmpeqdp(<2 x double> %{{[0-9]*}}, <2 x double> %{{[0-9]*}})
164 
165   res_vbi = vec_cmpeq(vf, vf);
166 // CHECK: call <4 x i32> @llvm.ppc.vsx.xvcmpeqsp(<4 x float> %{{[0-9]*}}, <4 x float> %{{[0-9]*}})
167 // CHECK-LE: call <4 x i32> @llvm.ppc.vsx.xvcmpeqsp(<4 x float> %{{[0-9]*}}, <4 x float> %{{[0-9]*}})
168 
169   res_vbll = vec_cmpge(vd, vd);
170 // CHECK: call <2 x i64> @llvm.ppc.vsx.xvcmpgedp(<2 x double> %{{[0-9]*}}, <2 x double> %{{[0-9]*}})
171 // CHECK-LE: call <2 x i64> @llvm.ppc.vsx.xvcmpgedp(<2 x double> %{{[0-9]*}}, <2 x double> %{{[0-9]*}})
172 
173   res_vbi = vec_cmpge(vf, vf);
174 // CHECK: call <4 x i32> @llvm.ppc.vsx.xvcmpgesp(<4 x float> %{{[0-9]*}}, <4 x float> %{{[0-9]*}})
175 // CHECK-LE: call <4 x i32> @llvm.ppc.vsx.xvcmpgesp(<4 x float> %{{[0-9]*}}, <4 x float> %{{[0-9]*}})
176 
177   res_vbll = vec_cmpgt(vd, vd);
178 // CHECK: call <2 x i64> @llvm.ppc.vsx.xvcmpgtdp(<2 x double> %{{[0-9]*}}, <2 x double> %{{[0-9]*}})
179 // CHECK-LE: call <2 x i64> @llvm.ppc.vsx.xvcmpgtdp(<2 x double> %{{[0-9]*}}, <2 x double> %{{[0-9]*}})
180 
181   res_vbi = vec_cmpgt(vf, vf);
182 // CHECK: call <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float> %{{[0-9]*}}, <4 x float> %{{[0-9]*}})
183 // CHECK-LE: call <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float> %{{[0-9]*}}, <4 x float> %{{[0-9]*}})
184 
185   res_vbll = vec_cmple(vd, vd);
186 // CHECK: call <2 x i64> @llvm.ppc.vsx.xvcmpgedp(<2 x double> %{{[0-9]*}}, <2 x double> %{{[0-9]*}})
187 // CHECK-LE: call <2 x i64> @llvm.ppc.vsx.xvcmpgedp(<2 x double> %{{[0-9]*}}, <2 x double> %{{[0-9]*}})
188 
189   res_vbi = vec_cmple(vf, vf);
190 // CHECK: call <4 x i32> @llvm.ppc.vsx.xvcmpgesp(<4 x float> %{{[0-9]*}}, <4 x float> %{{[0-9]*}})
191 // CHECK-LE: call <4 x i32> @llvm.ppc.vsx.xvcmpgesp(<4 x float> %{{[0-9]*}}, <4 x float> %{{[0-9]*}})
192 
193   res_vbll = vec_cmplt(vd, vd);
194 // CHECK: call <2 x i64> @llvm.ppc.vsx.xvcmpgtdp(<2 x double> %{{[0-9]*}}, <2 x double> %{{[0-9]*}})
195 // CHECK-LE: call <2 x i64> @llvm.ppc.vsx.xvcmpgtdp(<2 x double> %{{[0-9]*}}, <2 x double> %{{[0-9]*}})
196 
197   res_vbi = vec_cmplt(vf, vf);
198 // CHECK: call <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float> %{{[0-9]*}}, <4 x float> %{{[0-9]*}})
199 // CHECK-LE: call <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float> %{{[0-9]*}}, <4 x float> %{{[0-9]*}})
200 
201   /* vec_cpsgn */
202   res_vf = vec_cpsgn(vf, vf);
203 // CHECK: call <4 x float> @llvm.copysign.v4f32(<4 x float> %{{.+}}, <4 x float> %{{.+}})
204 // CHECK-LE: call <4 x float> @llvm.copysign.v4f32(<4 x float> %{{.+}}, <4 x float> %{{.+}})
205 
206   res_vd = vec_cpsgn(vd, vd);
207 // CHECK: call <2 x double> @llvm.copysign.v2f64(<2 x double> %{{.+}}, <2 x double> %{{.+}})
208 // CHECK-LE: call <2 x double> @llvm.copysign.v2f64(<2 x double> %{{.+}}, <2 x double> %{{.+}})
209 
210   /* vec_div */
211   res_vsll = vec_div(vsll, vsll);
212 // CHECK: sdiv <2 x i64>
213 // CHECK-LE: sdiv <2 x i64>
214 
215   res_vull = vec_div(vull, vull);
216 // CHECK: udiv <2 x i64>
217 // CHECK-LE: udiv <2 x i64>
218 
219   res_vf = vec_div(vf, vf);
220 // CHECK: fdiv <4 x float>
221 // CHECK-LE: fdiv <4 x float>
222 
223   res_vd = vec_div(vd, vd);
224 // CHECK: fdiv <2 x double>
225 // CHECK-LE: fdiv <2 x double>
226 
227   /* vec_max */
228   res_vf = vec_max(vf, vf);
229 // CHECK: @llvm.ppc.vsx.xvmaxsp
230 // CHECK-LE: @llvm.ppc.vsx.xvmaxsp
231 
232   res_vd = vec_max(vd, vd);
233 // CHECK: @llvm.ppc.vsx.xvmaxdp
234 // CHECK-LE: @llvm.ppc.vsx.xvmaxdp
235 
236   res_vf = vec_vmaxfp(vf, vf);
237 // CHECK: @llvm.ppc.vsx.xvmaxsp
238 // CHECK-LE: @llvm.ppc.vsx.xvmaxsp
239 
240   /* vec_min */
241   res_vf = vec_min(vf, vf);
242 // CHECK: @llvm.ppc.vsx.xvminsp
243 // CHECK-LE: @llvm.ppc.vsx.xvminsp
244 
245   res_vd = vec_min(vd, vd);
246 // CHECK: @llvm.ppc.vsx.xvmindp
247 // CHECK-LE: @llvm.ppc.vsx.xvmindp
248 
249   res_vf = vec_vminfp(vf, vf);
250 // CHECK: @llvm.ppc.vsx.xvminsp
251 // CHECK-LE: @llvm.ppc.vsx.xvminsp
252 
253   res_d = __builtin_vsx_xsmaxdp(d, d);
254 // CHECK: @llvm.ppc.vsx.xsmaxdp
255 // CHECK-LE: @llvm.ppc.vsx.xsmaxdp
256 
257   res_d = __builtin_vsx_xsmindp(d, d);
258 // CHECK: @llvm.ppc.vsx.xsmindp
259 // CHECK-LE: @llvm.ppc.vsx.xsmindp
260 
261   /* vec_perm */
262   res_vsll = vec_perm(vsll, vsll, vuc);
263 // CHECK: @llvm.ppc.altivec.vperm
264 // CHECK-LE: @llvm.ppc.altivec.vperm
265 
266   res_vull = vec_perm(vull, vull, vuc);
267 // CHECK: @llvm.ppc.altivec.vperm
268 // CHECK-LE: @llvm.ppc.altivec.vperm
269 
270   res_vbll = vec_perm(vbll, vbll, vuc);
271 // CHECK: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
272 // CHECK: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
273 // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8>
274 // CHECK-LE: xor <16 x i8>
275 // CHECK-LE: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
276 // CHECK-LE: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
277 // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8>
278 
279   res_vf = vec_round(vf);
280 // CHECK: call <4 x float> @llvm.round.v4f32(<4 x float>
281 // CHECK-LE: call <4 x float> @llvm.round.v4f32(<4 x float>
282 
283   res_vd = vec_round(vd);
284 // CHECK: call <2 x double> @llvm.round.v2f64(<2 x double>
285 // CHECK-LE: call <2 x double> @llvm.round.v2f64(<2 x double>
286 
287   res_vd = vec_perm(vd, vd, vuc);
288 // CHECK: @llvm.ppc.altivec.vperm
289 // CHECK-LE: @llvm.ppc.altivec.vperm
290 
291   res_vd = vec_splat(vd, 1);
292 // CHECK: [[T1:%.+]] = bitcast <2 x double> {{.+}} to <4 x i32>
293 // CHECK: [[T2:%.+]] = bitcast <2 x double> {{.+}} to <4 x i32>
294 // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8>
295 // CHECK-LE: xor <16 x i8>
296 // CHECK-LE: [[T1:%.+]] = bitcast <2 x double> {{.+}} to <4 x i32>
297 // CHECK-LE: [[T2:%.+]] = bitcast <2 x double> {{.+}} to <4 x i32>
298 // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8>
299 
300   res_vbll = vec_splat(vbll, 1);
301 // CHECK: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
302 // CHECK: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
303 // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8>
304 // CHECK-LE: xor <16 x i8>
305 // CHECK-LE: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
306 // CHECK-LE: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
307 // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8>
308 
309   res_vsll =  vec_splat(vsll, 1);
310 // CHECK: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
311 // CHECK: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
312 // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8>
313 // CHECK-LE: xor <16 x i8>
314 // CHECK-LE: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
315 // CHECK-LE: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
316 // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8>
317 
318   res_vull =  vec_splat(vull, 1);
319 // CHECK: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
320 // CHECK: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
321 // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8>
322 // CHECK-LE: xor <16 x i8>
323 // CHECK-LE: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
324 // CHECK-LE: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
325 // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> [[T1]], <4 x i32> [[T2]], <16 x i8>
326 
327   res_vsi = vec_pack(vsll, vsll);
328 // CHECK: @llvm.ppc.altivec.vperm
329 // CHECK-LE: @llvm.ppc.altivec.vperm
330 
331   res_vui = vec_pack(vull, vull);
332 // CHECK: @llvm.ppc.altivec.vperm
333 // CHECK-LE: @llvm.ppc.altivec.vperm
334 
335   res_vbi = vec_pack(vbll, vbll);
336 // CHECK: @llvm.ppc.altivec.vperm
337 // CHECK-LE: @llvm.ppc.altivec.vperm
338 
339   res_vsll = vec_vperm(vsll, vsll, vuc);
340 // CHECK: @llvm.ppc.altivec.vperm
341 // CHECK-LE: @llvm.ppc.altivec.vperm
342 
343   res_vull = vec_vperm(vull, vull, vuc);
344 // CHECK: @llvm.ppc.altivec.vperm
345 // CHECK-LE: @llvm.ppc.altivec.vperm
346 
347   res_vd = vec_vperm(vd, vd, vuc);
348 // CHECK: @llvm.ppc.altivec.vperm
349 // CHECK-LE: @llvm.ppc.altivec.vperm
350 
351   /* vec_vsx_ld */
352 
353   res_vbi = vec_vsx_ld(0, &vbi);
354 // CHECK: @llvm.ppc.vsx.lxvw4x
355 // CHECK-LE: @llvm.ppc.vsx.lxvw4x
356 
357   res_vsi = vec_vsx_ld(0, &vsi);
358 // CHECK: @llvm.ppc.vsx.lxvw4x
359 // CHECK-LE: @llvm.ppc.vsx.lxvw4x
360 
361   res_vsi = vec_vsx_ld(0, asi);
362 // CHECK: @llvm.ppc.vsx.lxvw4x
363 // CHECK-LE: @llvm.ppc.vsx.lxvw4x
364 
365   res_vui = vec_vsx_ld(0, &vui);
366 // CHECK: @llvm.ppc.vsx.lxvw4x
367 // CHECK-LE: @llvm.ppc.vsx.lxvw4x
368 
369   res_vui = vec_vsx_ld(0, aui);
370 // CHECK: @llvm.ppc.vsx.lxvw4x
371 // CHECK-LE: @llvm.ppc.vsx.lxvw4x
372 
373   res_vf = vec_vsx_ld (0, &vf);
374 // CHECK: @llvm.ppc.vsx.lxvw4x
375 // CHECK-LE: @llvm.ppc.vsx.lxvw4x
376 
377   res_vf = vec_vsx_ld (0, af);
378 // CHECK: @llvm.ppc.vsx.lxvw4x
379 // CHECK-LE: @llvm.ppc.vsx.lxvw4x
380 
381   res_vsll = vec_vsx_ld(0, &vsll);
382 // CHECK: @llvm.ppc.vsx.lxvd2x
383 // CHECK-LE: @llvm.ppc.vsx.lxvd2x
384 
385   res_vull = vec_vsx_ld(0, &vull);
386 // CHECK: @llvm.ppc.vsx.lxvd2x
387 // CHECK-LE: @llvm.ppc.vsx.lxvd2x
388 
389   res_vd = vec_vsx_ld(0, &vd);
390 // CHECK: @llvm.ppc.vsx.lxvd2x
391 // CHECK-LE: @llvm.ppc.vsx.lxvd2x
392 
393   res_vd = vec_vsx_ld(0, ad);
394 // CHECK: @llvm.ppc.vsx.lxvd2x
395 // CHECK-LE: @llvm.ppc.vsx.lxvd2x
396 
397   res_vbs = vec_vsx_ld(0, &vbs);
398 // CHECK: @llvm.ppc.vsx.lxvw4x
399 // CHECK-LE: @llvm.ppc.vsx.lxvw4x
400 
401   res_vss = vec_vsx_ld(0, &vss);
402 // CHECK: @llvm.ppc.vsx.lxvw4x
403 // CHECK-LE: @llvm.ppc.vsx.lxvw4x
404 
405   res_vss = vec_vsx_ld(0, ass);
406 // CHECK: @llvm.ppc.vsx.lxvw4x
407 // CHECK-LE: @llvm.ppc.vsx.lxvw4x
408 
409   res_vus = vec_vsx_ld(0, &vus);
410 // CHECK: @llvm.ppc.vsx.lxvw4x
411 // CHECK-LE: @llvm.ppc.vsx.lxvw4x
412 
413   res_vus = vec_vsx_ld(0, aus);
414 // CHECK: @llvm.ppc.vsx.lxvw4x
415 // CHECK-LE: @llvm.ppc.vsx.lxvw4x
416 
417   res_vbc = vec_vsx_ld(0, &vbc);
418 // CHECK: @llvm.ppc.vsx.lxvw4x
419 // CHECK-LE: @llvm.ppc.vsx.lxvw4x
420 
421   res_vsc = vec_vsx_ld(0, &vsc);
422 // CHECK: @llvm.ppc.vsx.lxvw4x
423 // CHECK-LE: @llvm.ppc.vsx.lxvw4x
424 
425   res_vuc = vec_vsx_ld(0, &vuc);
426 // CHECK: @llvm.ppc.vsx.lxvw4x
427 // CHECK-LE: @llvm.ppc.vsx.lxvw4x
428 
429   res_vsc = vec_vsx_ld(0, asc);
430 // CHECK: @llvm.ppc.vsx.lxvw4x
431 // CHECK-LE: @llvm.ppc.vsx.lxvw4x
432 
433   res_vuc = vec_vsx_ld(0, auc);
434 // CHECK: @llvm.ppc.vsx.lxvw4x
435 // CHECK-LE: @llvm.ppc.vsx.lxvw4x
436 
437   /* vec_vsx_st */
438 
439   vec_vsx_st(vbi, 0, &res_vbi);
440 // CHECK: @llvm.ppc.vsx.stxvw4x
441 // CHECK-LE: @llvm.ppc.vsx.stxvw4x
442 
443   vec_vsx_st(vbi, 0, res_aui);
444 // CHECK: @llvm.ppc.vsx.stxvw4x
445 // CHECK-LE: @llvm.ppc.vsx.stxvw4x
446 
447   vec_vsx_st(vbi, 0, res_asi);
448 // CHECK: @llvm.ppc.vsx.stxvw4x
449 // CHECK-LE: @llvm.ppc.vsx.stxvw4x
450 
451   vec_vsx_st(vsi, 0, &res_vsi);
452 // CHECK: @llvm.ppc.vsx.stxvw4x
453 // CHECK-LE: @llvm.ppc.vsx.stxvw4x
454 
455   vec_vsx_st(vsi, 0, res_asi);
456 // CHECK: @llvm.ppc.vsx.stxvw4x
457 // CHECK-LE: @llvm.ppc.vsx.stxvw4x
458 
459   vec_vsx_st(vui, 0, &res_vui);
460 // CHECK: @llvm.ppc.vsx.stxvw4x
461 // CHECK-LE: @llvm.ppc.vsx.stxvw4x
462 
463   vec_vsx_st(vui, 0, res_aui);
464 // CHECK: @llvm.ppc.vsx.stxvw4x
465 // CHECK-LE: @llvm.ppc.vsx.stxvw4x
466 
467   vec_vsx_st(vf, 0, &res_vf);
468 // CHECK: @llvm.ppc.vsx.stxvw4x
469 // CHECK-LE: @llvm.ppc.vsx.stxvw4x
470 
471   vec_vsx_st(vf, 0, res_af);
472 // CHECK: @llvm.ppc.vsx.stxvw4x
473 // CHECK-LE: @llvm.ppc.vsx.stxvw4x
474 
475   vec_vsx_st(vsll, 0, &res_vsll);
476 // CHECK: @llvm.ppc.vsx.stxvd2x
477 // CHECK-LE: @llvm.ppc.vsx.stxvd2x
478 
479   vec_vsx_st(vull, 0, &res_vull);
480 // CHECK: @llvm.ppc.vsx.stxvd2x
481 // CHECK-LE: @llvm.ppc.vsx.stxvd2x
482 
483   vec_vsx_st(vd, 0, &res_vd);
484 // CHECK: @llvm.ppc.vsx.stxvd2x
485 // CHECK-LE: @llvm.ppc.vsx.stxvd2x
486 
487   vec_vsx_st(vd, 0, res_ad);
488 // CHECK: @llvm.ppc.vsx.stxvd2x
489 // CHECK-LE: @llvm.ppc.vsx.stxvd2x
490 
491   vec_vsx_st(vbs, 0, &res_vbs);
492 // CHECK: @llvm.ppc.vsx.stxvw4x
493 // CHECK-LE: @llvm.ppc.vsx.stxvw4x
494 
495   vec_vsx_st(vbs, 0, res_aus);
496 // CHECK: @llvm.ppc.vsx.stxvw4x
497 // CHECK-LE: @llvm.ppc.vsx.stxvw4x
498 
499   vec_vsx_st(vbs, 0, res_ass);
500 // CHECK: @llvm.ppc.vsx.stxvw4x
501 // CHECK-LE: @llvm.ppc.vsx.stxvw4x
502 
503   vec_vsx_st(vss, 0, &res_vss);
504 // CHECK: @llvm.ppc.vsx.stxvw4x
505 // CHECK-LE: @llvm.ppc.vsx.stxvw4x
506 
507   vec_vsx_st(vss, 0, res_ass);
508 // CHECK: @llvm.ppc.vsx.stxvw4x
509 // CHECK-LE: @llvm.ppc.vsx.stxvw4x
510 
511   vec_vsx_st(vus, 0, &res_vus);
512 // CHECK: @llvm.ppc.vsx.stxvw4x
513 // CHECK-LE: @llvm.ppc.vsx.stxvw4x
514 
515   vec_vsx_st(vus, 0, res_aus);
516 // CHECK: @llvm.ppc.vsx.stxvw4x
517 // CHECK-LE: @llvm.ppc.vsx.stxvw4x
518 
519   vec_vsx_st(vsc, 0, &res_vsc);
520 // CHECK: @llvm.ppc.vsx.stxvw4x
521 // CHECK-LE: @llvm.ppc.vsx.stxvw4x
522 
523   vec_vsx_st(vsc, 0, res_asc);
524 // CHECK: @llvm.ppc.vsx.stxvw4x
525 // CHECK-LE: @llvm.ppc.vsx.stxvw4x
526 
527   vec_vsx_st(vuc, 0, &res_vuc);
528 // CHECK: @llvm.ppc.vsx.stxvw4x
529 // CHECK-LE: @llvm.ppc.vsx.stxvw4x
530 
531   vec_vsx_st(vuc, 0, res_auc);
532 // CHECK: @llvm.ppc.vsx.stxvw4x
533 // CHECK-LE: @llvm.ppc.vsx.stxvw4x
534 
535   vec_vsx_st(vbc, 0, &res_vbc);
536 // CHECK: @llvm.ppc.vsx.stxvw4x
537 // CHECK-LE: @llvm.ppc.vsx.stxvw4x
538 
539   vec_vsx_st(vbc, 0, res_asc);
540 // CHECK: @llvm.ppc.vsx.stxvw4x
541 // CHECK-LE: @llvm.ppc.vsx.stxvw4x
542 
543   vec_vsx_st(vbc, 0, res_auc);
544 // CHECK: @llvm.ppc.vsx.stxvw4x
545 // CHECK-LE: @llvm.ppc.vsx.stxvw4x
546 
547   /* vec_and */
548   res_vsll = vec_and(vsll, vsll);
549 // CHECK: and <2 x i64>
550 // CHECK-LE: and <2 x i64>
551 
552   res_vsll = vec_and(vbll, vsll);
553 // CHECK: and <2 x i64>
554 // CHECK-LE: and <2 x i64>
555 
556   res_vsll = vec_and(vsll, vbll);
557 // CHECK: and <2 x i64>
558 // CHECK-LE: and <2 x i64>
559 
560   res_vull = vec_and(vull, vull);
561 // CHECK: and <2 x i64>
562 // CHECK-LE: and <2 x i64>
563 
564   res_vull = vec_and(vbll, vull);
565 // CHECK: and <2 x i64>
566 // CHECK-LE: and <2 x i64>
567 
568   res_vull = vec_and(vull, vbll);
569 // CHECK: and <2 x i64>
570 // CHECK-LE: and <2 x i64>
571 
572   res_vbll = vec_and(vbll, vbll);
573 // CHECK: and <2 x i64>
574 // CHECK-LE: and <2 x i64>
575 
576   /* vec_vand */
577   res_vsll = vec_vand(vsll, vsll);
578 // CHECK: and <2 x i64>
579 // CHECK-LE: and <2 x i64>
580 
581   res_vsll = vec_vand(vbll, vsll);
582 // CHECK: and <2 x i64>
583 // CHECK-LE: and <2 x i64>
584 
585   res_vsll = vec_vand(vsll, vbll);
586 // CHECK: and <2 x i64>
587 // CHECK-LE: and <2 x i64>
588 
589   res_vull = vec_vand(vull, vull);
590 // CHECK: and <2 x i64>
591 // CHECK-LE: and <2 x i64>
592 
593   res_vull = vec_vand(vbll, vull);
594 // CHECK: and <2 x i64>
595 // CHECK-LE: and <2 x i64>
596 
597   res_vull = vec_vand(vull, vbll);
598 // CHECK: and <2 x i64>
599 // CHECK-LE: and <2 x i64>
600 
601   res_vbll = vec_vand(vbll, vbll);
602 // CHECK: and <2 x i64>
603 // CHECK-LE: and <2 x i64>
604 
605   /* vec_andc */
606   res_vsll = vec_andc(vsll, vsll);
607 // CHECK: xor <2 x i64>
608 // CHECK: and <2 x i64>
609 // CHECK-LE: xor <2 x i64>
610 // CHECK-LE: and <2 x i64>
611 
612   res_vsll = vec_andc(vbll, vsll);
613 // CHECK: xor <2 x i64>
614 // CHECK: and <2 x i64>
615 // CHECK-LE: xor <2 x i64>
616 // CHECK-LE: and <2 x i64>
617 
618   res_vsll = vec_andc(vsll, vbll);
619 // CHECK: xor <2 x i64>
620 // CHECK: and <2 x i64>
621 // CHECK-LE: xor <2 x i64>
622 // CHECK-LE: and <2 x i64>
623 
624   res_vull = vec_andc(vull, vull);
625 // CHECK: xor <2 x i64>
626 // CHECK: and <2 x i64>
627 // CHECK-LE: xor <2 x i64>
628 // CHECK-LE: and <2 x i64>
629 
630   res_vull = vec_andc(vbll, vull);
631 // CHECK: xor <2 x i64>
632 // CHECK: and <2 x i64>
633 // CHECK-LE: xor <2 x i64>
634 // CHECK-LE: and <2 x i64>
635 
636   res_vull = vec_andc(vull, vbll);
637 // CHECK: xor <2 x i64>
638 // CHECK: and <2 x i64>
639 // CHECK-LE: xor <2 x i64>
640 // CHECK-LE: and <2 x i64>
641 
642   res_vbll = vec_andc(vbll, vbll);
643 // CHECK: xor <2 x i64>
644 // CHECK: and <2 x i64>
645 // CHECK-LE: xor <2 x i64>
646 // CHECK-LE: and <2 x i64>
647 
648   res_vf = vec_floor(vf);
649 // CHECK: call <4 x float> @llvm.floor.v4f32(<4 x float> %{{[0-9]+}})
650 // CHECK-LE: call <4 x float> @llvm.floor.v4f32(<4 x float> %{{[0-9]+}})
651 
652   res_vd = vec_floor(vd);
653 // CHECK: call <2 x double> @llvm.floor.v2f64(<2 x double> %{{[0-9]+}})
654 // CHECK-LE: call <2 x double> @llvm.floor.v2f64(<2 x double> %{{[0-9]+}})
655 
656   res_vf = vec_madd(vf, vf, vf);
657 // CHECK: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}})
658 // CHECK-LE: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}})
659 
660   res_vd = vec_madd(vd, vd, vd);
661 // CHECK: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}})
662 // CHECK-LE: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}})
663 
664   /* vec_mergeh */
665   res_vsll = vec_mergeh(vsll, vsll);
666 // CHECK: @llvm.ppc.altivec.vperm
667 // CHECK-LE: @llvm.ppc.altivec.vperm
668 
669   res_vsll = vec_mergeh(vsll, vbll);
670 // CHECK: @llvm.ppc.altivec.vperm
671 // CHECK-LE: @llvm.ppc.altivec.vperm
672 
673   res_vsll = vec_mergeh(vbll, vsll);
674 // CHECK: @llvm.ppc.altivec.vperm
675 // CHECK-LE: @llvm.ppc.altivec.vperm
676 
677   res_vull = vec_mergeh(vull, vull);
678 // CHECK: @llvm.ppc.altivec.vperm
679 // CHECK-LE: @llvm.ppc.altivec.vperm
680 
681   res_vull = vec_mergeh(vull, vbll);
682 // CHECK: @llvm.ppc.altivec.vperm
683 // CHECK-LE: @llvm.ppc.altivec.vperm
684 
685   res_vull = vec_mergeh(vbll, vull);
686 // CHECK: @llvm.ppc.altivec.vperm
687 // CHECK-LE: @llvm.ppc.altivec.vperm
688 
689   /* vec_mergel */
690   res_vsll = vec_mergel(vsll, vsll);
691 // CHECK: @llvm.ppc.altivec.vperm
692 // CHECK-LE: @llvm.ppc.altivec.vperm
693 
694   res_vsll = vec_mergel(vsll, vbll);
695 // CHECK: @llvm.ppc.altivec.vperm
696 // CHECK-LE: @llvm.ppc.altivec.vperm
697 
698   res_vsll = vec_mergel(vbll, vsll);
699 // CHECK: @llvm.ppc.altivec.vperm
700 // CHECK-LE: @llvm.ppc.altivec.vperm
701 
702   res_vull = vec_mergel(vull, vull);
703 // CHECK: @llvm.ppc.altivec.vperm
704 // CHECK-LE: @llvm.ppc.altivec.vperm
705 
706   res_vull = vec_mergel(vull, vbll);
707 // CHECK: @llvm.ppc.altivec.vperm
708 // CHECK-LE: @llvm.ppc.altivec.vperm
709 
710   res_vull = vec_mergel(vbll, vull);
711 // CHECK: @llvm.ppc.altivec.vperm
712 // CHECK-LE: @llvm.ppc.altivec.vperm
713 
714   /* vec_msub */
715   res_vf = vec_msub(vf, vf, vf);
716 // CHECK: fneg <4 x float> %{{[0-9]+}}
717 // CHECK-NEXT: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}}, <4 x float>
718 // CHECK-LE: fneg <4 x float> %{{[0-9]+}}
719 // CHECK-LE-NEXT: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}}, <4 x float>
720 
721   res_vd = vec_msub(vd, vd, vd);
722 // CHECK: fneg <2 x double> %{{[0-9]+}}
723 // CHECK-NEXT: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x double>
724 // CHECK-LE: fneg <2 x double> %{{[0-9]+}}
725 // CHECK-LE-NEXT: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x double>
726 
727   res_vsll = vec_mul(vsll, vsll);
728 // CHECK: mul <2 x i64>
729 // CHECK-LE: mul <2 x i64>
730 
731   res_vull = vec_mul(vull, vull);
732 // CHECK: mul <2 x i64>
733 // CHECK-LE: mul <2 x i64>
734 
735   res_vf = vec_mul(vf, vf);
736 // CHECK: fmul <4 x float> %{{[0-9]+}}, %{{[0-9]+}}
737 // CHECK-LE: fmul <4 x float> %{{[0-9]+}}, %{{[0-9]+}}
738 
739   res_vd = vec_mul(vd, vd);
740 // CHECK: fmul <2 x double> %{{[0-9]+}}, %{{[0-9]+}}
741 // CHECK-LE: fmul <2 x double> %{{[0-9]+}}, %{{[0-9]+}}
742 
743   res_vf = vec_nearbyint(vf);
744 // CHECK: call <4 x float> @llvm.round.v4f32(<4 x float> %{{[0-9]+}})
745 // CHECK-LE: call <4 x float> @llvm.round.v4f32(<4 x float> %{{[0-9]+}})
746 
747   res_vd = vec_nearbyint(vd);
748 // CHECK: call <2 x double> @llvm.round.v2f64(<2 x double> %{{[0-9]+}})
749 // CHECK-LE: call <2 x double> @llvm.round.v2f64(<2 x double> %{{[0-9]+}})
750 
751   res_vf = vec_nmadd(vf, vf, vf);
752 // CHECK: [[FM:[0-9]+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}})
753 // CHECK-NEXT: fneg <4 x float> %[[FM]]
754 // CHECK-LE: [[FM:[0-9]+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}})
755 // CHECK-LE-NEXT: fneg <4 x float> %[[FM]]
756 
757   res_vd = vec_nmadd(vd, vd, vd);
758 // CHECK: [[FM:[0-9]+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}})
759 // CHECK-NEXT: fneg <2 x double> %[[FM]]
760 // CHECK-LE: [[FM:[0-9]+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}})
761 // CHECK-LE-NEXT: fneg <2 x double> %[[FM]]
762 
763   res_vf = vec_nmsub(vf, vf, vf);
764 // CHECK: fneg <4 x float> %{{[0-9]+}}
765 // CHECK-NEXT: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}}, <4 x float>
766 // CHECK: fneg <4 x float> %{{[0-9]+}}
767 // CHECK-LE: fneg <4 x float> %{{[0-9]+}}
768 // CHECK-LE-NEXT: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}}, <4 x float>
769 // CHECK-LE: fneg <4 x float> %{{[0-9]+}}
770 
771   res_vd = vec_nmsub(vd, vd, vd);
772 // CHECK: fneg <2 x double> %{{[0-9]+}}
773 // CHECK-NEXT: [[FM:[0-9]+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x double>
774 // CHECK-NEXT: fneg <2 x double> %[[FM]]
775 // CHECK-LE: fneg <2 x double> %{{[0-9]+}}
776 // CHECK-LE-NEXT: [[FM:[0-9]+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x double>
777 // CHECK-LE-NEXT: fneg <2 x double> %[[FM]]
778 
779   /* vec_nor */
780   res_vsll = vec_nor(vsll, vsll);
781 // CHECK: or <2 x i64>
782 // CHECK: xor <2 x i64>
783 // CHECK-LE: or <2 x i64>
784 // CHECK-LE: xor <2 x i64>
785 
786   res_vull = vec_nor(vull, vull);
787 // CHECK: or <2 x i64>
788 // CHECK: xor <2 x i64>
789 // CHECK-LE: or <2 x i64>
790 // CHECK-LE: xor <2 x i64>
791 
792   res_vull = vec_nor(vbll, vbll);
793 // CHECK: or <2 x i64>
794 // CHECK: xor <2 x i64>
795 // CHECK-LE: or <2 x i64>
796 // CHECK-LE: xor <2 x i64>
797 
798   res_vd = vec_nor(vd, vd);
799 // CHECK: bitcast <2 x double> %{{[0-9]+}} to <2 x i64>
800 // CHECK: [[OR:%.+]] = or <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
801 // CHECK-NEXT: xor <2 x i64> [[OR]], <i64 -1, i64 -1>
802 // CHECK-LE: bitcast <2 x double> %{{[0-9]+}} to <2 x i64>
803 // CHECK-LE: [[OR:%.+]] = or <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
804 // CHECK-LE-NEXT: xor <2 x i64> [[OR]], <i64 -1, i64 -1>
805 
806   /* vec_or */
807   res_vsll = vec_or(vsll, vsll);
808 // CHECK: or <2 x i64>
809 // CHECK-LE: or <2 x i64>
810 
811   res_vsll = vec_or(vbll, vsll);
812 // CHECK: or <2 x i64>
813 // CHECK-LE: or <2 x i64>
814 
815   res_vsll = vec_or(vsll, vbll);
816 // CHECK: or <2 x i64>
817 // CHECK-LE: or <2 x i64>
818 
819   res_vull = vec_or(vull, vull);
820 // CHECK: or <2 x i64>
821 // CHECK-LE: or <2 x i64>
822 
823   res_vull = vec_or(vbll, vull);
824 // CHECK: or <2 x i64>
825 // CHECK-LE: or <2 x i64>
826 
827   res_vull = vec_or(vull, vbll);
828 // CHECK: or <2 x i64>
829 // CHECK-LE: or <2 x i64>
830 
831   res_vbll = vec_or(vbll, vbll);
832 // CHECK: or <2 x i64>
833 // CHECK-LE: or <2 x i64>
834 
835   res_vd = vec_or(vd, vd);
836 // CHECK: bitcast <2 x double> %{{[0-9]+}} to <2 x i64>
837 // CHECK: or <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
838 // CHECK-LE: bitcast <2 x double> %{{[0-9]+}} to <2 x i64>
839 // CHECK-LE: or <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
840 
841   res_vd = vec_or(vbll, vd);
842 // CHECK: [[T1:%.+]] = bitcast <2 x double> %{{[0-9]+}} to <2 x i64>
843 // CHECK: [[T2:%.+]] = or <2 x i64> %{{[0-9]+}}, [[T1]]
844 // CHECK: bitcast <2 x i64> [[T2]] to <2 x double>
845 // CHECK-LE: [[T1:%.+]] = bitcast <2 x double> %{{[0-9]+}} to <2 x i64>
846 // CHECK-LE: [[T2:%.+]] = or <2 x i64> %{{[0-9]+}}, [[T1]]
847 // CHECK-LE: bitcast <2 x i64> [[T2]] to <2 x double>
848 
849   res_vd = vec_or(vd, vbll);
850 // CHECK: [[T1:%.+]] = bitcast <2 x double> %{{[0-9]+}} to <2 x i64>
851 // CHECK: [[T2:%.+]] = or <2 x i64> [[T1]], %{{[0-9]+}}
852 // CHECK: bitcast <2 x i64> [[T2]] to <2 x double>
853 // CHECK-LE: [[T1:%.+]] = bitcast <2 x double> %{{[0-9]+}} to <2 x i64>
854 // CHECK-LE: [[T2:%.+]] = or <2 x i64> [[T1]], %{{[0-9]+}}
855 // CHECK-LE: bitcast <2 x i64> [[T2]] to <2 x double>
856 
857   res_vf = vec_re(vf);
858 // CHECK: call <4 x float> @llvm.ppc.vsx.xvresp(<4 x float>
859 // CHECK-LE: call <4 x float> @llvm.ppc.vsx.xvresp(<4 x float>
860 
861   res_vd = vec_re(vd);
862 // CHECK: call <2 x double> @llvm.ppc.vsx.xvredp(<2 x double>
863 // CHECK-LE: call <2 x double> @llvm.ppc.vsx.xvredp(<2 x double>
864 
865   res_vf = vec_rint(vf);
866 // CHECK: call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %{{[0-9]+}})
867 // CHECK-LE: call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %{{[0-9]+}})
868 
869   res_vd = vec_rint(vd);
870 // CHECK: call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %{{[0-9]+}})
871 // CHECK-LE: call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %{{[0-9]+}})
872 
873   res_vf = vec_rsqrte(vf);
874 // CHECK: call <4 x float> @llvm.ppc.vsx.xvrsqrtesp(<4 x float> %{{[0-9]+}})
875 // CHECK-LE: call <4 x float> @llvm.ppc.vsx.xvrsqrtesp(<4 x float> %{{[0-9]+}})
876 
877   res_vd = vec_rsqrte(vd);
878 // CHECK: call <2 x double> @llvm.ppc.vsx.xvrsqrtedp(<2 x double> %{{[0-9]+}})
879 // CHECK-LE: call <2 x double> @llvm.ppc.vsx.xvrsqrtedp(<2 x double> %{{[0-9]+}})
880 
881   dummy();
882 // CHECK: call void @dummy()
883 // CHECK-LE: call void @dummy()
884 
885   res_vd = vec_sel(vd, vd, vbll);
886 // CHECK: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
887 // CHECK: and <2 x i64> %{{[0-9]+}},
888 // CHECK: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
889 // CHECK: or <2 x i64>
890 // CHECK: bitcast <2 x i64> %{{[0-9]+}} to <2 x double>
891 // CHECK-LE: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
892 // CHECK-LE: and <2 x i64> %{{[0-9]+}},
893 // CHECK-LE: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
894 // CHECK-LE: or <2 x i64>
895 // CHECK-LE: bitcast <2 x i64> %{{[0-9]+}} to <2 x double>
896 
897   dummy();
898 // CHECK: call void @dummy()
899 // CHECK-LE: call void @dummy()
900 
901   res_vd = vec_sel(vd, vd, vull);
902 // CHECK: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
903 // CHECK: and <2 x i64> %{{[0-9]+}},
904 // CHECK: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
905 // CHECK: or <2 x i64>
906 // CHECK: bitcast <2 x i64> %{{[0-9]+}} to <2 x double>
907 // CHECK-LE: xor <2 x i64> %{{[0-9]+}}, <i64 -1, i64 -1>
908 // CHECK-LE: and <2 x i64> %{{[0-9]+}},
909 // CHECK-LE: and <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
910 // CHECK-LE: or <2 x i64>
911 // CHECK-LE: bitcast <2 x i64> %{{[0-9]+}} to <2 x double>
912 
913   res_vf = vec_sqrt(vf);
914 // CHECK: call <4 x float> @llvm.sqrt.v4f32(<4 x float> %{{[0-9]+}})
915 // CHECK-LE: call <4 x float> @llvm.sqrt.v4f32(<4 x float> %{{[0-9]+}})
916 
917   res_vd = vec_sqrt(vd);
918 // CHECK: call <2 x double> @llvm.sqrt.v2f64(<2 x double> %{{[0-9]+}})
919 // CHECK-LE: call <2 x double> @llvm.sqrt.v2f64(<2 x double> %{{[0-9]+}})
920 
921   res_vd = vec_sub(vd, vd);
922 // CHECK: fsub <2 x double> %{{[0-9]+}}, %{{[0-9]+}}
923 // CHECK-LE: fsub <2 x double> %{{[0-9]+}}, %{{[0-9]+}}
924 
925   res_vf = vec_trunc(vf);
926 // CHECK: call <4 x float> @llvm.trunc.v4f32(<4 x float> %{{[0-9]+}})
927 // CHECK-LE: call <4 x float> @llvm.trunc.v4f32(<4 x float> %{{[0-9]+}})
928 
929   res_vd = vec_trunc(vd);
930 // CHECK: call <2 x double> @llvm.trunc.v2f64(<2 x double> %{{[0-9]+}})
931 // CHECK-LE: call <2 x double> @llvm.trunc.v2f64(<2 x double> %{{[0-9]+}})
932 
933   /* vec_vor */
934   res_vsll = vec_vor(vsll, vsll);
935 // CHECK: or <2 x i64>
936 // CHECK-LE: or <2 x i64>
937 
938   res_vsll = vec_vor(vbll, vsll);
939 // CHECK: or <2 x i64>
940 // CHECK-LE: or <2 x i64>
941 
942   res_vsll = vec_vor(vsll, vbll);
943 // CHECK: or <2 x i64>
944 // CHECK-LE: or <2 x i64>
945 
946   res_vull = vec_vor(vull, vull);
947 // CHECK: or <2 x i64>
948 // CHECK-LE: or <2 x i64>
949 
950   res_vull = vec_vor(vbll, vull);
951 // CHECK: or <2 x i64>
952 // CHECK-LE: or <2 x i64>
953 
954   res_vull = vec_vor(vull, vbll);
955 // CHECK: or <2 x i64>
956 // CHECK-LE: or <2 x i64>
957 
958   res_vbll = vec_vor(vbll, vbll);
959 // CHECK: or <2 x i64>
960 // CHECK-LE: or <2 x i64>
961 
962   /* vec_xor */
963   res_vsll = vec_xor(vsll, vsll);
964 // CHECK: xor <2 x i64>
965 // CHECK-LE: xor <2 x i64>
966 
967   res_vsll = vec_xor(vbll, vsll);
968 // CHECK: xor <2 x i64>
969 // CHECK-LE: xor <2 x i64>
970 
971   res_vsll = vec_xor(vsll, vbll);
972 // CHECK: xor <2 x i64>
973 // CHECK-LE: xor <2 x i64>
974 
975   res_vull = vec_xor(vull, vull);
976 // CHECK: xor <2 x i64>
977 // CHECK-LE: xor <2 x i64>
978 
979   res_vull = vec_xor(vbll, vull);
980 // CHECK: xor <2 x i64>
981 // CHECK-LE: xor <2 x i64>
982 
983   res_vull = vec_xor(vull, vbll);
984 // CHECK: xor <2 x i64>
985 // CHECK-LE: xor <2 x i64>
986 
987   res_vbll = vec_xor(vbll, vbll);
988 // CHECK: xor <2 x i64>
989 // CHECK-LE: xor <2 x i64>
990 
991   dummy();
992 // CHECK: call void @dummy()
993 // CHECK-LE: call void @dummy()
994 
995   res_vd = vec_xor(vd, vd);
996 // CHECK: [[X1:%.+]] = xor <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
997 // CHECK: bitcast <2 x i64> [[X1]] to <2 x double>
998 // CHECK-LE: [[X1:%.+]] = xor <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
999 // CHECK-LE: bitcast <2 x i64> [[X1]] to <2 x double>
1000 
1001   dummy();
1002 // CHECK: call void @dummy()
1003 // CHECK-LE: call void @dummy()
1004 
1005   res_vd = vec_xor(vd, vbll);
1006 // CHECK: [[X1:%.+]] = xor <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
1007 // CHECK: bitcast <2 x i64> [[X1]] to <2 x double>
1008 // CHECK-LE: [[X1:%.+]] = xor <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
1009 // CHECK-LE: bitcast <2 x i64> [[X1]] to <2 x double>
1010 
1011   dummy();
1012 // CHECK: call void @dummy()
1013 // CHECK-LE: call void @dummy()
1014 
1015   res_vd = vec_xor(vbll, vd);
1016 // CHECK: [[X1:%.+]] = xor <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
1017 // CHECK: bitcast <2 x i64> [[X1]] to <2 x double>
1018 // CHECK-LE: [[X1:%.+]] = xor <2 x i64> %{{[0-9]+}}, %{{[0-9]+}}
1019 // CHECK-LE: bitcast <2 x i64> [[X1]] to <2 x double>
1020 
1021   /* vec_vxor */
1022   res_vsll = vec_vxor(vsll, vsll);
1023 // CHECK: xor <2 x i64>
1024 // CHECK-LE: xor <2 x i64>
1025 
1026   res_vsll = vec_vxor(vbll, vsll);
1027 // CHECK: xor <2 x i64>
1028 // CHECK-LE: xor <2 x i64>
1029 
1030   res_vsll = vec_vxor(vsll, vbll);
1031 // CHECK: xor <2 x i64>
1032 // CHECK-LE: xor <2 x i64>
1033 
1034   res_vull = vec_vxor(vull, vull);
1035 // CHECK: xor <2 x i64>
1036 // CHECK-LE: xor <2 x i64>
1037 
1038   res_vull = vec_vxor(vbll, vull);
1039 // CHECK: xor <2 x i64>
1040 // CHECK-LE: xor <2 x i64>
1041 
1042   res_vull = vec_vxor(vull, vbll);
1043 // CHECK: xor <2 x i64>
1044 // CHECK-LE: xor <2 x i64>
1045 
1046   res_vbll = vec_vxor(vbll, vbll);
1047 // CHECK: xor <2 x i64>
1048 // CHECK-LE: xor <2 x i64>
1049 
1050   res_vsll = vec_cts(vd, 0);
1051 // CHECK: fmul <2 x double>
1052 // CHECK: fptosi <2 x double> %{{.*}} to <2 x i64>
1053 // CHECK-LE: fmul <2 x double>
1054 // CHECK-LE: fptosi <2 x double> %{{.*}} to <2 x i64>
1055 
1056   res_vsll = vec_cts(vd, 31);
1057 // CHECK: fmul <2 x double>
1058 // CHECK: fptosi <2 x double> %{{.*}} to <2 x i64>
1059 // CHECK-LE: fmul <2 x double>
1060 // CHECK-LE: fptosi <2 x double> %{{.*}} to <2 x i64>
1061 
1062   res_vsll = vec_ctu(vd, 0);
1063 // CHECK: fmul <2 x double>
1064 // CHECK: fptoui <2 x double> %{{.*}} to <2 x i64>
1065 // CHECK-LE: fmul <2 x double>
1066 // CHECK-LE: fptoui <2 x double> %{{.*}} to <2 x i64>
1067 
1068   res_vsll = vec_ctu(vd, 31);
1069 // CHECK: fmul <2 x double>
1070 // CHECK: fptoui <2 x double> %{{.*}} to <2 x i64>
1071 // CHECK-LE: fmul <2 x double>
1072 // CHECK-LE: fptoui <2 x double> %{{.*}} to <2 x i64>
1073 
1074   res_vd = vec_ctf(vsll, 0);
1075 // CHECK: sitofp <2 x i64> %{{.*}} to <2 x double>
1076 // CHECK: fmul <2 x double>
1077 // CHECK-LE: sitofp <2 x i64> %{{.*}} to <2 x double>
1078 // CHECK-LE: fmul <2 x double>
1079 
1080   res_vd = vec_ctf(vsll, 31);
1081 // CHECK: sitofp <2 x i64> %{{.*}} to <2 x double>
1082 // CHECK: fmul <2 x double>
1083 // CHECK-LE: sitofp <2 x i64> %{{.*}} to <2 x double>
1084 // CHECK-LE: fmul <2 x double>
1085 
1086   res_vd = vec_ctf(vull, 0);
1087 // CHECK: uitofp <2 x i64> %{{.*}} to <2 x double>
1088 // CHECK: fmul <2 x double>
1089 // CHECK-LE: uitofp <2 x i64> %{{.*}} to <2 x double>
1090 // CHECK-LE: fmul <2 x double>
1091 
1092   res_vd = vec_ctf(vull, 31);
1093 // CHECK: uitofp <2 x i64> %{{.*}} to <2 x double>
1094 // CHECK: fmul <2 x double>
1095 // CHECK-LE: uitofp <2 x i64> %{{.*}} to <2 x double>
1096 // CHECK-LE: fmul <2 x double>
1097 
1098   res_vsll = vec_signed(vd);
1099 // CHECK: fptosi <2 x double>
1100 // CHECK-LE: fptosi <2 x double>
1101 
1102   res_vsi = vec_signed2(vd, vd);
1103 // CHECK: extractelement <2 x double>
1104 // CHECK: fptosi double
1105 // CHECK: insertelement <4 x i32>
1106 // CHECK: extractelement <2 x double>
1107 // CHECK: fptosi double
1108 // CHECK: insertelement <4 x i32>
1109 // CHECK: extractelement <2 x double>
1110 // CHECK: fptosi double
1111 // CHECK: insertelement <4 x i32>
1112 // CHECK: extractelement <2 x double>
1113 // CHECK: fptosi double
1114 // CHECK: insertelement <4 x i32>
1115 // CHECK-LE: extractelement <2 x double>
1116 // CHECK-LE: fptosi double
1117 // CHECK-LE: insertelement <4 x i32>
1118 // CHECK-LE: extractelement <2 x double>
1119 // CHECK-LE: fptosi double
1120 // CHECK-LE: insertelement <4 x i32>
1121 // CHECK-LE: extractelement <2 x double>
1122 // CHECK-LE: fptosi double
1123 // CHECK-LE: insertelement <4 x i32>
1124 // CHECK-LE: extractelement <2 x double>
1125 // CHECK-LE: fptosi double
1126 // CHECK-LE: insertelement <4 x i32>
1127 
1128   res_vsi = vec_signede(vd);
1129 // CHECK: @llvm.ppc.vsx.xvcvdpsxws(<2 x double>
1130 // CHECK-LE: @llvm.ppc.vsx.xvcvdpsxws(<2 x double>
1131 // CHECK-LE: sub nsw i32 16
1132 // CHECK-LE: sub nsw i32 17
1133 // CHECK-LE: sub nsw i32 18
1134 // CHECK-LE: sub nsw i32 31
1135 // CHECK-LE: @llvm.ppc.altivec.vperm
1136 
1137   res_vsi = vec_signedo(vd);
1138 // CHECK: @llvm.ppc.vsx.xvcvdpsxws(<2 x double>
1139 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
1140 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
1141 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
1142 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
1143 // CHECK: @llvm.ppc.altivec.vperm
1144 // CHECK-LE: @llvm.ppc.vsx.xvcvdpsxws(<2 x double>
1145 
1146   res_vull = vec_unsigned(vd);
1147 // CHECK: fptoui <2 x double>
1148 // CHECK-LE: fptoui <2 x double>
1149 
1150   res_vui = vec_unsigned2(vd, vd);
1151 // CHECK: extractelement <2 x double>
1152 // CHECK: fptoui double
1153 // CHECK: insertelement <4 x i32>
1154 // CHECK: extractelement <2 x double>
1155 // CHECK: fptoui double
1156 // CHECK: insertelement <4 x i32>
1157 // CHECK: extractelement <2 x double>
1158 // CHECK: fptoui double
1159 // CHECK: insertelement <4 x i32>
1160 // CHECK: extractelement <2 x double>
1161 // CHECK: fptoui double
1162 // CHECK: insertelement <4 x i32>
1163 // CHECK-LE: extractelement <2 x double>
1164 // CHECK-LE: fptoui double
1165 // CHECK-LE: insertelement <4 x i32>
1166 // CHECK-LE: extractelement <2 x double>
1167 // CHECK-LE: fptoui double
1168 // CHECK-LE: insertelement <4 x i32>
1169 // CHECK-LE: extractelement <2 x double>
1170 // CHECK-LE: fptoui double
1171 // CHECK-LE: insertelement <4 x i32>
1172 // CHECK-LE: extractelement <2 x double>
1173 // CHECK-LE: fptoui double
1174 // CHECK-LE: insertelement <4 x i32>
1175 
1176   res_vui = vec_unsignede(vd);
1177 // CHECK: @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
1178 // CHECK-LE: @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
1179 // CHECK-LE: sub nsw i32 16
1180 // CHECK-LE: sub nsw i32 17
1181 // CHECK-LE: sub nsw i32 18
1182 // CHECK-LE: sub nsw i32 31
1183 // CHECK-LE: @llvm.ppc.altivec.vperm
1184 
1185   res_vui = vec_unsignedo(vd);
1186 // CHECK: @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
1187 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
1188 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
1189 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
1190 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
1191 // CHECK: @llvm.ppc.altivec.vperm
1192 // CHECK-LE: @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
1193 
1194   res_vf = vec_float2(vsll, vsll);
1195 // CHECK: extractelement <2 x i64>
1196 // CHECK: sitofp i64
1197 // CHECK: insertelement <4 x float>
1198 // CHECK: extractelement <2 x i64>
1199 // CHECK: sitofp i64
1200 // CHECK: insertelement <4 x float>
1201 // CHECK: extractelement <2 x i64>
1202 // CHECK: sitofp i64
1203 // CHECK: insertelement <4 x float>
1204 // CHECK: extractelement <2 x i64>
1205 // CHECK: sitofp i64
1206 // CHECK: insertelement <4 x float>
1207 // CHECK-LE: extractelement <2 x i64>
1208 // CHECK-LE: sitofp i64
1209 // CHECK-LE: insertelement <4 x float>
1210 // CHECK-LE: extractelement <2 x i64>
1211 // CHECK-LE: sitofp i64
1212 // CHECK-LE: insertelement <4 x float>
1213 // CHECK-LE: extractelement <2 x i64>
1214 // CHECK-LE: sitofp i64
1215 // CHECK-LE: insertelement <4 x float>
1216 // CHECK-LE: extractelement <2 x i64>
1217 // CHECK-LE: sitofp i64
1218 // CHECK-LE: insertelement <4 x float>
1219 
1220   res_vf = vec_float2(vull, vull);
1221 // CHECK: extractelement <2 x i64>
1222 // CHECK: uitofp i64
1223 // CHECK: insertelement <4 x float>
1224 // CHECK: extractelement <2 x i64>
1225 // CHECK: uitofp i64
1226 // CHECK: insertelement <4 x float>
1227 // CHECK: extractelement <2 x i64>
1228 // CHECK: uitofp i64
1229 // CHECK: insertelement <4 x float>
1230 // CHECK: extractelement <2 x i64>
1231 // CHECK: uitofp i64
1232 // CHECK: insertelement <4 x float>
1233 // CHECK-LE: extractelement <2 x i64>
1234 // CHECK-LE: uitofp i64
1235 // CHECK-LE: insertelement <4 x float>
1236 // CHECK-LE: extractelement <2 x i64>
1237 // CHECK-LE: uitofp i64
1238 // CHECK-LE: insertelement <4 x float>
1239 // CHECK-LE: extractelement <2 x i64>
1240 // CHECK-LE: uitofp i64
1241 // CHECK-LE: insertelement <4 x float>
1242 // CHECK-LE: extractelement <2 x i64>
1243 // CHECK-LE: uitofp i64
1244 // CHECK-LE: insertelement <4 x float>
1245 
1246   res_vf = vec_float2(vd, vd);
1247 // CHECK: extractelement <2 x double>
1248 // CHECK: fptrunc double
1249 // CHECK: insertelement <4 x float>
1250 // CHECK: extractelement <2 x double>
1251 // CHECK: fptrunc double
1252 // CHECK: insertelement <4 x float>
1253 // CHECK: extractelement <2 x double>
1254 // CHECK: fptrunc double
1255 // CHECK: insertelement <4 x float>
1256 // CHECK: extractelement <2 x double>
1257 // CHECK: fptrunc double
1258 // CHECK: insertelement <4 x float>
1259 // CHECK-LE: extractelement <2 x double>
1260 // CHECK-LE: fptrunc double
1261 // CHECK-LE: insertelement <4 x float>
1262 // CHECK-LE: extractelement <2 x double>
1263 // CHECK-LE: fptrunc double
1264 // CHECK-LE: insertelement <4 x float>
1265 // CHECK-LE: extractelement <2 x double>
1266 // CHECK-LE: fptrunc double
1267 // CHECK-LE: insertelement <4 x float>
1268 // CHECK-LE: extractelement <2 x double>
1269 // CHECK-LE: fptrunc double
1270 // CHECK-LE: insertelement <4 x float>
1271 
1272   res_vf = vec_floate(vsll);
1273 // CHECK: @llvm.ppc.vsx.xvcvsxdsp
1274 // CHECK-LE: @llvm.ppc.vsx.xvcvsxdsp
1275 // CHECK-LE: sub nsw i32 16
1276 // CHECK-LE: sub nsw i32 17
1277 // CHECK-LE: sub nsw i32 18
1278 // CHECK-LE: sub nsw i32 31
1279 // CHECK-LE: @llvm.ppc.altivec.vperm
1280 
1281   res_vf = vec_floate(vull);
1282 // CHECK: @llvm.ppc.vsx.xvcvuxdsp
1283 // CHECK-LE: @llvm.ppc.vsx.xvcvuxdsp
1284 // CHECK-LE: sub nsw i32 16
1285 // CHECK-LE: sub nsw i32 17
1286 // CHECK-LE: sub nsw i32 18
1287 // CHECK-LE: sub nsw i32 31
1288 // CHECK-LE: @llvm.ppc.altivec.vperm
1289 
1290   res_vf = vec_floate(vd);
1291 // CHECK: @llvm.ppc.vsx.xvcvdpsp
1292 // CHECK-LE: @llvm.ppc.vsx.xvcvdpsp
1293 // CHECK-LE: sub nsw i32 16
1294 // CHECK-LE: sub nsw i32 17
1295 // CHECK-LE: sub nsw i32 18
1296 // CHECK-LE: sub nsw i32 31
1297 // CHECK-LE: @llvm.ppc.altivec.vperm
1298 
1299   res_vf = vec_floato(vsll);
1300 // CHECK: @llvm.ppc.vsx.xvcvsxdsp
1301 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
1302 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
1303 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
1304 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
1305 // CHECK: @llvm.ppc.altivec.vperm
1306 // CHECK-LE: @llvm.ppc.vsx.xvcvsxdsp
1307 
1308   res_vf = vec_floato(vull);
1309 // CHECK: @llvm.ppc.vsx.xvcvuxdsp
1310 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
1311 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
1312 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
1313 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
1314 // CHECK: @llvm.ppc.altivec.vperm
1315 // CHECK-LE: @llvm.ppc.vsx.xvcvuxdsp
1316 
1317   res_vf = vec_floato(vd);
1318 // CHECK: @llvm.ppc.vsx.xvcvdpsp
1319 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
1320 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
1321 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
1322 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
1323 // CHECK: @llvm.ppc.altivec.vperm
1324 // CHECK-LE: @llvm.ppc.vsx.xvcvdpsp
1325 
1326   res_vd = vec_double(vsll);
1327 // CHECK: sitofp <2 x i64>
1328 // CHECK-LE: sitofp <2 x i64>
1329 
1330   res_vd = vec_double(vull);
1331 // CHECK: uitofp <2 x i64>
1332 // CHECK-LE: uitofp <2 x i64>
1333 
1334   res_vd = vec_doublee(vsi);
1335 // CHECK: @llvm.ppc.vsx.xvcvsxwdp(<4 x i32
1336 // CHECK-LE: sub nsw i32 16
1337 // CHECK-LE: sub nsw i32 17
1338 // CHECK-LE: sub nsw i32 18
1339 // CHECK-LE: sub nsw i32 31
1340 // CHECK-LE: @llvm.ppc.altivec.vperm
1341 // CHECK-LE: @llvm.ppc.vsx.xvcvsxwdp(<4 x i32
1342 
1343   res_vd = vec_doublee(vui);
1344 // CHECK: @llvm.ppc.vsx.xvcvuxwdp(<4 x i32
1345 // CHECK-LE: sub nsw i32 16
1346 // CHECK-LE: sub nsw i32 17
1347 // CHECK-LE: sub nsw i32 18
1348 // CHECK-LE: sub nsw i32 31
1349 // CHECK-LE: @llvm.ppc.altivec.vperm
1350 // CHECK-LE: @llvm.ppc.vsx.xvcvuxwdp(<4 x i32
1351 
1352   res_vd = vec_doublee(vf);
1353 // CHECK: @llvm.ppc.vsx.xvcvspdp(<4 x float
1354 // CHECK-LE: sub nsw i32 16
1355 // CHECK-LE: sub nsw i32 17
1356 // CHECK-LE: sub nsw i32 18
1357 // CHECK-LE: sub nsw i32 31
1358 // CHECK-LE: @llvm.ppc.altivec.vperm
1359 // CHECK-LE: @llvm.ppc.vsx.xvcvspdp(<4 x float
1360 
1361   res_vd = vec_doubleh(vsi);
1362 // CHECK: extractelement <4 x i32>
1363 // CHECK: sitofp i32
1364 // CHECK: insertelement <2 x double>
1365 // CHECK: extractelement <4 x i32>
1366 // CHECK: sitofp i32
1367 // CHECK: insertelement <2 x double>
1368 // CHECK-LE: extractelement <4 x i32>
1369 // CHECK-LE: sitofp i32
1370 // CHECK-LE: insertelement <2 x double>
1371 // CHECK-LE: extractelement <4 x i32>
1372 // CHECK-LE: sitofp i32
1373 // CHECK-LE: insertelement <2 x double>
1374 
1375   res_vd = vec_doubleh(vui);
1376 // CHECK: extractelement <4 x i32>
1377 // CHECK: uitofp i32
1378 // CHECK: insertelement <2 x double>
1379 // CHECK: extractelement <4 x i32>
1380 // CHECK: uitofp i32
1381 // CHECK: insertelement <2 x double>
1382 // CHECK-LE: extractelement <4 x i32>
1383 // CHECK-LE: uitofp i32
1384 // CHECK-LE: insertelement <2 x double>
1385 // CHECK-LE: extractelement <4 x i32>
1386 // CHECK-LE: uitofp i32
1387 // CHECK-LE: insertelement <2 x double>
1388 
1389   res_vd = vec_doubleh(vf);
1390 // CHECK: extractelement <4 x float>
1391 // CHECK: fpext float
1392 // CHECK: insertelement <2 x double>
1393 // CHECK: extractelement <4 x float>
1394 // CHECK: fpext float
1395 // CHECK: insertelement <2 x double>
1396 // CHECK-LE: extractelement <4 x float>
1397 // CHECK-LE: fpext float
1398 // CHECK-LE: insertelement <2 x double>
1399 // CHECK-LE: extractelement <4 x float>
1400 // CHECK-LE: fpext float
1401 // CHECK-LE: insertelement <2 x double>
1402 
1403   res_vd = vec_doublel(vsi);
1404 // CHECK: extractelement <4 x i32>
1405 // CHECK: sitofp i32
1406 // CHECK: insertelement <2 x double>
1407 // CHECK: extractelement <4 x i32>
1408 // CHECK: sitofp i32
1409 // CHECK: insertelement <2 x double>
1410 // CHECK-LE: extractelement <4 x i32>
1411 // CHECK-LE: sitofp i32
1412 // CHECK-LE: insertelement <2 x double>
1413 // CHECK-LE: extractelement <4 x i32>
1414 // CHECK-LE: sitofp i32
1415 // CHECK-LE: insertelement <2 x double>
1416 
1417   res_vd = vec_doublel(vui);
1418 // CHECK: extractelement <4 x i32>
1419 // CHECK: uitofp i32
1420 // CHECK: insertelement <2 x double>
1421 // CHECK: extractelement <4 x i32>
1422 // CHECK: uitofp i32
1423 // CHECK: insertelement <2 x double>
1424 // CHECK-LE: extractelement <4 x i32>
1425 // CHECK-LE: uitofp i32
1426 // CHECK-LE: insertelement <2 x double>
1427 // CHECK-LE: extractelement <4 x i32>
1428 // CHECK-LE: uitofp i32
1429 // CHECK-LE: insertelement <2 x double>
1430 
1431   res_vd = vec_doublel(vf);
1432 // CHECK: extractelement <4 x float>
1433 // CHECK: fpext float
1434 // CHECK: insertelement <2 x double>
1435 // CHECK: extractelement <4 x float>
1436 // CHECK: fpext float
1437 // CHECK: insertelement <2 x double>
1438 // CHECK-LE: extractelement <4 x float>
1439 // CHECK-LE: fpext float
1440 // CHECK-LE: insertelement <2 x double>
1441 // CHECK-LE: extractelement <4 x float>
1442 // CHECK-LE: fpext float
1443 // CHECK-LE: insertelement <2 x double>
1444 
1445   res_vd = vec_doubleo(vsi);
1446 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
1447 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
1448 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
1449 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
1450 // CHECK: @llvm.ppc.altivec.vperm
1451 // CHECK: @llvm.ppc.vsx.xvcvsxwdp(<4 x i32>
1452 // CHECK-LE: @llvm.ppc.vsx.xvcvsxwdp(<4 x i32>
1453 
1454   res_vd = vec_doubleo(vui);
1455 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
1456 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
1457 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
1458 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
1459 // CHECK: @llvm.ppc.altivec.vperm
1460 // CHECK: @llvm.ppc.vsx.xvcvuxwdp(<4 x i32>
1461 // CHECK-LE: @llvm.ppc.vsx.xvcvuxwdp(<4 x i32>
1462 
1463   res_vd = vec_doubleo(vf);
1464 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
1465 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
1466 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
1467 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
1468 // CHECK: @llvm.ppc.altivec.vperm
1469 // CHECK: @llvm.ppc.vsx.xvcvspdp(<4 x float>
1470 // CHECK-LE: @llvm.ppc.vsx.xvcvspdp(<4 x float>
1471 
1472   res_vbll = vec_reve(vbll);
1473 // CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 0>
1474 // CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 0>
1475 
1476   res_vsll = vec_reve(vsll);
1477 // CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 0>
1478 // CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 0>
1479 
1480   res_vull = vec_reve(vull);
1481 // CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 0>
1482 // CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 0>
1483 
1484   res_vd = vec_reve(vd);
1485 // CHECK: shufflevector <2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x i32> <i32 1, i32 0>
1486 // CHECK-LE: shufflevector <2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x i32> <i32 1, i32 0>
1487 
1488   res_vbll = vec_revb(vbll);
1489 // CHECK: store <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>, <16 x i8>* {{%.+}}, align 16
1490 // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
1491 // CHECK-LE: store <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>, <16 x i8>* {{%.+}}, align 16
1492 // CHECK-LE: store <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8>* {{%.+}}, align 16
1493 // CHECK-LE: xor <16 x i8>
1494 // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
1495 
1496   res_vsll = vec_revb(vsll);
1497 // CHECK: store <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>, <16 x i8>* {{%.+}}, align 16
1498 // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
1499 // CHECK-LE: store <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>, <16 x i8>* {{%.+}}, align 16
1500 // CHECK-LE: store <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8>* {{%.+}}, align 16
1501 // CHECK-LE: xor <16 x i8>
1502 // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
1503 
1504   res_vull = vec_revb(vull);
1505 // CHECK: store <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>, <16 x i8>* {{%.+}}, align 16
1506 // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
1507 // CHECK-LE: store <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>, <16 x i8>* {{%.+}}, align 16
1508 // CHECK-LE: store <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8>* {{%.+}}, align 16
1509 // CHECK-LE: xor <16 x i8>
1510 // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
1511 
1512   res_vd = vec_revb(vd);
1513 // CHECK: store <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>, <16 x i8>* {{%.+}}, align 16
1514 // CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
1515 // CHECK-LE: store <16 x i8> <i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8>, <16 x i8>* {{%.+}}, align 16
1516 // CHECK-LE: store <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8>* {{%.+}}, align 16
1517 // CHECK-LE: xor <16 x i8>
1518 // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
1519 
1520   res_vbll = vec_sld(vbll, vbll, 0);
1521 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
1522 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
1523 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
1524 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
1525 // CHECK: @llvm.ppc.altivec.vperm
1526 // CHECK-LE: sub nsw i32 16
1527 // CHECK-LE: sub nsw i32 17
1528 // CHECK-LE: sub nsw i32 18
1529 // CHECK-LE: sub nsw i32 31
1530 // CHECK-LE: @llvm.ppc.altivec.vperm
1531 
1532   res_vsll = vec_sld(vsll, vsll, 0);
1533 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
1534 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
1535 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
1536 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
1537 // CHECK: @llvm.ppc.altivec.vperm
1538 // CHECK-LE: sub nsw i32 16
1539 // CHECK-LE: sub nsw i32 17
1540 // CHECK-LE: sub nsw i32 18
1541 // CHECK-LE: sub nsw i32 31
1542 // CHECK-LE: @llvm.ppc.altivec.vperm
1543 
1544   res_vull = vec_sld(vull, vull, 0);
1545 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
1546 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
1547 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
1548 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
1549 // CHECK: @llvm.ppc.altivec.vperm
1550 // CHECK-LE: sub nsw i32 16
1551 // CHECK-LE: sub nsw i32 17
1552 // CHECK-LE: sub nsw i32 18
1553 // CHECK-LE: sub nsw i32 31
1554 // CHECK-LE: @llvm.ppc.altivec.vperm
1555 
1556   res_vd = vec_sld(vd, vd, 0);
1557 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
1558 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
1559 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
1560 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
1561 // CHECK: @llvm.ppc.altivec.vperm
1562 // CHECK-LE: sub nsw i32 16
1563 // CHECK-LE: sub nsw i32 17
1564 // CHECK-LE: sub nsw i32 18
1565 // CHECK-LE: sub nsw i32 31
1566 // CHECK-LE: @llvm.ppc.altivec.vperm
1567 
1568   res_vsll = vec_sldw(vsll, vsll, 0);
1569 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
1570 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
1571 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
1572 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
1573 // CHECK: @llvm.ppc.altivec.vperm
1574 // CHECK-LE: sub nsw i32 16
1575 // CHECK-LE: sub nsw i32 17
1576 // CHECK-LE: sub nsw i32 18
1577 // CHECK-LE: sub nsw i32 31
1578 // CHECK-LE: @llvm.ppc.altivec.vperm
1579 
1580   res_vull = vec_sldw(vull, vull, 0);
1581 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
1582 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
1583 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
1584 // CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
1585 // CHECK: @llvm.ppc.altivec.vperm
1586 // CHECK-LE: sub nsw i32 16
1587 // CHECK-LE: sub nsw i32 17
1588 // CHECK-LE: sub nsw i32 18
1589 // CHECK-LE: sub nsw i32 31
1590 // CHECK-LE: @llvm.ppc.altivec.vperm
1591 
1592   res_vsll = vec_sll(vsll, vuc);
1593 // CHECK: @llvm.ppc.altivec.vsl
1594 // CHECK-LE: @llvm.ppc.altivec.vsl
1595 
1596 res_vull = vec_sll(vull, vuc);
1597 // CHECK: @llvm.ppc.altivec.vsl
1598 // CHECK-LE: @llvm.ppc.altivec.vsl
1599 
1600 res_vsll = vec_slo(vsll, vsc);
1601 // CHECK: @llvm.ppc.altivec.vslo
1602 // CHECK-LE: @llvm.ppc.altivec.vslo
1603 
1604   res_vsll = vec_slo(vsll, vuc);
1605 // CHECK: @llvm.ppc.altivec.vslo
1606 // CHECK-LE: @llvm.ppc.altivec.vslo
1607 
1608   res_vull = vec_slo(vull, vsc);
1609 // CHECK: @llvm.ppc.altivec.vslo
1610 // CHECK-LE: @llvm.ppc.altivec.vslo
1611 
1612   res_vull = vec_slo(vull, vuc);
1613 // CHECK: @llvm.ppc.altivec.vslo
1614 // CHECK-LE: @llvm.ppc.altivec.vslo
1615 
1616   res_vsll = vec_srl(vsll, vuc);
1617 // CHECK: @llvm.ppc.altivec.vsr
1618 // CHECK-LE: @llvm.ppc.altivec.vsr
1619 
1620   res_vull = vec_srl(vull, vuc);
1621 // CHECK: @llvm.ppc.altivec.vsr
1622 // CHECK-LE: @llvm.ppc.altivec.vsr
1623 
1624   res_vsll = vec_sro(vsll, vsc);
1625 // CHECK: @llvm.ppc.altivec.vsro
1626 // CHECK-LE: @llvm.ppc.altivec.vsro
1627 
1628   res_vsll = vec_sro(vsll, vuc);
1629 // CHECK: @llvm.ppc.altivec.vsro
1630 // CHECK-LE: @llvm.ppc.altivec.vsro
1631 
1632   res_vull = vec_sro(vull, vsc);
1633 // CHECK: @llvm.ppc.altivec.vsro
1634 // CHECK-LE: @llvm.ppc.altivec.vsro
1635 
1636   res_vull = vec_sro(vull, vuc);
1637 // CHECK: @llvm.ppc.altivec.vsro
1638 // CHECK-LE: @llvm.ppc.altivec.vsro
1639 
1640 res_vsll = vec_xl(sll, asll);
1641 // CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 1
1642 // CHECK-LE: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 1
1643 
1644 res_vull = vec_xl(sll, aull);
1645 // CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 1
1646 // CHECK-LE: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 1
1647 
1648 res_vd = vec_xl(sll, ad);
1649 // CHECK: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 1
1650 // CHECK-LE: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 1
1651 
1652 vec_xst(vsll, sll, asll);
1653 // CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 1
1654 // CHECK-LE: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 1
1655 
1656 vec_xst(vull, sll, aull);
1657 // CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 1
1658 // CHECK-LE: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 1
1659 
1660 vec_xst(vd, sll, ad);
1661 // CHECK: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 1
1662 // CHECK-LE: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 1
1663 
1664 res_vsll = vec_xl_be(sll, asll);
1665 // CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 1
1666 // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}})
1667 
1668 res_vull = vec_xl_be(sll, aull);
1669 // CHECK: load <2 x i64>, <2 x i64>* %{{[0-9]+}}, align 1
1670 // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}})
1671 
1672 res_vd = vec_xl_be(sll, ad);
1673 // CHECK: load <2 x double>, <2 x double>* %{{[0-9]+}}, align 1
1674 // CHECK-LE: call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %{{[0-9]+}})
1675 
1676 vec_xst_be(vsll, sll, asll);
1677 // CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 1
1678 // CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}})
1679 
1680 vec_xst_be(vull, sll, aull);
1681 // CHECK: store <2 x i64> %{{[0-9]+}}, <2 x i64>* %{{[0-9]+}}, align 1
1682 // CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}})
1683 
1684 vec_xst_be(vd, sll, ad);
1685 // CHECK: store <2 x double> %{{[0-9]+}}, <2 x double>* %{{[0-9]+}}, align 1
1686 // CHECK-LE: call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %{{[0-9]+}}, i8* %{{[0-9]+}})
1687 
1688   res_vf = vec_neg(vf);
1689 // CHECK: fneg <4 x float> {{%[0-9]+}}
1690 // CHECK-LE: fneg <4 x float> {{%[0-9]+}}
1691 
1692   res_vd = vec_neg(vd);
1693 // CHECK: fneg <2 x double> {{%[0-9]+}}
1694 // CHECK-LE: fneg <2 x double> {{%[0-9]+}}
1695 
1696 res_vd = vec_xxpermdi(vd, vd, 0);
1697 // CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 2>
1698 // CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 2>
1699 
1700 res_vf = vec_xxpermdi(vf, vf, 1);
1701 // CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 3>
1702 // CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 3>
1703 
1704 res_vsll = vec_xxpermdi(vsll, vsll, 2);
1705 // CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 2>
1706 // CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 2>
1707 
1708 res_vull = vec_xxpermdi(vull, vull, 3);
1709 // CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 3>
1710 // CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 3>
1711 
1712 res_vsi = vec_xxpermdi(vsi, vsi, 0);
1713 // CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 2>
1714 // CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 2>
1715 
1716 res_vui = vec_xxpermdi(vui, vui, 1);
1717 // CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 3>
1718 // CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 3>
1719 
1720 res_vss = vec_xxpermdi(vss, vss, 2);
1721 // CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 2>
1722 // CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 2>
1723 
1724 res_vus = vec_xxpermdi(vus, vus, 3);
1725 // CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 3>
1726 // CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 3>
1727 
1728 res_vsc = vec_xxpermdi(vsc, vsc, 0);
1729 // CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 2>
1730 // CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 2>
1731 
1732 res_vuc = vec_xxpermdi(vuc, vuc, 1);
1733 // CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 3>
1734 // CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 3>
1735 
1736 res_vd = vec_xxsldwi(vd, vd, 0);
1737 // CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1738 // CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1739 
1740 res_vf = vec_xxsldwi(vf, vf, 1);
1741 // CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
1742 // CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 7, i32 0, i32 1, i32 2>
1743 
1744 res_vsll = vec_xxsldwi(vsll, vsll, 2);
1745 // CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
1746 // CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1747 
1748 res_vull = vec_xxsldwi(vull, vull, 3);
1749 // CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
1750 // CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 5, i32 6, i32 7, i32 0>
1751 
1752 res_vsi = vec_xxsldwi(vsi, vsi, 0);
1753 // CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1754 // CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1755 
1756 res_vui = vec_xxsldwi(vui, vui, 1);
1757 // CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
1758 // CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 7, i32 0, i32 1, i32 2>
1759 
1760 res_vss = vec_xxsldwi(vss, vss, 2);
1761 // CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
1762 // CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
1763 
1764 
1765 res_vus = vec_xxsldwi(vus, vus, 3);
1766 // CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
1767 // CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 5, i32 6, i32 7, i32 0>
1768 
1769 res_vsc = vec_xxsldwi(vsc, vsc, 0);
1770 // CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1771 // CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1772 
1773 res_vuc = vec_xxsldwi(vuc, vuc, 1);
1774 // CHECK: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
1775 // CHECK-LE: shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 7, i32 0, i32 1, i32 2>
1776 }
1777 
1778 // The return type of the call expression may be different from the return type of the shufflevector.
1779 // Wrong implementation could crash the compiler, add this test case to check that and avoid ICE.
xxpermdi_should_not_assert(vector int a,vector int b)1780 vector int xxpermdi_should_not_assert(vector int a, vector int b) {
1781   return vec_xxpermdi(a, b, 0);
1782 // CHECK-LABEL: xxpermdi_should_not_assert
1783 // CHECK:  bitcast <4 x i32> %{{[0-9]+}} to <2 x i64>
1784 // CHECK-NEXT:  bitcast <4 x i32> %{{[0-9]+}} to <2 x i64>
1785 // CHECK-NEXT:  shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 2>
1786 // CHECK-NEXT:  bitcast <2 x i64> %{{[0-9]+}} to <4 x i32>
1787 
1788 // CHECK-LE:  bitcast <4 x i32> %{{[0-9]+}} to <2 x i64>
1789 // CHECK-LE-NEXT:  bitcast <4 x i32> %{{[0-9]+}} to <2 x i64>
1790 // CHECK-LE-NEXT:  shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 0, i32 2>
1791 // CHECK-LE-NEXT:  bitcast <2 x i64> %{{[0-9]+}} to <4 x i32>
1792 }
1793 
xxsldwi_should_not_assert(vector double a,vector double b)1794 vector double xxsldwi_should_not_assert(vector double a, vector double b) {
1795   return vec_xxsldwi(a, b, 0);
1796 // CHECK-LABEL: xxsldwi_should_not_assert
1797 // CHECK:  bitcast <2 x double> %{{[0-9]+}} to <4 x i32>
1798 // CHECK-NEXT:  bitcast <2 x double> %{{[0-9]+}} to <4 x i32>
1799 // CHECK-NEXT:  shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1800 // CHECK-NEXT:  bitcast <4 x i32> %{{[0-9]+}} to <2 x double>
1801 
1802 // CHECK-LE:  bitcast <2 x double> %{{[0-9]+}} to <4 x i32>
1803 // CHECK-NEXT-LE:  bitcast <2 x double> %{{[0-9]+}} to <4 x i32>
1804 // CHECK-NEXT-LE:  shufflevector <4 x i32> %{{[0-9]+}}, <4 x i32> %{{[0-9]+}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1805 // CHECK-NEXT-LE:  bitcast <4 x i32> %{{[0-9]+}} to <2 x double>
1806 }
1807 
testVectorInt128Pack()1808 void testVectorInt128Pack(){
1809 // CHECK-LABEL: testVectorInt128Pack
1810 // CHECK-LABEL-LE: testVectorInt128Pack
1811   res_vslll = __builtin_pack_vector_int128(aull[0], aull[1]);
1812 // CHECK: %[[V1:[0-9]+]] = insertelement <2 x i64> undef, i64 %{{[0-9]+}}, i64 0
1813 // CHECK-NEXT: %[[V2:[0-9]+]] = insertelement <2 x i64> %[[V1]], i64 %{{[0-9]+}}, i64 1
1814 // CHECK-NEXT:  bitcast <2 x i64> %[[V2]] to <1 x i128>
1815 
1816 // CHECK-LE: %[[V1:[0-9]+]] = insertelement <2 x i64> undef, i64 %{{[0-9]+}}, i64 1
1817 // CHECK-NEXT-LE: %[[V2:[0-9]+]] = insertelement <2 x i64> %[[V1]], i64 %{{[0-9]+}}, i64 0
1818 // CHECK-NEXT-LE:  bitcast <2 x i64> %[[V2]] to <1 x i128>
1819 
1820   __builtin_unpack_vector_int128(res_vslll, 0);
1821 // CHECK:  %[[V1:[0-9]+]] = bitcast <1 x i128> %{{[0-9]+}} to <2 x i64>
1822 // CHECK-NEXT: %{{[0-9]+}} = extractelement <2 x i64> %[[V1]], i32 0
1823 
1824 // CHECK-LE:  %[[V1:[0-9]+]] = bitcast <1 x i128> %{{[0-9]+}} to <2 x i64>
1825 // CHECK-NEXT-LE: %{{[0-9]+}} = extractelement <2 x i64> %[[V1]], i32 1
1826 
1827   __builtin_unpack_vector_int128(res_vslll, 1);
1828 // CHECK:  %[[V1:[0-9]+]] = bitcast <1 x i128> %{{[0-9]+}} to <2 x i64>
1829 // CHECK-NEXT: %{{[0-9]+}} = extractelement <2 x i64> %[[V1]], i32 1
1830 
1831 // CHECK-LE:  %[[V1:[0-9]+]] = bitcast <1 x i128> %{{[0-9]+}} to <2 x i64>
1832 // CHECK-NEXT-LE: %{{[0-9]+}} = extractelement <2 x i64> %[[V1]], i32 0
1833 
1834 }
1835