1//===- AMDGPUGenRegisterBankInfo.def -----------------------------*- C++ -*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// \file 9/// This file defines all the static objects used by AMDGPURegisterBankInfo. 10/// \todo This should be generated by TableGen. 11//===----------------------------------------------------------------------===// 12 13namespace llvm { 14namespace AMDGPU { 15 16enum PartialMappingIdx { 17 None = - 1, 18 PM_SGPR1 = 1, 19 PM_SGPR16 = 5, 20 PM_SGPR32 = 6, 21 PM_SGPR64 = 7, 22 PM_SGPR128 = 8, 23 PM_SGPR256 = 9, 24 PM_SGPR512 = 10, 25 PM_SGPR1024 = 11, 26 PM_VGPR1 = 12, 27 PM_VGPR16 = 16, 28 PM_VGPR32 = 17, 29 PM_VGPR64 = 18, 30 PM_VGPR128 = 19, 31 PM_VGPR256 = 20, 32 PM_VGPR512 = 21, 33 PM_VGPR1024 = 22, 34 PM_SGPR96 = 23, 35 PM_VGPR96 = 24, 36 PM_AGPR96 = 25, 37 PM_AGPR32 = 31, 38 PM_AGPR64 = 32, 39 PM_AGPR128 = 33, 40 PM_AGPR512 = 34, 41 PM_AGPR1024 = 35 42}; 43 44const RegisterBankInfo::PartialMapping PartMappings[] { 45 // StartIdx, Length, RegBank 46 {0, 1, VCCRegBank}, 47 48 {0, 1, SGPRRegBank}, // SGPR begin 49 {0, 16, SGPRRegBank}, 50 {0, 32, SGPRRegBank}, 51 {0, 64, SGPRRegBank}, 52 {0, 128, SGPRRegBank}, 53 {0, 256, SGPRRegBank}, 54 {0, 512, SGPRRegBank}, 55 {0, 1024, SGPRRegBank}, 56 57 {0, 1, VGPRRegBank}, // VGPR begin 58 {0, 16, VGPRRegBank}, 59 {0, 32, VGPRRegBank}, 60 {0, 64, VGPRRegBank}, 61 {0, 128, VGPRRegBank}, 62 {0, 256, VGPRRegBank}, 63 {0, 512, VGPRRegBank}, 64 {0, 1024, VGPRRegBank}, 65 {0, 96, SGPRRegBank}, 66 {0, 96, VGPRRegBank}, 67 {0, 96, AGPRRegBank}, 68 69 {0, 32, AGPRRegBank}, // AGPR begin 70 {0, 64, AGPRRegBank}, 71 {0, 128, AGPRRegBank}, 72 {0, 512, AGPRRegBank}, 73 {0, 1024, AGPRRegBank} 74}; 75 76const RegisterBankInfo::ValueMapping ValMappings[] { 77 // VCC 78 {&PartMappings[0], 1}, 79 80 // SGPRs 81 {&PartMappings[1], 1}, // 1 82 {nullptr, 0}, // Illegal power of 2 sizes 83 {nullptr, 0}, 84 {nullptr, 0}, 85 {&PartMappings[2], 1}, // 16 86 {&PartMappings[3], 1}, // 32 87 {&PartMappings[4], 1}, // 64 88 {&PartMappings[5], 1}, // 128 89 {&PartMappings[6], 1}, // 256 90 {&PartMappings[7], 1}, // 512 91 {&PartMappings[8], 1}, // 1024 92 93 // VGPRs 94 {&PartMappings[9], 1}, // 1 95 {nullptr, 0}, 96 {nullptr, 0}, 97 {nullptr, 0}, 98 {&PartMappings[10], 1}, // 16 99 {&PartMappings[11], 1}, // 32 100 {&PartMappings[12], 1}, // 64 101 {&PartMappings[13], 1}, // 128 102 {&PartMappings[14], 1}, // 256 103 {&PartMappings[15], 1}, // 512 104 {&PartMappings[16], 1}, // 1024 105 {&PartMappings[17], 1}, 106 {&PartMappings[18], 1}, 107 {&PartMappings[19], 1}, 108 109 // AGPRs 110 {nullptr, 0}, 111 {nullptr, 0}, 112 {nullptr, 0}, 113 {nullptr, 0}, 114 {nullptr, 0}, 115 {&PartMappings[20], 1}, // 32 116 {&PartMappings[21], 1}, // 64 117 {&PartMappings[22], 1}, // 128 118 {nullptr, 0}, 119 {&PartMappings[23], 1}, // 512 120 {&PartMappings[24], 1} // 1024 121}; 122 123const RegisterBankInfo::PartialMapping SGPROnly64BreakDown[] { 124 {0, 32, SGPRRegBank}, // 32-bit op 125 {0, 32, SGPRRegBank}, // 2x32-bit op 126 {32, 32, SGPRRegBank}, 127 {0, 64, SGPRRegBank}, // <2x32-bit> op 128 129 {0, 32, VGPRRegBank}, // 32-bit op 130 {0, 32, VGPRRegBank}, // 2x32-bit op 131 {32, 32, VGPRRegBank}, 132}; 133 134 135// For some instructions which can operate 64-bit only for the scalar 136// version. Otherwise, these need to be split into 2 32-bit operations. 137const RegisterBankInfo::ValueMapping ValMappingsSGPR64OnlyVGPR32[] { 138 /*32-bit sgpr*/ {&SGPROnly64BreakDown[0], 1}, 139 /*2 x 32-bit sgpr*/ {&SGPROnly64BreakDown[1], 2}, 140 /*64-bit sgpr */ {&SGPROnly64BreakDown[3], 1}, 141 142 /*32-bit vgpr*/ {&SGPROnly64BreakDown[4], 1}, 143 /*2 x 32-bit vgpr*/ {&SGPROnly64BreakDown[5], 2} 144}; 145 146enum ValueMappingIdx { 147 SGPRStartIdx = 1, 148 VGPRStartIdx = 12, 149 AGPRStartIdx = 26 150}; 151 152const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID, 153 unsigned Size) { 154 unsigned Idx; 155 switch (Size) { 156 case 1: 157 if (BankID == AMDGPU::VCCRegBankID) 158 return &ValMappings[0]; 159 160 Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR1 : PM_VGPR1; 161 break; 162 case 96: 163 switch (BankID) { 164 case AMDGPU::VGPRRegBankID: 165 Idx = PM_VGPR96; 166 break; 167 case AMDGPU::SGPRRegBankID: 168 Idx = PM_SGPR96; 169 break; 170 case AMDGPU::AGPRRegBankID: 171 Idx = PM_AGPR96; 172 break; 173 default: llvm_unreachable("Invalid register bank"); 174 } 175 break; 176 default: 177 switch (BankID) { 178 case AMDGPU::VGPRRegBankID: 179 Idx = VGPRStartIdx; 180 break; 181 case AMDGPU::SGPRRegBankID: 182 Idx = SGPRStartIdx; 183 break; 184 case AMDGPU::AGPRRegBankID: 185 Idx = AGPRStartIdx; 186 break; 187 default: llvm_unreachable("Invalid register bank"); 188 } 189 Idx += Log2_32_Ceil(Size); 190 break; 191 } 192 193 assert(Log2_32_Ceil(Size) == Log2_32_Ceil(ValMappings[Idx].BreakDown->Length)); 194 assert(BankID == ValMappings[Idx].BreakDown->RegBank->getID()); 195 196 return &ValMappings[Idx]; 197} 198 199const RegisterBankInfo::ValueMapping *getValueMappingSGPR64Only(unsigned BankID, 200 unsigned Size) { 201 if (Size != 64) 202 return getValueMapping(BankID, Size); 203 204 if (BankID == AMDGPU::VGPRRegBankID) 205 return &ValMappingsSGPR64OnlyVGPR32[4]; 206 207 assert(BankID == AMDGPU::SGPRRegBankID); 208 return &ValMappingsSGPR64OnlyVGPR32[2]; 209} 210 211/// Split any 64-bit value into 2 32-bit pieces. Unlike 212/// getValueMappingSGPR64Only, this splits both VGPRs and SGPRs. 213const RegisterBankInfo::ValueMapping *getValueMappingSplit64(unsigned BankID, 214 unsigned Size) { 215 assert(Size == 64); 216 if (BankID == AMDGPU::VGPRRegBankID) 217 return &ValMappingsSGPR64OnlyVGPR32[4]; 218 219 assert(BankID == AMDGPU::SGPRRegBankID); 220 return &ValMappingsSGPR64OnlyVGPR32[1]; 221} 222 223 224} // End AMDGPU namespace. 225} // End llvm namespace. 226