1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the MSP430TargetLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "MSP430ISelLowering.h"
14 #include "MSP430.h"
15 #include "MSP430MachineFunctionInfo.h"
16 #include "MSP430Subtarget.h"
17 #include "MSP430TargetMachine.h"
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/IR/CallingConv.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/GlobalAlias.h"
30 #include "llvm/IR/GlobalVariable.h"
31 #include "llvm/IR/Intrinsics.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 using namespace llvm;
37
38 #define DEBUG_TYPE "msp430-lower"
39
40 static cl::opt<bool>MSP430NoLegalImmediate(
41 "msp430-no-legal-immediate", cl::Hidden,
42 cl::desc("Enable non legal immediates (for testing purposes only)"),
43 cl::init(false));
44
MSP430TargetLowering(const TargetMachine & TM,const MSP430Subtarget & STI)45 MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM,
46 const MSP430Subtarget &STI)
47 : TargetLowering(TM) {
48
49 // Set up the register classes.
50 addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
51 addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
52
53 // Compute derived properties from the register classes
54 computeRegisterProperties(STI.getRegisterInfo());
55
56 // Provide all sorts of operation actions
57 setStackPointerRegisterToSaveRestore(MSP430::SP);
58 setBooleanContents(ZeroOrOneBooleanContent);
59 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
60
61 // We have post-incremented loads / stores.
62 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
63 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
64
65 for (MVT VT : MVT::integer_valuetypes()) {
66 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
67 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
68 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
69 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
70 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand);
71 }
72
73 // We don't have any truncstores
74 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
75
76 setOperationAction(ISD::SRA, MVT::i8, Custom);
77 setOperationAction(ISD::SHL, MVT::i8, Custom);
78 setOperationAction(ISD::SRL, MVT::i8, Custom);
79 setOperationAction(ISD::SRA, MVT::i16, Custom);
80 setOperationAction(ISD::SHL, MVT::i16, Custom);
81 setOperationAction(ISD::SRL, MVT::i16, Custom);
82 setOperationAction(ISD::ROTL, MVT::i8, Expand);
83 setOperationAction(ISD::ROTR, MVT::i8, Expand);
84 setOperationAction(ISD::ROTL, MVT::i16, Expand);
85 setOperationAction(ISD::ROTR, MVT::i16, Expand);
86 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
87 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
88 setOperationAction(ISD::BlockAddress, MVT::i16, Custom);
89 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
90 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
91 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
92 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
93 setOperationAction(ISD::SETCC, MVT::i8, Custom);
94 setOperationAction(ISD::SETCC, MVT::i16, Custom);
95 setOperationAction(ISD::SELECT, MVT::i8, Expand);
96 setOperationAction(ISD::SELECT, MVT::i16, Expand);
97 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
98 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
99 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom);
100 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
101 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
102 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
103 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
104
105 setOperationAction(ISD::CTTZ, MVT::i8, Expand);
106 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
107 setOperationAction(ISD::CTLZ, MVT::i8, Expand);
108 setOperationAction(ISD::CTLZ, MVT::i16, Expand);
109 setOperationAction(ISD::CTPOP, MVT::i8, Expand);
110 setOperationAction(ISD::CTPOP, MVT::i16, Expand);
111
112 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
113 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
114 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
115 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
116 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
117 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
118
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
120
121 // FIXME: Implement efficiently multiplication by a constant
122 setOperationAction(ISD::MUL, MVT::i8, Promote);
123 setOperationAction(ISD::MULHS, MVT::i8, Promote);
124 setOperationAction(ISD::MULHU, MVT::i8, Promote);
125 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Promote);
126 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Promote);
127 setOperationAction(ISD::MUL, MVT::i16, LibCall);
128 setOperationAction(ISD::MULHS, MVT::i16, Expand);
129 setOperationAction(ISD::MULHU, MVT::i16, Expand);
130 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
131 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
132
133 setOperationAction(ISD::UDIV, MVT::i8, Promote);
134 setOperationAction(ISD::UDIVREM, MVT::i8, Promote);
135 setOperationAction(ISD::UREM, MVT::i8, Promote);
136 setOperationAction(ISD::SDIV, MVT::i8, Promote);
137 setOperationAction(ISD::SDIVREM, MVT::i8, Promote);
138 setOperationAction(ISD::SREM, MVT::i8, Promote);
139 setOperationAction(ISD::UDIV, MVT::i16, LibCall);
140 setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
141 setOperationAction(ISD::UREM, MVT::i16, LibCall);
142 setOperationAction(ISD::SDIV, MVT::i16, LibCall);
143 setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
144 setOperationAction(ISD::SREM, MVT::i16, LibCall);
145
146 // varargs support
147 setOperationAction(ISD::VASTART, MVT::Other, Custom);
148 setOperationAction(ISD::VAARG, MVT::Other, Expand);
149 setOperationAction(ISD::VAEND, MVT::Other, Expand);
150 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
151 setOperationAction(ISD::JumpTable, MVT::i16, Custom);
152
153 // EABI Libcalls - EABI Section 6.2
154 const struct {
155 const RTLIB::Libcall Op;
156 const char * const Name;
157 const ISD::CondCode Cond;
158 } LibraryCalls[] = {
159 // Floating point conversions - EABI Table 6
160 { RTLIB::FPROUND_F64_F32, "__mspabi_cvtdf", ISD::SETCC_INVALID },
161 { RTLIB::FPEXT_F32_F64, "__mspabi_cvtfd", ISD::SETCC_INVALID },
162 // The following is NOT implemented in libgcc
163 //{ RTLIB::FPTOSINT_F64_I16, "__mspabi_fixdi", ISD::SETCC_INVALID },
164 { RTLIB::FPTOSINT_F64_I32, "__mspabi_fixdli", ISD::SETCC_INVALID },
165 { RTLIB::FPTOSINT_F64_I64, "__mspabi_fixdlli", ISD::SETCC_INVALID },
166 // The following is NOT implemented in libgcc
167 //{ RTLIB::FPTOUINT_F64_I16, "__mspabi_fixdu", ISD::SETCC_INVALID },
168 { RTLIB::FPTOUINT_F64_I32, "__mspabi_fixdul", ISD::SETCC_INVALID },
169 { RTLIB::FPTOUINT_F64_I64, "__mspabi_fixdull", ISD::SETCC_INVALID },
170 // The following is NOT implemented in libgcc
171 //{ RTLIB::FPTOSINT_F32_I16, "__mspabi_fixfi", ISD::SETCC_INVALID },
172 { RTLIB::FPTOSINT_F32_I32, "__mspabi_fixfli", ISD::SETCC_INVALID },
173 { RTLIB::FPTOSINT_F32_I64, "__mspabi_fixflli", ISD::SETCC_INVALID },
174 // The following is NOT implemented in libgcc
175 //{ RTLIB::FPTOUINT_F32_I16, "__mspabi_fixfu", ISD::SETCC_INVALID },
176 { RTLIB::FPTOUINT_F32_I32, "__mspabi_fixful", ISD::SETCC_INVALID },
177 { RTLIB::FPTOUINT_F32_I64, "__mspabi_fixfull", ISD::SETCC_INVALID },
178 // TODO The following IS implemented in libgcc
179 //{ RTLIB::SINTTOFP_I16_F64, "__mspabi_fltid", ISD::SETCC_INVALID },
180 { RTLIB::SINTTOFP_I32_F64, "__mspabi_fltlid", ISD::SETCC_INVALID },
181 // TODO The following IS implemented in libgcc but is not in the EABI
182 { RTLIB::SINTTOFP_I64_F64, "__mspabi_fltllid", ISD::SETCC_INVALID },
183 // TODO The following IS implemented in libgcc
184 //{ RTLIB::UINTTOFP_I16_F64, "__mspabi_fltud", ISD::SETCC_INVALID },
185 { RTLIB::UINTTOFP_I32_F64, "__mspabi_fltuld", ISD::SETCC_INVALID },
186 // The following IS implemented in libgcc but is not in the EABI
187 { RTLIB::UINTTOFP_I64_F64, "__mspabi_fltulld", ISD::SETCC_INVALID },
188 // TODO The following IS implemented in libgcc
189 //{ RTLIB::SINTTOFP_I16_F32, "__mspabi_fltif", ISD::SETCC_INVALID },
190 { RTLIB::SINTTOFP_I32_F32, "__mspabi_fltlif", ISD::SETCC_INVALID },
191 // TODO The following IS implemented in libgcc but is not in the EABI
192 { RTLIB::SINTTOFP_I64_F32, "__mspabi_fltllif", ISD::SETCC_INVALID },
193 // TODO The following IS implemented in libgcc
194 //{ RTLIB::UINTTOFP_I16_F32, "__mspabi_fltuf", ISD::SETCC_INVALID },
195 { RTLIB::UINTTOFP_I32_F32, "__mspabi_fltulf", ISD::SETCC_INVALID },
196 // The following IS implemented in libgcc but is not in the EABI
197 { RTLIB::UINTTOFP_I64_F32, "__mspabi_fltullf", ISD::SETCC_INVALID },
198
199 // Floating point comparisons - EABI Table 7
200 { RTLIB::OEQ_F64, "__mspabi_cmpd", ISD::SETEQ },
201 { RTLIB::UNE_F64, "__mspabi_cmpd", ISD::SETNE },
202 { RTLIB::OGE_F64, "__mspabi_cmpd", ISD::SETGE },
203 { RTLIB::OLT_F64, "__mspabi_cmpd", ISD::SETLT },
204 { RTLIB::OLE_F64, "__mspabi_cmpd", ISD::SETLE },
205 { RTLIB::OGT_F64, "__mspabi_cmpd", ISD::SETGT },
206 { RTLIB::OEQ_F32, "__mspabi_cmpf", ISD::SETEQ },
207 { RTLIB::UNE_F32, "__mspabi_cmpf", ISD::SETNE },
208 { RTLIB::OGE_F32, "__mspabi_cmpf", ISD::SETGE },
209 { RTLIB::OLT_F32, "__mspabi_cmpf", ISD::SETLT },
210 { RTLIB::OLE_F32, "__mspabi_cmpf", ISD::SETLE },
211 { RTLIB::OGT_F32, "__mspabi_cmpf", ISD::SETGT },
212
213 // Floating point arithmetic - EABI Table 8
214 { RTLIB::ADD_F64, "__mspabi_addd", ISD::SETCC_INVALID },
215 { RTLIB::ADD_F32, "__mspabi_addf", ISD::SETCC_INVALID },
216 { RTLIB::DIV_F64, "__mspabi_divd", ISD::SETCC_INVALID },
217 { RTLIB::DIV_F32, "__mspabi_divf", ISD::SETCC_INVALID },
218 { RTLIB::MUL_F64, "__mspabi_mpyd", ISD::SETCC_INVALID },
219 { RTLIB::MUL_F32, "__mspabi_mpyf", ISD::SETCC_INVALID },
220 { RTLIB::SUB_F64, "__mspabi_subd", ISD::SETCC_INVALID },
221 { RTLIB::SUB_F32, "__mspabi_subf", ISD::SETCC_INVALID },
222 // The following are NOT implemented in libgcc
223 // { RTLIB::NEG_F64, "__mspabi_negd", ISD::SETCC_INVALID },
224 // { RTLIB::NEG_F32, "__mspabi_negf", ISD::SETCC_INVALID },
225
226 // Universal Integer Operations - EABI Table 9
227 { RTLIB::SDIV_I16, "__mspabi_divi", ISD::SETCC_INVALID },
228 { RTLIB::SDIV_I32, "__mspabi_divli", ISD::SETCC_INVALID },
229 { RTLIB::SDIV_I64, "__mspabi_divlli", ISD::SETCC_INVALID },
230 { RTLIB::UDIV_I16, "__mspabi_divu", ISD::SETCC_INVALID },
231 { RTLIB::UDIV_I32, "__mspabi_divul", ISD::SETCC_INVALID },
232 { RTLIB::UDIV_I64, "__mspabi_divull", ISD::SETCC_INVALID },
233 { RTLIB::SREM_I16, "__mspabi_remi", ISD::SETCC_INVALID },
234 { RTLIB::SREM_I32, "__mspabi_remli", ISD::SETCC_INVALID },
235 { RTLIB::SREM_I64, "__mspabi_remlli", ISD::SETCC_INVALID },
236 { RTLIB::UREM_I16, "__mspabi_remu", ISD::SETCC_INVALID },
237 { RTLIB::UREM_I32, "__mspabi_remul", ISD::SETCC_INVALID },
238 { RTLIB::UREM_I64, "__mspabi_remull", ISD::SETCC_INVALID },
239
240 // Bitwise Operations - EABI Table 10
241 // TODO: __mspabi_[srli/srai/slli] ARE implemented in libgcc
242 { RTLIB::SRL_I32, "__mspabi_srll", ISD::SETCC_INVALID },
243 { RTLIB::SRA_I32, "__mspabi_sral", ISD::SETCC_INVALID },
244 { RTLIB::SHL_I32, "__mspabi_slll", ISD::SETCC_INVALID },
245 // __mspabi_[srlll/srall/sllll/rlli/rlll] are NOT implemented in libgcc
246
247 };
248
249 for (const auto &LC : LibraryCalls) {
250 setLibcallName(LC.Op, LC.Name);
251 if (LC.Cond != ISD::SETCC_INVALID)
252 setCmpLibcallCC(LC.Op, LC.Cond);
253 }
254
255 if (STI.hasHWMult16()) {
256 const struct {
257 const RTLIB::Libcall Op;
258 const char * const Name;
259 } LibraryCalls[] = {
260 // Integer Multiply - EABI Table 9
261 { RTLIB::MUL_I16, "__mspabi_mpyi_hw" },
262 { RTLIB::MUL_I32, "__mspabi_mpyl_hw" },
263 { RTLIB::MUL_I64, "__mspabi_mpyll_hw" },
264 // TODO The __mspabi_mpysl*_hw functions ARE implemented in libgcc
265 // TODO The __mspabi_mpyul*_hw functions ARE implemented in libgcc
266 };
267 for (const auto &LC : LibraryCalls) {
268 setLibcallName(LC.Op, LC.Name);
269 }
270 } else if (STI.hasHWMult32()) {
271 const struct {
272 const RTLIB::Libcall Op;
273 const char * const Name;
274 } LibraryCalls[] = {
275 // Integer Multiply - EABI Table 9
276 { RTLIB::MUL_I16, "__mspabi_mpyi_hw" },
277 { RTLIB::MUL_I32, "__mspabi_mpyl_hw32" },
278 { RTLIB::MUL_I64, "__mspabi_mpyll_hw32" },
279 // TODO The __mspabi_mpysl*_hw32 functions ARE implemented in libgcc
280 // TODO The __mspabi_mpyul*_hw32 functions ARE implemented in libgcc
281 };
282 for (const auto &LC : LibraryCalls) {
283 setLibcallName(LC.Op, LC.Name);
284 }
285 } else if (STI.hasHWMultF5()) {
286 const struct {
287 const RTLIB::Libcall Op;
288 const char * const Name;
289 } LibraryCalls[] = {
290 // Integer Multiply - EABI Table 9
291 { RTLIB::MUL_I16, "__mspabi_mpyi_f5hw" },
292 { RTLIB::MUL_I32, "__mspabi_mpyl_f5hw" },
293 { RTLIB::MUL_I64, "__mspabi_mpyll_f5hw" },
294 // TODO The __mspabi_mpysl*_f5hw functions ARE implemented in libgcc
295 // TODO The __mspabi_mpyul*_f5hw functions ARE implemented in libgcc
296 };
297 for (const auto &LC : LibraryCalls) {
298 setLibcallName(LC.Op, LC.Name);
299 }
300 } else { // NoHWMult
301 const struct {
302 const RTLIB::Libcall Op;
303 const char * const Name;
304 } LibraryCalls[] = {
305 // Integer Multiply - EABI Table 9
306 { RTLIB::MUL_I16, "__mspabi_mpyi" },
307 { RTLIB::MUL_I32, "__mspabi_mpyl" },
308 { RTLIB::MUL_I64, "__mspabi_mpyll" },
309 // The __mspabi_mpysl* functions are NOT implemented in libgcc
310 // The __mspabi_mpyul* functions are NOT implemented in libgcc
311 };
312 for (const auto &LC : LibraryCalls) {
313 setLibcallName(LC.Op, LC.Name);
314 }
315 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::MSP430_BUILTIN);
316 }
317
318 // Several of the runtime library functions use a special calling conv
319 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::MSP430_BUILTIN);
320 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::MSP430_BUILTIN);
321 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::MSP430_BUILTIN);
322 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::MSP430_BUILTIN);
323 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::MSP430_BUILTIN);
324 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::MSP430_BUILTIN);
325 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::MSP430_BUILTIN);
326 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::MSP430_BUILTIN);
327 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::MSP430_BUILTIN);
328 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::MSP430_BUILTIN);
329 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::MSP430_BUILTIN);
330 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::MSP430_BUILTIN);
331 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::MSP430_BUILTIN);
332 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::MSP430_BUILTIN);
333 // TODO: __mspabi_srall, __mspabi_srlll, __mspabi_sllll
334
335 setMinFunctionAlignment(Align(2));
336 setPrefFunctionAlignment(Align(2));
337 }
338
LowerOperation(SDValue Op,SelectionDAG & DAG) const339 SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
340 SelectionDAG &DAG) const {
341 switch (Op.getOpcode()) {
342 case ISD::SHL: // FALLTHROUGH
343 case ISD::SRL:
344 case ISD::SRA: return LowerShifts(Op, DAG);
345 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
346 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
347 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
348 case ISD::SETCC: return LowerSETCC(Op, DAG);
349 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
350 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
351 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
352 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
353 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
354 case ISD::VASTART: return LowerVASTART(Op, DAG);
355 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
356 default:
357 llvm_unreachable("unimplemented operand");
358 }
359 }
360
361 // Define non profitable transforms into shifts
shouldAvoidTransformToShift(EVT VT,unsigned Amount) const362 bool MSP430TargetLowering::shouldAvoidTransformToShift(EVT VT,
363 unsigned Amount) const {
364 return !(Amount == 8 || Amount == 9 || Amount<=2);
365 }
366
367 // Implemented to verify test case assertions in
368 // tests/codegen/msp430/shift-amount-threshold-b.ll
isLegalICmpImmediate(int64_t Immed) const369 bool MSP430TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
370 if (MSP430NoLegalImmediate)
371 return Immed >= -32 && Immed < 32;
372 return TargetLowering::isLegalICmpImmediate(Immed);
373 }
374
375 //===----------------------------------------------------------------------===//
376 // MSP430 Inline Assembly Support
377 //===----------------------------------------------------------------------===//
378
379 /// getConstraintType - Given a constraint letter, return the type of
380 /// constraint it is for this target.
381 TargetLowering::ConstraintType
getConstraintType(StringRef Constraint) const382 MSP430TargetLowering::getConstraintType(StringRef Constraint) const {
383 if (Constraint.size() == 1) {
384 switch (Constraint[0]) {
385 case 'r':
386 return C_RegisterClass;
387 default:
388 break;
389 }
390 }
391 return TargetLowering::getConstraintType(Constraint);
392 }
393
394 std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo * TRI,StringRef Constraint,MVT VT) const395 MSP430TargetLowering::getRegForInlineAsmConstraint(
396 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
397 if (Constraint.size() == 1) {
398 // GCC Constraint Letters
399 switch (Constraint[0]) {
400 default: break;
401 case 'r': // GENERAL_REGS
402 if (VT == MVT::i8)
403 return std::make_pair(0U, &MSP430::GR8RegClass);
404
405 return std::make_pair(0U, &MSP430::GR16RegClass);
406 }
407 }
408
409 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
410 }
411
412 //===----------------------------------------------------------------------===//
413 // Calling Convention Implementation
414 //===----------------------------------------------------------------------===//
415
416 #include "MSP430GenCallingConv.inc"
417
418 /// For each argument in a function store the number of pieces it is composed
419 /// of.
420 template<typename ArgT>
ParseFunctionArgs(const SmallVectorImpl<ArgT> & Args,SmallVectorImpl<unsigned> & Out)421 static void ParseFunctionArgs(const SmallVectorImpl<ArgT> &Args,
422 SmallVectorImpl<unsigned> &Out) {
423 unsigned CurrentArgIndex;
424
425 if (Args.empty())
426 return;
427
428 CurrentArgIndex = Args[0].OrigArgIndex;
429 Out.push_back(0);
430
431 for (auto &Arg : Args) {
432 if (CurrentArgIndex == Arg.OrigArgIndex) {
433 Out.back() += 1;
434 } else {
435 Out.push_back(1);
436 CurrentArgIndex = Arg.OrigArgIndex;
437 }
438 }
439 }
440
AnalyzeVarArgs(CCState & State,const SmallVectorImpl<ISD::OutputArg> & Outs)441 static void AnalyzeVarArgs(CCState &State,
442 const SmallVectorImpl<ISD::OutputArg> &Outs) {
443 State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
444 }
445
AnalyzeVarArgs(CCState & State,const SmallVectorImpl<ISD::InputArg> & Ins)446 static void AnalyzeVarArgs(CCState &State,
447 const SmallVectorImpl<ISD::InputArg> &Ins) {
448 State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack);
449 }
450
451 /// Analyze incoming and outgoing function arguments. We need custom C++ code
452 /// to handle special constraints in the ABI like reversing the order of the
453 /// pieces of splitted arguments. In addition, all pieces of a certain argument
454 /// have to be passed either using registers or the stack but never mixing both.
455 template<typename ArgT>
AnalyzeArguments(CCState & State,SmallVectorImpl<CCValAssign> & ArgLocs,const SmallVectorImpl<ArgT> & Args)456 static void AnalyzeArguments(CCState &State,
457 SmallVectorImpl<CCValAssign> &ArgLocs,
458 const SmallVectorImpl<ArgT> &Args) {
459 static const MCPhysReg CRegList[] = {
460 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
461 };
462 static const unsigned CNbRegs = array_lengthof(CRegList);
463 static const MCPhysReg BuiltinRegList[] = {
464 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
465 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
466 };
467 static const unsigned BuiltinNbRegs = array_lengthof(BuiltinRegList);
468
469 ArrayRef<MCPhysReg> RegList;
470 unsigned NbRegs;
471
472 bool Builtin = (State.getCallingConv() == CallingConv::MSP430_BUILTIN);
473 if (Builtin) {
474 RegList = BuiltinRegList;
475 NbRegs = BuiltinNbRegs;
476 } else {
477 RegList = CRegList;
478 NbRegs = CNbRegs;
479 }
480
481 if (State.isVarArg()) {
482 AnalyzeVarArgs(State, Args);
483 return;
484 }
485
486 SmallVector<unsigned, 4> ArgsParts;
487 ParseFunctionArgs(Args, ArgsParts);
488
489 if (Builtin) {
490 assert(ArgsParts.size() == 2 &&
491 "Builtin calling convention requires two arguments");
492 }
493
494 unsigned RegsLeft = NbRegs;
495 bool UsedStack = false;
496 unsigned ValNo = 0;
497
498 for (unsigned i = 0, e = ArgsParts.size(); i != e; i++) {
499 MVT ArgVT = Args[ValNo].VT;
500 ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags;
501 MVT LocVT = ArgVT;
502 CCValAssign::LocInfo LocInfo = CCValAssign::Full;
503
504 // Promote i8 to i16
505 if (LocVT == MVT::i8) {
506 LocVT = MVT::i16;
507 if (ArgFlags.isSExt())
508 LocInfo = CCValAssign::SExt;
509 else if (ArgFlags.isZExt())
510 LocInfo = CCValAssign::ZExt;
511 else
512 LocInfo = CCValAssign::AExt;
513 }
514
515 // Handle byval arguments
516 if (ArgFlags.isByVal()) {
517 State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, Align(2), ArgFlags);
518 continue;
519 }
520
521 unsigned Parts = ArgsParts[i];
522
523 if (Builtin) {
524 assert(Parts == 4 &&
525 "Builtin calling convention requires 64-bit arguments");
526 }
527
528 if (!UsedStack && Parts == 2 && RegsLeft == 1) {
529 // Special case for 32-bit register split, see EABI section 3.3.3
530 unsigned Reg = State.AllocateReg(RegList);
531 State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
532 RegsLeft -= 1;
533
534 UsedStack = true;
535 CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
536 } else if (Parts <= RegsLeft) {
537 for (unsigned j = 0; j < Parts; j++) {
538 unsigned Reg = State.AllocateReg(RegList);
539 State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
540 RegsLeft--;
541 }
542 } else {
543 UsedStack = true;
544 for (unsigned j = 0; j < Parts; j++)
545 CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
546 }
547 }
548 }
549
AnalyzeRetResult(CCState & State,const SmallVectorImpl<ISD::InputArg> & Ins)550 static void AnalyzeRetResult(CCState &State,
551 const SmallVectorImpl<ISD::InputArg> &Ins) {
552 State.AnalyzeCallResult(Ins, RetCC_MSP430);
553 }
554
AnalyzeRetResult(CCState & State,const SmallVectorImpl<ISD::OutputArg> & Outs)555 static void AnalyzeRetResult(CCState &State,
556 const SmallVectorImpl<ISD::OutputArg> &Outs) {
557 State.AnalyzeReturn(Outs, RetCC_MSP430);
558 }
559
560 template<typename ArgT>
AnalyzeReturnValues(CCState & State,SmallVectorImpl<CCValAssign> & RVLocs,const SmallVectorImpl<ArgT> & Args)561 static void AnalyzeReturnValues(CCState &State,
562 SmallVectorImpl<CCValAssign> &RVLocs,
563 const SmallVectorImpl<ArgT> &Args) {
564 AnalyzeRetResult(State, Args);
565 }
566
LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const567 SDValue MSP430TargetLowering::LowerFormalArguments(
568 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
569 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
570 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
571
572 switch (CallConv) {
573 default:
574 report_fatal_error("Unsupported calling convention");
575 case CallingConv::C:
576 case CallingConv::Fast:
577 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
578 case CallingConv::MSP430_INTR:
579 if (Ins.empty())
580 return Chain;
581 report_fatal_error("ISRs cannot have arguments");
582 }
583 }
584
585 SDValue
LowerCall(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const586 MSP430TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
587 SmallVectorImpl<SDValue> &InVals) const {
588 SelectionDAG &DAG = CLI.DAG;
589 SDLoc &dl = CLI.DL;
590 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
591 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
592 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
593 SDValue Chain = CLI.Chain;
594 SDValue Callee = CLI.Callee;
595 bool &isTailCall = CLI.IsTailCall;
596 CallingConv::ID CallConv = CLI.CallConv;
597 bool isVarArg = CLI.IsVarArg;
598
599 // MSP430 target does not yet support tail call optimization.
600 isTailCall = false;
601
602 switch (CallConv) {
603 default:
604 report_fatal_error("Unsupported calling convention");
605 case CallingConv::MSP430_BUILTIN:
606 case CallingConv::Fast:
607 case CallingConv::C:
608 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
609 Outs, OutVals, Ins, dl, DAG, InVals);
610 case CallingConv::MSP430_INTR:
611 report_fatal_error("ISRs cannot be called directly");
612 }
613 }
614
615 /// LowerCCCArguments - transform physical registers into virtual registers and
616 /// generate load operations for arguments places on the stack.
617 // FIXME: struct return stuff
LowerCCCArguments(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const618 SDValue MSP430TargetLowering::LowerCCCArguments(
619 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
620 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
621 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
622 MachineFunction &MF = DAG.getMachineFunction();
623 MachineFrameInfo &MFI = MF.getFrameInfo();
624 MachineRegisterInfo &RegInfo = MF.getRegInfo();
625 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
626
627 // Assign locations to all of the incoming arguments.
628 SmallVector<CCValAssign, 16> ArgLocs;
629 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
630 *DAG.getContext());
631 AnalyzeArguments(CCInfo, ArgLocs, Ins);
632
633 // Create frame index for the start of the first vararg value
634 if (isVarArg) {
635 unsigned Offset = CCInfo.getNextStackOffset();
636 FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, Offset, true));
637 }
638
639 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
640 CCValAssign &VA = ArgLocs[i];
641 if (VA.isRegLoc()) {
642 // Arguments passed in registers
643 EVT RegVT = VA.getLocVT();
644 switch (RegVT.getSimpleVT().SimpleTy) {
645 default:
646 {
647 #ifndef NDEBUG
648 errs() << "LowerFormalArguments Unhandled argument type: "
649 << RegVT.getEVTString() << "\n";
650 #endif
651 llvm_unreachable(nullptr);
652 }
653 case MVT::i16:
654 Register VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
655 RegInfo.addLiveIn(VA.getLocReg(), VReg);
656 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
657
658 // If this is an 8-bit value, it is really passed promoted to 16
659 // bits. Insert an assert[sz]ext to capture this, then truncate to the
660 // right size.
661 if (VA.getLocInfo() == CCValAssign::SExt)
662 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
663 DAG.getValueType(VA.getValVT()));
664 else if (VA.getLocInfo() == CCValAssign::ZExt)
665 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
666 DAG.getValueType(VA.getValVT()));
667
668 if (VA.getLocInfo() != CCValAssign::Full)
669 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
670
671 InVals.push_back(ArgValue);
672 }
673 } else {
674 // Sanity check
675 assert(VA.isMemLoc());
676
677 SDValue InVal;
678 ISD::ArgFlagsTy Flags = Ins[i].Flags;
679
680 if (Flags.isByVal()) {
681 int FI = MFI.CreateFixedObject(Flags.getByValSize(),
682 VA.getLocMemOffset(), true);
683 InVal = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
684 } else {
685 // Load the argument to a virtual register
686 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
687 if (ObjSize > 2) {
688 errs() << "LowerFormalArguments Unhandled argument type: "
689 << EVT(VA.getLocVT()).getEVTString()
690 << "\n";
691 }
692 // Create the frame index object for this incoming parameter...
693 int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
694
695 // Create the SelectionDAG nodes corresponding to a load
696 //from this parameter
697 SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
698 InVal = DAG.getLoad(
699 VA.getLocVT(), dl, Chain, FIN,
700 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
701 }
702
703 InVals.push_back(InVal);
704 }
705 }
706
707 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
708 if (Ins[i].Flags.isSRet()) {
709 unsigned Reg = FuncInfo->getSRetReturnReg();
710 if (!Reg) {
711 Reg = MF.getRegInfo().createVirtualRegister(
712 getRegClassFor(MVT::i16));
713 FuncInfo->setSRetReturnReg(Reg);
714 }
715 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
716 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
717 }
718 }
719
720 return Chain;
721 }
722
723 bool
CanLowerReturn(CallingConv::ID CallConv,MachineFunction & MF,bool IsVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,LLVMContext & Context) const724 MSP430TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
725 MachineFunction &MF,
726 bool IsVarArg,
727 const SmallVectorImpl<ISD::OutputArg> &Outs,
728 LLVMContext &Context) const {
729 SmallVector<CCValAssign, 16> RVLocs;
730 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
731 return CCInfo.CheckReturn(Outs, RetCC_MSP430);
732 }
733
734 SDValue
LowerReturn(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SDLoc & dl,SelectionDAG & DAG) const735 MSP430TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
736 bool isVarArg,
737 const SmallVectorImpl<ISD::OutputArg> &Outs,
738 const SmallVectorImpl<SDValue> &OutVals,
739 const SDLoc &dl, SelectionDAG &DAG) const {
740
741 MachineFunction &MF = DAG.getMachineFunction();
742
743 // CCValAssign - represent the assignment of the return value to a location
744 SmallVector<CCValAssign, 16> RVLocs;
745
746 // ISRs cannot return any value.
747 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
748 report_fatal_error("ISRs cannot return any value");
749
750 // CCState - Info about the registers and stack slot.
751 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
752 *DAG.getContext());
753
754 // Analize return values.
755 AnalyzeReturnValues(CCInfo, RVLocs, Outs);
756
757 SDValue Flag;
758 SmallVector<SDValue, 4> RetOps(1, Chain);
759
760 // Copy the result values into the output registers.
761 for (unsigned i = 0; i != RVLocs.size(); ++i) {
762 CCValAssign &VA = RVLocs[i];
763 assert(VA.isRegLoc() && "Can only return in registers!");
764
765 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
766 OutVals[i], Flag);
767
768 // Guarantee that all emitted copies are stuck together,
769 // avoiding something bad.
770 Flag = Chain.getValue(1);
771 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
772 }
773
774 if (MF.getFunction().hasStructRetAttr()) {
775 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
776 unsigned Reg = FuncInfo->getSRetReturnReg();
777
778 if (!Reg)
779 llvm_unreachable("sret virtual register not created in entry block");
780
781 SDValue Val =
782 DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy(DAG.getDataLayout()));
783 unsigned R12 = MSP430::R12;
784
785 Chain = DAG.getCopyToReg(Chain, dl, R12, Val, Flag);
786 Flag = Chain.getValue(1);
787 RetOps.push_back(DAG.getRegister(R12, getPointerTy(DAG.getDataLayout())));
788 }
789
790 unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
791 MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG);
792
793 RetOps[0] = Chain; // Update chain.
794
795 // Add the flag if we have it.
796 if (Flag.getNode())
797 RetOps.push_back(Flag);
798
799 return DAG.getNode(Opc, dl, MVT::Other, RetOps);
800 }
801
802 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
803 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
LowerCCCCallTo(SDValue Chain,SDValue Callee,CallingConv::ID CallConv,bool isVarArg,bool isTailCall,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const804 SDValue MSP430TargetLowering::LowerCCCCallTo(
805 SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
806 bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs,
807 const SmallVectorImpl<SDValue> &OutVals,
808 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
809 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
810 // Analyze operands of the call, assigning locations to each operand.
811 SmallVector<CCValAssign, 16> ArgLocs;
812 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
813 *DAG.getContext());
814 AnalyzeArguments(CCInfo, ArgLocs, Outs);
815
816 // Get a count of how many bytes are to be pushed on the stack.
817 unsigned NumBytes = CCInfo.getNextStackOffset();
818 auto PtrVT = getPointerTy(DAG.getDataLayout());
819
820 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
821
822 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
823 SmallVector<SDValue, 12> MemOpChains;
824 SDValue StackPtr;
825
826 // Walk the register/memloc assignments, inserting copies/loads.
827 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
828 CCValAssign &VA = ArgLocs[i];
829
830 SDValue Arg = OutVals[i];
831
832 // Promote the value if needed.
833 switch (VA.getLocInfo()) {
834 default: llvm_unreachable("Unknown loc info!");
835 case CCValAssign::Full: break;
836 case CCValAssign::SExt:
837 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
838 break;
839 case CCValAssign::ZExt:
840 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
841 break;
842 case CCValAssign::AExt:
843 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
844 break;
845 }
846
847 // Arguments that can be passed on register must be kept at RegsToPass
848 // vector
849 if (VA.isRegLoc()) {
850 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
851 } else {
852 assert(VA.isMemLoc());
853
854 if (!StackPtr.getNode())
855 StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SP, PtrVT);
856
857 SDValue PtrOff =
858 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
859 DAG.getIntPtrConstant(VA.getLocMemOffset(), dl));
860
861 SDValue MemOp;
862 ISD::ArgFlagsTy Flags = Outs[i].Flags;
863
864 if (Flags.isByVal()) {
865 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i16);
866 MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode,
867 Flags.getNonZeroByValAlign(),
868 /*isVolatile*/ false,
869 /*AlwaysInline=*/true,
870 /*isTailCall=*/false,
871 /*MustPreserveCheriCapabilities=*/false,
872 MachinePointerInfo(), MachinePointerInfo());
873 } else {
874 MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo());
875 }
876
877 MemOpChains.push_back(MemOp);
878 }
879 }
880
881 // Transform all store nodes into one single node because all store nodes are
882 // independent of each other.
883 if (!MemOpChains.empty())
884 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
885
886 // Build a sequence of copy-to-reg nodes chained together with token chain and
887 // flag operands which copy the outgoing args into registers. The InFlag in
888 // necessary since all emitted instructions must be stuck together.
889 SDValue InFlag;
890 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
891 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
892 RegsToPass[i].second, InFlag);
893 InFlag = Chain.getValue(1);
894 }
895
896 // If the callee is a GlobalAddress node (quite common, every direct call is)
897 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
898 // Likewise ExternalSymbol -> TargetExternalSymbol.
899 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
900 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16);
901 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
902 Callee = DAG.getTargetExternalFunctionSymbol(E->getSymbol());
903
904 // Returns a chain & a flag for retval copy to use.
905 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
906 SmallVector<SDValue, 8> Ops;
907 Ops.push_back(Chain);
908 Ops.push_back(Callee);
909
910 // Add argument registers to the end of the list so that they are
911 // known live into the call.
912 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
913 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
914 RegsToPass[i].second.getValueType()));
915
916 if (InFlag.getNode())
917 Ops.push_back(InFlag);
918
919 Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, Ops);
920 InFlag = Chain.getValue(1);
921
922 // Create the CALLSEQ_END node.
923 Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, dl, PtrVT, true),
924 DAG.getConstant(0, dl, PtrVT, true), InFlag, dl);
925 InFlag = Chain.getValue(1);
926
927 // Handle result values, copying them out of physregs into vregs that we
928 // return.
929 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
930 DAG, InVals);
931 }
932
933 /// LowerCallResult - Lower the result values of a call into the
934 /// appropriate copies out of appropriate physical registers.
935 ///
LowerCallResult(SDValue Chain,SDValue InFlag,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const936 SDValue MSP430TargetLowering::LowerCallResult(
937 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
938 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
939 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
940
941 // Assign locations to each value returned by this call.
942 SmallVector<CCValAssign, 16> RVLocs;
943 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
944 *DAG.getContext());
945
946 AnalyzeReturnValues(CCInfo, RVLocs, Ins);
947
948 // Copy all of the result registers out of their specified physreg.
949 for (unsigned i = 0; i != RVLocs.size(); ++i) {
950 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
951 RVLocs[i].getValVT(), InFlag).getValue(1);
952 InFlag = Chain.getValue(2);
953 InVals.push_back(Chain.getValue(0));
954 }
955
956 return Chain;
957 }
958
LowerShifts(SDValue Op,SelectionDAG & DAG) const959 SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
960 SelectionDAG &DAG) const {
961 unsigned Opc = Op.getOpcode();
962 SDNode* N = Op.getNode();
963 EVT VT = Op.getValueType();
964 SDLoc dl(N);
965
966 // Expand non-constant shifts to loops:
967 if (!isa<ConstantSDNode>(N->getOperand(1)))
968 return Op;
969
970 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
971
972 // Expand the stuff into sequence of shifts.
973 SDValue Victim = N->getOperand(0);
974
975 if (ShiftAmount >= 8) {
976 assert(VT == MVT::i16 && "Can not shift i8 by 8 and more");
977 switch(Opc) {
978 default:
979 llvm_unreachable("Unknown shift");
980 case ISD::SHL:
981 // foo << (8 + N) => swpb(zext(foo)) << N
982 Victim = DAG.getZeroExtendInReg(Victim, dl, MVT::i8);
983 Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim);
984 break;
985 case ISD::SRA:
986 case ISD::SRL:
987 // foo >> (8 + N) => sxt(swpb(foo)) >> N
988 Victim = DAG.getNode(ISD::BSWAP, dl, VT, Victim);
989 Victim = (Opc == ISD::SRA)
990 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, Victim,
991 DAG.getValueType(MVT::i8))
992 : DAG.getZeroExtendInReg(Victim, dl, MVT::i8);
993 break;
994 }
995 ShiftAmount -= 8;
996 }
997
998 if (Opc == ISD::SRL && ShiftAmount) {
999 // Emit a special goodness here:
1000 // srl A, 1 => clrc; rrc A
1001 Victim = DAG.getNode(MSP430ISD::RRCL, dl, VT, Victim);
1002 ShiftAmount -= 1;
1003 }
1004
1005 while (ShiftAmount--)
1006 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
1007 dl, VT, Victim);
1008
1009 return Victim;
1010 }
1011
LowerGlobalAddress(SDValue Op,SelectionDAG & DAG) const1012 SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op,
1013 SelectionDAG &DAG) const {
1014 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1015 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
1016 auto PtrVT = getPointerTy(DAG.getDataLayout());
1017
1018 // Create the TargetGlobalAddress node, folding in the constant offset.
1019 SDValue Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op), PtrVT, Offset);
1020 return DAG.getNode(MSP430ISD::Wrapper, SDLoc(Op), PtrVT, Result);
1021 }
1022
LowerExternalSymbol(SDValue Op,SelectionDAG & DAG) const1023 SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
1024 SelectionDAG &DAG) const {
1025 SDLoc dl(Op);
1026 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
1027 auto PtrVT = getPointerTy(DAG.getDataLayout());
1028 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT);
1029
1030 return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);
1031 }
1032
LowerBlockAddress(SDValue Op,SelectionDAG & DAG) const1033 SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op,
1034 SelectionDAG &DAG) const {
1035 SDLoc dl(Op);
1036 auto PtrVT = getPointerTy(DAG.getDataLayout());
1037 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1038 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT);
1039
1040 return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);
1041 }
1042
EmitCMP(SDValue & LHS,SDValue & RHS,SDValue & TargetCC,ISD::CondCode CC,const SDLoc & dl,SelectionDAG & DAG)1043 static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
1044 ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG) {
1045 // FIXME: Handle bittests someday
1046 assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
1047
1048 // FIXME: Handle jump negative someday
1049 MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
1050 switch (CC) {
1051 default: llvm_unreachable("Invalid integer condition!");
1052 case ISD::SETEQ:
1053 TCC = MSP430CC::COND_E; // aka COND_Z
1054 // Minor optimization: if LHS is a constant, swap operands, then the
1055 // constant can be folded into comparison.
1056 if (LHS.getOpcode() == ISD::Constant)
1057 std::swap(LHS, RHS);
1058 break;
1059 case ISD::SETNE:
1060 TCC = MSP430CC::COND_NE; // aka COND_NZ
1061 // Minor optimization: if LHS is a constant, swap operands, then the
1062 // constant can be folded into comparison.
1063 if (LHS.getOpcode() == ISD::Constant)
1064 std::swap(LHS, RHS);
1065 break;
1066 case ISD::SETULE:
1067 std::swap(LHS, RHS);
1068 LLVM_FALLTHROUGH;
1069 case ISD::SETUGE:
1070 // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
1071 // fold constant into instruction.
1072 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1073 LHS = RHS;
1074 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1075 TCC = MSP430CC::COND_LO;
1076 break;
1077 }
1078 TCC = MSP430CC::COND_HS; // aka COND_C
1079 break;
1080 case ISD::SETUGT:
1081 std::swap(LHS, RHS);
1082 LLVM_FALLTHROUGH;
1083 case ISD::SETULT:
1084 // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
1085 // fold constant into instruction.
1086 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1087 LHS = RHS;
1088 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1089 TCC = MSP430CC::COND_HS;
1090 break;
1091 }
1092 TCC = MSP430CC::COND_LO; // aka COND_NC
1093 break;
1094 case ISD::SETLE:
1095 std::swap(LHS, RHS);
1096 LLVM_FALLTHROUGH;
1097 case ISD::SETGE:
1098 // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
1099 // fold constant into instruction.
1100 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1101 LHS = RHS;
1102 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1103 TCC = MSP430CC::COND_L;
1104 break;
1105 }
1106 TCC = MSP430CC::COND_GE;
1107 break;
1108 case ISD::SETGT:
1109 std::swap(LHS, RHS);
1110 LLVM_FALLTHROUGH;
1111 case ISD::SETLT:
1112 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
1113 // fold constant into instruction.
1114 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
1115 LHS = RHS;
1116 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
1117 TCC = MSP430CC::COND_GE;
1118 break;
1119 }
1120 TCC = MSP430CC::COND_L;
1121 break;
1122 }
1123
1124 TargetCC = DAG.getConstant(TCC, dl, MVT::i8);
1125 return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS);
1126 }
1127
1128
LowerBR_CC(SDValue Op,SelectionDAG & DAG) const1129 SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
1130 SDValue Chain = Op.getOperand(0);
1131 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1132 SDValue LHS = Op.getOperand(2);
1133 SDValue RHS = Op.getOperand(3);
1134 SDValue Dest = Op.getOperand(4);
1135 SDLoc dl (Op);
1136
1137 SDValue TargetCC;
1138 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1139
1140 return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
1141 Chain, Dest, TargetCC, Flag);
1142 }
1143
LowerSETCC(SDValue Op,SelectionDAG & DAG) const1144 SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1145 SDValue LHS = Op.getOperand(0);
1146 SDValue RHS = Op.getOperand(1);
1147 SDLoc dl (Op);
1148
1149 // If we are doing an AND and testing against zero, then the CMP
1150 // will not be generated. The AND (or BIT) will generate the condition codes,
1151 // but they are different from CMP.
1152 // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
1153 // lowering & isel wouldn't diverge.
1154 bool andCC = false;
1155 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1156 if (RHSC->isNullValue() && LHS.hasOneUse() &&
1157 (LHS.getOpcode() == ISD::AND ||
1158 (LHS.getOpcode() == ISD::TRUNCATE &&
1159 LHS.getOperand(0).getOpcode() == ISD::AND))) {
1160 andCC = true;
1161 }
1162 }
1163 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1164 SDValue TargetCC;
1165 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1166
1167 // Get the condition codes directly from the status register, if its easy.
1168 // Otherwise a branch will be generated. Note that the AND and BIT
1169 // instructions generate different flags than CMP, the carry bit can be used
1170 // for NE/EQ.
1171 bool Invert = false;
1172 bool Shift = false;
1173 bool Convert = true;
1174 switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
1175 default:
1176 Convert = false;
1177 break;
1178 case MSP430CC::COND_HS:
1179 // Res = SR & 1, no processing is required
1180 break;
1181 case MSP430CC::COND_LO:
1182 // Res = ~(SR & 1)
1183 Invert = true;
1184 break;
1185 case MSP430CC::COND_NE:
1186 if (andCC) {
1187 // C = ~Z, thus Res = SR & 1, no processing is required
1188 } else {
1189 // Res = ~((SR >> 1) & 1)
1190 Shift = true;
1191 Invert = true;
1192 }
1193 break;
1194 case MSP430CC::COND_E:
1195 Shift = true;
1196 // C = ~Z for AND instruction, thus we can put Res = ~(SR & 1), however,
1197 // Res = (SR >> 1) & 1 is 1 word shorter.
1198 break;
1199 }
1200 EVT VT = Op.getValueType();
1201 SDValue One = DAG.getConstant(1, dl, VT);
1202 if (Convert) {
1203 SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SR,
1204 MVT::i16, Flag);
1205 if (Shift)
1206 // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
1207 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
1208 SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
1209 if (Invert)
1210 SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
1211 return SR;
1212 } else {
1213 SDValue Zero = DAG.getConstant(0, dl, VT);
1214 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1215 SDValue Ops[] = {One, Zero, TargetCC, Flag};
1216 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
1217 }
1218 }
1219
LowerSELECT_CC(SDValue Op,SelectionDAG & DAG) const1220 SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op,
1221 SelectionDAG &DAG) const {
1222 SDValue LHS = Op.getOperand(0);
1223 SDValue RHS = Op.getOperand(1);
1224 SDValue TrueV = Op.getOperand(2);
1225 SDValue FalseV = Op.getOperand(3);
1226 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1227 SDLoc dl (Op);
1228
1229 SDValue TargetCC;
1230 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1231
1232 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1233 SDValue Ops[] = {TrueV, FalseV, TargetCC, Flag};
1234
1235 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
1236 }
1237
LowerSIGN_EXTEND(SDValue Op,SelectionDAG & DAG) const1238 SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
1239 SelectionDAG &DAG) const {
1240 SDValue Val = Op.getOperand(0);
1241 EVT VT = Op.getValueType();
1242 SDLoc dl(Op);
1243
1244 assert(VT == MVT::i16 && "Only support i16 for now!");
1245
1246 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
1247 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
1248 DAG.getValueType(Val.getValueType()));
1249 }
1250
1251 SDValue
getReturnAddressFrameIndex(SelectionDAG & DAG) const1252 MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
1253 MachineFunction &MF = DAG.getMachineFunction();
1254 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
1255 int ReturnAddrIndex = FuncInfo->getRAIndex();
1256 auto PtrVT = getPointerTy(MF.getDataLayout());
1257
1258 if (ReturnAddrIndex == 0) {
1259 // Set up a frame object for the return address.
1260 uint64_t SlotSize = MF.getDataLayout().getPointerSize();
1261 ReturnAddrIndex = MF.getFrameInfo().CreateFixedObject(SlotSize, -SlotSize,
1262 true);
1263 FuncInfo->setRAIndex(ReturnAddrIndex);
1264 }
1265
1266 return DAG.getFrameIndex(ReturnAddrIndex, PtrVT);
1267 }
1268
LowerRETURNADDR(SDValue Op,SelectionDAG & DAG) const1269 SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op,
1270 SelectionDAG &DAG) const {
1271 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1272 MFI.setReturnAddressIsTaken(true);
1273
1274 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
1275 return SDValue();
1276
1277 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1278 SDLoc dl(Op);
1279 auto PtrVT = getPointerTy(DAG.getDataLayout());
1280
1281 if (Depth > 0) {
1282 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1283 SDValue Offset =
1284 DAG.getConstant(DAG.getDataLayout().getPointerSize(), dl, MVT::i16);
1285 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1286 DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
1287 MachinePointerInfo());
1288 }
1289
1290 // Just load the return address.
1291 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
1292 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI,
1293 MachinePointerInfo());
1294 }
1295
LowerFRAMEADDR(SDValue Op,SelectionDAG & DAG) const1296 SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op,
1297 SelectionDAG &DAG) const {
1298 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1299 MFI.setFrameAddressIsTaken(true);
1300
1301 EVT VT = Op.getValueType();
1302 SDLoc dl(Op); // FIXME probably not meaningful
1303 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1304 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1305 MSP430::R4, VT);
1306 while (Depth--)
1307 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1308 MachinePointerInfo());
1309 return FrameAddr;
1310 }
1311
LowerVASTART(SDValue Op,SelectionDAG & DAG) const1312 SDValue MSP430TargetLowering::LowerVASTART(SDValue Op,
1313 SelectionDAG &DAG) const {
1314 MachineFunction &MF = DAG.getMachineFunction();
1315 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
1316 auto PtrVT = getPointerTy(DAG.getDataLayout());
1317
1318 // Frame index of first vararg argument
1319 SDValue FrameIndex =
1320 DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1321 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1322
1323 // Create a store of the frame index to the location operand
1324 return DAG.getStore(Op.getOperand(0), SDLoc(Op), FrameIndex, Op.getOperand(1),
1325 MachinePointerInfo(SV));
1326 }
1327
LowerJumpTable(SDValue Op,SelectionDAG & DAG) const1328 SDValue MSP430TargetLowering::LowerJumpTable(SDValue Op,
1329 SelectionDAG &DAG) const {
1330 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1331 auto PtrVT = getPointerTy(DAG.getDataLayout());
1332 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1333 return DAG.getNode(MSP430ISD::Wrapper, SDLoc(JT), PtrVT, Result);
1334 }
1335
1336 /// getPostIndexedAddressParts - returns true by value, base pointer and
1337 /// offset pointer and addressing mode by reference if this node can be
1338 /// combined with a load / store to form a post-indexed load / store.
getPostIndexedAddressParts(SDNode * N,SDNode * Op,SDValue & Base,SDValue & Offset,ISD::MemIndexedMode & AM,SelectionDAG & DAG) const1339 bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1340 SDValue &Base,
1341 SDValue &Offset,
1342 ISD::MemIndexedMode &AM,
1343 SelectionDAG &DAG) const {
1344
1345 LoadSDNode *LD = cast<LoadSDNode>(N);
1346 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1347 return false;
1348
1349 EVT VT = LD->getMemoryVT();
1350 if (VT != MVT::i8 && VT != MVT::i16)
1351 return false;
1352
1353 if (Op->getOpcode() != ISD::ADD)
1354 return false;
1355
1356 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1357 uint64_t RHSC = RHS->getZExtValue();
1358 if ((VT == MVT::i16 && RHSC != 2) ||
1359 (VT == MVT::i8 && RHSC != 1))
1360 return false;
1361
1362 Base = Op->getOperand(0);
1363 Offset = DAG.getConstant(RHSC, SDLoc(N), VT);
1364 AM = ISD::POST_INC;
1365 return true;
1366 }
1367
1368 return false;
1369 }
1370
1371
getTargetNodeName(unsigned Opcode) const1372 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
1373 switch ((MSP430ISD::NodeType)Opcode) {
1374 case MSP430ISD::FIRST_NUMBER: break;
1375 case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG";
1376 case MSP430ISD::RETI_FLAG: return "MSP430ISD::RETI_FLAG";
1377 case MSP430ISD::RRA: return "MSP430ISD::RRA";
1378 case MSP430ISD::RLA: return "MSP430ISD::RLA";
1379 case MSP430ISD::RRC: return "MSP430ISD::RRC";
1380 case MSP430ISD::RRCL: return "MSP430ISD::RRCL";
1381 case MSP430ISD::CALL: return "MSP430ISD::CALL";
1382 case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper";
1383 case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC";
1384 case MSP430ISD::CMP: return "MSP430ISD::CMP";
1385 case MSP430ISD::SETCC: return "MSP430ISD::SETCC";
1386 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC";
1387 case MSP430ISD::DADD: return "MSP430ISD::DADD";
1388 }
1389 return nullptr;
1390 }
1391
isTruncateFree(Type * Ty1,Type * Ty2) const1392 bool MSP430TargetLowering::isTruncateFree(Type *Ty1,
1393 Type *Ty2) const {
1394 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
1395 return false;
1396
1397 return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
1398 }
1399
isTruncateFree(EVT VT1,EVT VT2) const1400 bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1401 if (!VT1.isInteger() || !VT2.isInteger())
1402 return false;
1403
1404 return (VT1.getSizeInBits() > VT2.getSizeInBits());
1405 }
1406
isZExtFree(Type * Ty1,Type * Ty2) const1407 bool MSP430TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
1408 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1409 return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1410 }
1411
isZExtFree(EVT VT1,EVT VT2) const1412 bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
1413 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1414 return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
1415 }
1416
isZExtFree(SDValue Val,EVT VT2) const1417 bool MSP430TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
1418 return isZExtFree(Val.getValueType(), VT2);
1419 }
1420
1421 //===----------------------------------------------------------------------===//
1422 // Other Lowering Code
1423 //===----------------------------------------------------------------------===//
1424
1425 MachineBasicBlock *
EmitShiftInstr(MachineInstr & MI,MachineBasicBlock * BB) const1426 MSP430TargetLowering::EmitShiftInstr(MachineInstr &MI,
1427 MachineBasicBlock *BB) const {
1428 MachineFunction *F = BB->getParent();
1429 MachineRegisterInfo &RI = F->getRegInfo();
1430 DebugLoc dl = MI.getDebugLoc();
1431 const TargetInstrInfo &TII = *F->getSubtarget().getInstrInfo();
1432
1433 unsigned Opc;
1434 bool ClearCarry = false;
1435 const TargetRegisterClass * RC;
1436 switch (MI.getOpcode()) {
1437 default: llvm_unreachable("Invalid shift opcode!");
1438 case MSP430::Shl8:
1439 Opc = MSP430::ADD8rr;
1440 RC = &MSP430::GR8RegClass;
1441 break;
1442 case MSP430::Shl16:
1443 Opc = MSP430::ADD16rr;
1444 RC = &MSP430::GR16RegClass;
1445 break;
1446 case MSP430::Sra8:
1447 Opc = MSP430::RRA8r;
1448 RC = &MSP430::GR8RegClass;
1449 break;
1450 case MSP430::Sra16:
1451 Opc = MSP430::RRA16r;
1452 RC = &MSP430::GR16RegClass;
1453 break;
1454 case MSP430::Srl8:
1455 ClearCarry = true;
1456 Opc = MSP430::RRC8r;
1457 RC = &MSP430::GR8RegClass;
1458 break;
1459 case MSP430::Srl16:
1460 ClearCarry = true;
1461 Opc = MSP430::RRC16r;
1462 RC = &MSP430::GR16RegClass;
1463 break;
1464 case MSP430::Rrcl8:
1465 case MSP430::Rrcl16: {
1466 BuildMI(*BB, MI, dl, TII.get(MSP430::BIC16rc), MSP430::SR)
1467 .addReg(MSP430::SR).addImm(1);
1468 Register SrcReg = MI.getOperand(1).getReg();
1469 Register DstReg = MI.getOperand(0).getReg();
1470 unsigned RrcOpc = MI.getOpcode() == MSP430::Rrcl16
1471 ? MSP430::RRC16r : MSP430::RRC8r;
1472 BuildMI(*BB, MI, dl, TII.get(RrcOpc), DstReg)
1473 .addReg(SrcReg);
1474 MI.eraseFromParent(); // The pseudo instruction is gone now.
1475 return BB;
1476 }
1477 }
1478
1479 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1480 MachineFunction::iterator I = ++BB->getIterator();
1481
1482 // Create loop block
1483 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1484 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1485
1486 F->insert(I, LoopBB);
1487 F->insert(I, RemBB);
1488
1489 // Update machine-CFG edges by transferring all successors of the current
1490 // block to the block containing instructions after shift.
1491 RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1492 BB->end());
1493 RemBB->transferSuccessorsAndUpdatePHIs(BB);
1494
1495 // Add edges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1496 BB->addSuccessor(LoopBB);
1497 BB->addSuccessor(RemBB);
1498 LoopBB->addSuccessor(RemBB);
1499 LoopBB->addSuccessor(LoopBB);
1500
1501 Register ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass);
1502 Register ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass);
1503 Register ShiftReg = RI.createVirtualRegister(RC);
1504 Register ShiftReg2 = RI.createVirtualRegister(RC);
1505 Register ShiftAmtSrcReg = MI.getOperand(2).getReg();
1506 Register SrcReg = MI.getOperand(1).getReg();
1507 Register DstReg = MI.getOperand(0).getReg();
1508
1509 // BB:
1510 // cmp 0, N
1511 // je RemBB
1512 BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1513 .addReg(ShiftAmtSrcReg).addImm(0);
1514 BuildMI(BB, dl, TII.get(MSP430::JCC))
1515 .addMBB(RemBB)
1516 .addImm(MSP430CC::COND_E);
1517
1518 // LoopBB:
1519 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1520 // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1521 // ShiftReg2 = shift ShiftReg
1522 // ShiftAmt2 = ShiftAmt - 1;
1523 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1524 .addReg(SrcReg).addMBB(BB)
1525 .addReg(ShiftReg2).addMBB(LoopBB);
1526 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1527 .addReg(ShiftAmtSrcReg).addMBB(BB)
1528 .addReg(ShiftAmtReg2).addMBB(LoopBB);
1529 if (ClearCarry)
1530 BuildMI(LoopBB, dl, TII.get(MSP430::BIC16rc), MSP430::SR)
1531 .addReg(MSP430::SR).addImm(1);
1532 if (Opc == MSP430::ADD8rr || Opc == MSP430::ADD16rr)
1533 BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1534 .addReg(ShiftReg)
1535 .addReg(ShiftReg);
1536 else
1537 BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1538 .addReg(ShiftReg);
1539 BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1540 .addReg(ShiftAmtReg).addImm(1);
1541 BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1542 .addMBB(LoopBB)
1543 .addImm(MSP430CC::COND_NE);
1544
1545 // RemBB:
1546 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1547 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1548 .addReg(SrcReg).addMBB(BB)
1549 .addReg(ShiftReg2).addMBB(LoopBB);
1550
1551 MI.eraseFromParent(); // The pseudo instruction is gone now.
1552 return RemBB;
1553 }
1554
1555 MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr & MI,MachineBasicBlock * BB) const1556 MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1557 MachineBasicBlock *BB) const {
1558 unsigned Opc = MI.getOpcode();
1559
1560 if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1561 Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1562 Opc == MSP430::Srl8 || Opc == MSP430::Srl16 ||
1563 Opc == MSP430::Rrcl8 || Opc == MSP430::Rrcl16)
1564 return EmitShiftInstr(MI, BB);
1565
1566 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
1567 DebugLoc dl = MI.getDebugLoc();
1568
1569 assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1570 "Unexpected instr type to insert");
1571
1572 // To "insert" a SELECT instruction, we actually have to insert the diamond
1573 // control-flow pattern. The incoming instruction knows the destination vreg
1574 // to set, the condition code register to branch on, the true/false values to
1575 // select between, and a branch opcode to use.
1576 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1577 MachineFunction::iterator I = ++BB->getIterator();
1578
1579 // thisMBB:
1580 // ...
1581 // TrueVal = ...
1582 // cmpTY ccX, r1, r2
1583 // jCC copy1MBB
1584 // fallthrough --> copy0MBB
1585 MachineBasicBlock *thisMBB = BB;
1586 MachineFunction *F = BB->getParent();
1587 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1588 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1589 F->insert(I, copy0MBB);
1590 F->insert(I, copy1MBB);
1591 // Update machine-CFG edges by transferring all successors of the current
1592 // block to the new block which will contain the Phi node for the select.
1593 copy1MBB->splice(copy1MBB->begin(), BB,
1594 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1595 copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
1596 // Next, add the true and fallthrough blocks as its successors.
1597 BB->addSuccessor(copy0MBB);
1598 BB->addSuccessor(copy1MBB);
1599
1600 BuildMI(BB, dl, TII.get(MSP430::JCC))
1601 .addMBB(copy1MBB)
1602 .addImm(MI.getOperand(3).getImm());
1603
1604 // copy0MBB:
1605 // %FalseValue = ...
1606 // # fallthrough to copy1MBB
1607 BB = copy0MBB;
1608
1609 // Update machine-CFG edges
1610 BB->addSuccessor(copy1MBB);
1611
1612 // copy1MBB:
1613 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1614 // ...
1615 BB = copy1MBB;
1616 BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), MI.getOperand(0).getReg())
1617 .addReg(MI.getOperand(2).getReg())
1618 .addMBB(copy0MBB)
1619 .addReg(MI.getOperand(1).getReg())
1620 .addMBB(thisMBB);
1621
1622 MI.eraseFromParent(); // The pseudo instruction is gone now.
1623 return BB;
1624 }
1625