1 //===---- MipsABIInfo.h - Information about MIPS ABI's --------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIINFO_H 10 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIINFO_H 11 12 #include "llvm/ADT/Triple.h" 13 #include "llvm/IR/CallingConv.h" 14 #include "llvm/MC/MCRegisterInfo.h" 15 #include "llvm/MC/MCTargetOptions.h" 16 17 namespace llvm { 18 19 template <typename T> class ArrayRef; 20 class MCTargetOptions; 21 class MCAsmInfo; 22 class StringRef; 23 24 class MipsABIInfo { 25 public: 26 enum class ABI { Unknown, O32, N32, N64 }; 27 28 protected: 29 ABI ThisABI; 30 bool isCheriPureCap = false; 31 32 public: ThisABI(ThisABI)33 MipsABIInfo(ABI ThisABI, bool isAllCap=false) : ThisABI(ThisABI), 34 isCheriPureCap(isAllCap) {} 35 Unknown()36 static MipsABIInfo Unknown() { return MipsABIInfo(ABI::Unknown); } O32()37 static MipsABIInfo O32() { return MipsABIInfo(ABI::O32); } N32()38 static MipsABIInfo N32() { return MipsABIInfo(ABI::N32); } N64()39 static MipsABIInfo N64() { return MipsABIInfo(ABI::N64); } CheriPureCap()40 static MipsABIInfo CheriPureCap() { return MipsABIInfo(ABI::N64, true); } 41 static MipsABIInfo computeTargetABI(const Triple &TT, StringRef CPU, 42 const MCTargetOptions &Options); 43 IsKnown()44 bool IsKnown() const { return ThisABI != ABI::Unknown; } IsO32()45 bool IsO32() const { return ThisABI == ABI::O32; } IsN32()46 bool IsN32() const { return ThisABI == ABI::N32; } IsN64()47 bool IsN64() const { return ThisABI == ABI::N64; } IsCheriPureCap()48 bool IsCheriPureCap() const { return isCheriPureCap; } CapabilityTableABI()49 CheriCapabilityTableABI CapabilityTableABI() const { 50 assert(IsCheriPureCap()); 51 return MCTargetOptions::cheriCapabilityTableABI(); 52 } StackAddrSpace()53 unsigned StackAddrSpace() const { return isCheriPureCap ? 200 : 0; } GetEnumValue()54 ABI GetEnumValue() const { return ThisABI; } 55 56 /// The registers to use for byval arguments. 57 ArrayRef<MCPhysReg> GetByValArgRegs() const; 58 59 /// The registers to use for the variable argument list. 60 ArrayRef<MCPhysReg> GetVarArgRegs() const; 61 62 /// Obtain the size of the area allocated by the callee for arguments. 63 /// CallingConv::FastCall affects the value for O32. 64 unsigned GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const; 65 66 /// Ordering of ABI's 67 /// MipsGenSubtargetInfo.inc will use this to resolve conflicts when given 68 /// multiple ABI options. 69 bool operator<(const MipsABIInfo Other) const { 70 return ThisABI < Other.GetEnumValue(); 71 } 72 73 unsigned GetDefaultDataCapability() const; 74 unsigned GetReturnAddress() const; 75 unsigned GetStackPtr() const; 76 unsigned GetFramePtr() const; 77 unsigned GetBasePtr() const; 78 unsigned GetGlobalPtr() const; 79 /// This method will eventually be replaced by GetGlobalPtr in 80 /// pure-capability mode, but until all of the new linker work is done we 81 /// need a separate $gp and $cgp as a transition step. 82 unsigned GetGlobalCapability() const; 83 unsigned GetNullPtr() const; 84 unsigned GetZeroReg() const; 85 unsigned GetPtrAdduOp() const; 86 unsigned GetPtrAddiuOp() const; 87 unsigned GetPtrSubuOp() const; 88 unsigned GetPtrAndOp() const; 89 unsigned GetGPRMoveOp() const; 90 unsigned GetSPMoveOp() const; ArePtrs64bit()91 inline bool ArePtrs64bit() const { return IsN64(); } AreGprs64bit()92 inline bool AreGprs64bit() const { return IsN32() || IsN64(); } 93 94 unsigned GetEhDataReg(unsigned I) const; 95 96 // Update the initial CFA register from SP to C11 if needed 97 void updateCheriInitialFrameStateHack(const MCAsmInfo &MAI, 98 const MCRegisterInfo &MRI); 99 }; 100 } 101 102 #endif 103