1 //===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Mips specific target streamer methods.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsTargetStreamer.h"
14 #include "MipsInstPrinter.h"
15 #include "MCTargetDesc/MipsABIInfo.h"
16 #include "MipsELFStreamer.h"
17 #include "MipsMCExpr.h"
18 #include "MipsMCTargetDesc.h"
19 #include "MipsTargetObjectFile.h"
20 #include "llvm/BinaryFormat/ELF.h"
21 #include "llvm/CHERI/cheri-compressed-cap/cheri_compressed_cap.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCSectionELF.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MCSymbolELF.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/FormattedStream.h"
29 
30 using namespace llvm;
31 
32 namespace {
33 static cl::opt<bool> RoundSectionSizes(
34     "mips-round-section-sizes", cl::init(false),
35     cl::desc("Round section sizes up to the section alignment"), cl::Hidden);
36 } // end anonymous namespace
37 
getCheriCapabilitySize(FeatureBitset Features)38 llvm::Optional<unsigned> llvm::getCheriCapabilitySize(FeatureBitset Features) {
39   if (Features[Mips::FeatureMipsCheri256]) {
40     assert(Features[Mips::FeatureMipsCheri]);
41     return 32;
42   }
43   if (Features[Mips::FeatureMipsCheri128]) {
44     assert(Features[Mips::FeatureMipsCheri]);
45     return 16;
46   }
47   if (Features[Mips::FeatureMipsCheri64]) {
48     assert(Features[Mips::FeatureMipsCheri]);
49     return 8;
50   }
51   assert(!Features[Mips::FeatureMipsCheri]);
52   return None;
53 }
54 
isMicroMips(const MCSubtargetInfo * STI)55 static bool isMicroMips(const MCSubtargetInfo *STI) {
56   return STI->getFeatureBits()[Mips::FeatureMicroMips];
57 }
58 
MipsTargetStreamer(MCStreamer & S)59 MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S)
60     : MCTargetStreamer(S), GPReg(Mips::GP), ModuleDirectiveAllowed(true) {
61   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
62 }
emitDirectiveSetMicroMips()63 void MipsTargetStreamer::emitDirectiveSetMicroMips() {}
emitDirectiveSetNoMicroMips()64 void MipsTargetStreamer::emitDirectiveSetNoMicroMips() {}
setUsesMicroMips()65 void MipsTargetStreamer::setUsesMicroMips() {}
emitDirectiveSetMips16()66 void MipsTargetStreamer::emitDirectiveSetMips16() {}
emitDirectiveSetNoMips16()67 void MipsTargetStreamer::emitDirectiveSetNoMips16() { forbidModuleDirective(); }
emitDirectiveSetReorder()68 void MipsTargetStreamer::emitDirectiveSetReorder() { forbidModuleDirective(); }
emitDirectiveSetNoReorder()69 void MipsTargetStreamer::emitDirectiveSetNoReorder() {}
emitDirectiveSetMacro()70 void MipsTargetStreamer::emitDirectiveSetMacro() { forbidModuleDirective(); }
emitDirectiveSetNoMacro()71 void MipsTargetStreamer::emitDirectiveSetNoMacro() { forbidModuleDirective(); }
emitDirectiveSetMsa()72 void MipsTargetStreamer::emitDirectiveSetMsa() { forbidModuleDirective(); }
emitDirectiveSetNoMsa()73 void MipsTargetStreamer::emitDirectiveSetNoMsa() { forbidModuleDirective(); }
emitDirectiveSetMt()74 void MipsTargetStreamer::emitDirectiveSetMt() {}
emitDirectiveSetNoMt()75 void MipsTargetStreamer::emitDirectiveSetNoMt() { forbidModuleDirective(); }
emitDirectiveSetCRC()76 void MipsTargetStreamer::emitDirectiveSetCRC() {}
emitDirectiveSetNoCRC()77 void MipsTargetStreamer::emitDirectiveSetNoCRC() {}
emitDirectiveSetVirt()78 void MipsTargetStreamer::emitDirectiveSetVirt() {}
emitDirectiveSetNoVirt()79 void MipsTargetStreamer::emitDirectiveSetNoVirt() {}
emitDirectiveSetGINV()80 void MipsTargetStreamer::emitDirectiveSetGINV() {}
emitDirectiveSetNoGINV()81 void MipsTargetStreamer::emitDirectiveSetNoGINV() {}
emitDirectiveSetAt()82 void MipsTargetStreamer::emitDirectiveSetAt() { forbidModuleDirective(); }
emitDirectiveSetAtWithArg(unsigned RegNo)83 void MipsTargetStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
84   forbidModuleDirective();
85 }
emitDirectiveSetNoAt()86 void MipsTargetStreamer::emitDirectiveSetNoAt() { forbidModuleDirective(); }
emitDirectiveEnd(StringRef Name)87 void MipsTargetStreamer::emitDirectiveEnd(StringRef Name) {}
emitDirectiveEnt(const MCSymbol & Symbol)88 void MipsTargetStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {}
emitDirectiveAbiCalls()89 void MipsTargetStreamer::emitDirectiveAbiCalls() {}
emitDirectiveNaN2008()90 void MipsTargetStreamer::emitDirectiveNaN2008() {}
emitDirectiveNaNLegacy()91 void MipsTargetStreamer::emitDirectiveNaNLegacy() {}
emitDirectiveOptionPic0()92 void MipsTargetStreamer::emitDirectiveOptionPic0() {}
emitDirectiveOptionPic2()93 void MipsTargetStreamer::emitDirectiveOptionPic2() {}
emitDirectiveInsn()94 void MipsTargetStreamer::emitDirectiveInsn() { forbidModuleDirective(); }
emitFrame(unsigned StackReg,unsigned StackSize,unsigned ReturnReg)95 void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
96                                    unsigned ReturnReg) {}
emitMask(unsigned CPUBitmask,int CPUTopSavedRegOff)97 void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
emitFMask(unsigned FPUBitmask,int FPUTopSavedRegOff)98 void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
99 }
emitDirectiveSetArch(StringRef Arch)100 void MipsTargetStreamer::emitDirectiveSetArch(StringRef Arch) {
101   forbidModuleDirective();
102 }
emitDirectiveSetMips0()103 void MipsTargetStreamer::emitDirectiveSetMips0() { forbidModuleDirective(); }
emitDirectiveSetMips1()104 void MipsTargetStreamer::emitDirectiveSetMips1() { forbidModuleDirective(); }
emitDirectiveSetMips2()105 void MipsTargetStreamer::emitDirectiveSetMips2() { forbidModuleDirective(); }
emitDirectiveSetMips3()106 void MipsTargetStreamer::emitDirectiveSetMips3() { forbidModuleDirective(); }
emitDirectiveSetMips4()107 void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); }
emitDirectiveSetMips5()108 void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); }
emitDirectiveSetMips32()109 void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); }
emitDirectiveSetMips32R2()110 void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); }
emitDirectiveSetMips32R3()111 void MipsTargetStreamer::emitDirectiveSetMips32R3() { forbidModuleDirective(); }
emitDirectiveSetMips32R5()112 void MipsTargetStreamer::emitDirectiveSetMips32R5() { forbidModuleDirective(); }
emitDirectiveSetMips32R6()113 void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); }
emitDirectiveSetMips64()114 void MipsTargetStreamer::emitDirectiveSetMips64() { forbidModuleDirective(); }
emitDirectiveSetMips64R2()115 void MipsTargetStreamer::emitDirectiveSetMips64R2() { forbidModuleDirective(); }
emitDirectiveSetMips64R3()116 void MipsTargetStreamer::emitDirectiveSetMips64R3() { forbidModuleDirective(); }
emitDirectiveSetMips64R5()117 void MipsTargetStreamer::emitDirectiveSetMips64R5() { forbidModuleDirective(); }
emitDirectiveSetMips64R6()118 void MipsTargetStreamer::emitDirectiveSetMips64R6() { forbidModuleDirective(); }
emitDirectiveSetPop()119 void MipsTargetStreamer::emitDirectiveSetPop() { forbidModuleDirective(); }
emitDirectiveSetPush()120 void MipsTargetStreamer::emitDirectiveSetPush() { forbidModuleDirective(); }
emitDirectiveSetSoftFloat()121 void MipsTargetStreamer::emitDirectiveSetSoftFloat() {
122   forbidModuleDirective();
123 }
emitDirectiveSetHardFloat()124 void MipsTargetStreamer::emitDirectiveSetHardFloat() {
125   forbidModuleDirective();
126 }
emitDirectiveSetDsp()127 void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); }
emitDirectiveSetDspr2()128 void MipsTargetStreamer::emitDirectiveSetDspr2() { forbidModuleDirective(); }
emitDirectiveSetNoDsp()129 void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); }
emitDirectiveSetMips3D()130 void MipsTargetStreamer::emitDirectiveSetMips3D() { forbidModuleDirective(); }
emitDirectiveSetNoMips3D()131 void MipsTargetStreamer::emitDirectiveSetNoMips3D() { forbidModuleDirective(); }
emitDirectiveCpAdd(unsigned RegNo)132 void MipsTargetStreamer::emitDirectiveCpAdd(unsigned RegNo) {}
emitDirectiveCpLoad(unsigned RegNo)133 void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {}
emitDirectiveCpLocal(unsigned RegNo)134 void MipsTargetStreamer::emitDirectiveCpLocal(unsigned RegNo) {
135   // .cplocal $reg
136   // This directive forces to use the alternate register for context pointer.
137   // For example
138   //   .cplocal $4
139   //   jal foo
140   // expands to
141   //   ld    $25, %call16(foo)($4)
142   //   jalr  $25
143 
144   if (!getABI().IsN32() && !getABI().IsN64())
145     return;
146 
147   GPReg = RegNo;
148 
149   forbidModuleDirective();
150 }
emitDirectiveCpRestore(int Offset,function_ref<unsigned ()> GetATReg,SMLoc IDLoc,const MCSubtargetInfo * STI)151 bool MipsTargetStreamer::emitDirectiveCpRestore(
152     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
153     const MCSubtargetInfo *STI) {
154   forbidModuleDirective();
155   return true;
156 }
emitDirectiveCpsetup(unsigned RegNo,int RegOrOffset,const MCSymbol & Sym,bool IsReg)157 void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
158                                               const MCSymbol &Sym, bool IsReg) {
159 }
emitDirectiveCpreturn(unsigned SaveLocation,bool SaveLocationIsRegister)160 void MipsTargetStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
161                                                bool SaveLocationIsRegister) {}
162 
emitDirectiveModuleFP()163 void MipsTargetStreamer::emitDirectiveModuleFP() {}
164 
emitDirectiveModuleOddSPReg()165 void MipsTargetStreamer::emitDirectiveModuleOddSPReg() {
166   if (!ABIFlagsSection.OddSPReg && !ABIFlagsSection.Is32BitABI)
167     report_fatal_error("+nooddspreg is only valid for O32");
168 }
emitDirectiveModuleSoftFloat()169 void MipsTargetStreamer::emitDirectiveModuleSoftFloat() {}
emitDirectiveModuleHardFloat()170 void MipsTargetStreamer::emitDirectiveModuleHardFloat() {}
emitDirectiveModuleMT()171 void MipsTargetStreamer::emitDirectiveModuleMT() {}
emitDirectiveModuleCRC()172 void MipsTargetStreamer::emitDirectiveModuleCRC() {}
emitDirectiveModuleNoCRC()173 void MipsTargetStreamer::emitDirectiveModuleNoCRC() {}
emitDirectiveModuleVirt()174 void MipsTargetStreamer::emitDirectiveModuleVirt() {}
emitDirectiveModuleNoVirt()175 void MipsTargetStreamer::emitDirectiveModuleNoVirt() {}
emitDirectiveModuleGINV()176 void MipsTargetStreamer::emitDirectiveModuleGINV() {}
emitDirectiveModuleNoGINV()177 void MipsTargetStreamer::emitDirectiveModuleNoGINV() {}
emitDirectiveSetFp(MipsABIFlagsSection::FpABIKind Value)178 void MipsTargetStreamer::emitDirectiveSetFp(
179     MipsABIFlagsSection::FpABIKind Value) {
180   forbidModuleDirective();
181 }
emitDirectiveSetOddSPReg()182 void MipsTargetStreamer::emitDirectiveSetOddSPReg() { forbidModuleDirective(); }
emitDirectiveSetNoOddSPReg()183 void MipsTargetStreamer::emitDirectiveSetNoOddSPReg() {
184   forbidModuleDirective();
185 }
186 
emitR(unsigned Opcode,unsigned Reg0,SMLoc IDLoc,const MCSubtargetInfo * STI)187 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
188                                const MCSubtargetInfo *STI) {
189   MCInst TmpInst;
190   TmpInst.setOpcode(Opcode);
191   TmpInst.addOperand(MCOperand::createReg(Reg0));
192   TmpInst.setLoc(IDLoc);
193   getStreamer().emitInstruction(TmpInst, *STI);
194 }
195 
emitRX(unsigned Opcode,unsigned Reg0,MCOperand Op1,SMLoc IDLoc,const MCSubtargetInfo * STI)196 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1,
197                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
198   MCInst TmpInst;
199   TmpInst.setOpcode(Opcode);
200   TmpInst.addOperand(MCOperand::createReg(Reg0));
201   TmpInst.addOperand(Op1);
202   TmpInst.setLoc(IDLoc);
203   getStreamer().emitInstruction(TmpInst, *STI);
204 }
205 
emitRI(unsigned Opcode,unsigned Reg0,int32_t Imm,SMLoc IDLoc,const MCSubtargetInfo * STI)206 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm,
207                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
208   emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI);
209 }
210 
emitRR(unsigned Opcode,unsigned Reg0,unsigned Reg1,SMLoc IDLoc,const MCSubtargetInfo * STI)211 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
212                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
213   emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI);
214 }
215 
emitII(unsigned Opcode,int16_t Imm1,int16_t Imm2,SMLoc IDLoc,const MCSubtargetInfo * STI)216 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2,
217                                 SMLoc IDLoc, const MCSubtargetInfo *STI) {
218   MCInst TmpInst;
219   TmpInst.setOpcode(Opcode);
220   TmpInst.addOperand(MCOperand::createImm(Imm1));
221   TmpInst.addOperand(MCOperand::createImm(Imm2));
222   TmpInst.setLoc(IDLoc);
223   getStreamer().emitInstruction(TmpInst, *STI);
224 }
225 
emitRRX(unsigned Opcode,unsigned Reg0,unsigned Reg1,MCOperand Op2,SMLoc IDLoc,const MCSubtargetInfo * STI)226 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
227                                  MCOperand Op2, SMLoc IDLoc,
228                                  const MCSubtargetInfo *STI) {
229   MCInst TmpInst;
230   TmpInst.setOpcode(Opcode);
231   TmpInst.addOperand(MCOperand::createReg(Reg0));
232   TmpInst.addOperand(MCOperand::createReg(Reg1));
233   TmpInst.addOperand(Op2);
234   TmpInst.setLoc(IDLoc);
235   getStreamer().emitInstruction(TmpInst, *STI);
236 }
237 
emitRRR(unsigned Opcode,unsigned Reg0,unsigned Reg1,unsigned Reg2,SMLoc IDLoc,const MCSubtargetInfo * STI)238 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1,
239                                  unsigned Reg2, SMLoc IDLoc,
240                                  const MCSubtargetInfo *STI) {
241   emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI);
242 }
243 
emitRRRX(unsigned Opcode,unsigned Reg0,unsigned Reg1,unsigned Reg2,MCOperand Op3,SMLoc IDLoc,const MCSubtargetInfo * STI)244 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1,
245                                   unsigned Reg2, MCOperand Op3, SMLoc IDLoc,
246                                   const MCSubtargetInfo *STI) {
247   MCInst TmpInst;
248   TmpInst.setOpcode(Opcode);
249   TmpInst.addOperand(MCOperand::createReg(Reg0));
250   TmpInst.addOperand(MCOperand::createReg(Reg1));
251   TmpInst.addOperand(MCOperand::createReg(Reg2));
252   TmpInst.addOperand(Op3);
253   TmpInst.setLoc(IDLoc);
254   getStreamer().emitInstruction(TmpInst, *STI);
255 }
256 
emitRRI(unsigned Opcode,unsigned Reg0,unsigned Reg1,int16_t Imm,SMLoc IDLoc,const MCSubtargetInfo * STI)257 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1,
258                                  int16_t Imm, SMLoc IDLoc,
259                                  const MCSubtargetInfo *STI) {
260   emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI);
261 }
262 
emitRRIII(unsigned Opcode,unsigned Reg0,unsigned Reg1,int16_t Imm0,int16_t Imm1,int16_t Imm2,SMLoc IDLoc,const MCSubtargetInfo * STI)263 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0,
264                                    unsigned Reg1, int16_t Imm0, int16_t Imm1,
265                                    int16_t Imm2, SMLoc IDLoc,
266                                    const MCSubtargetInfo *STI) {
267   MCInst TmpInst;
268   TmpInst.setOpcode(Opcode);
269   TmpInst.addOperand(MCOperand::createReg(Reg0));
270   TmpInst.addOperand(MCOperand::createReg(Reg1));
271   TmpInst.addOperand(MCOperand::createImm(Imm0));
272   TmpInst.addOperand(MCOperand::createImm(Imm1));
273   TmpInst.addOperand(MCOperand::createImm(Imm2));
274   TmpInst.setLoc(IDLoc);
275   getStreamer().emitInstruction(TmpInst, *STI);
276 }
277 
emitAddu(unsigned DstReg,unsigned SrcReg,unsigned TrgReg,bool Is64Bit,const MCSubtargetInfo * STI)278 void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg,
279                                   unsigned TrgReg, bool Is64Bit,
280                                   const MCSubtargetInfo *STI) {
281   emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(),
282           STI);
283 }
284 
emitDSLL(unsigned DstReg,unsigned SrcReg,int16_t ShiftAmount,SMLoc IDLoc,const MCSubtargetInfo * STI)285 void MipsTargetStreamer::emitDSLL(unsigned DstReg, unsigned SrcReg,
286                                   int16_t ShiftAmount, SMLoc IDLoc,
287                                   const MCSubtargetInfo *STI) {
288   if (ShiftAmount >= 32) {
289     emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI);
290     return;
291   }
292 
293   emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI);
294 }
295 
emitEmptyDelaySlot(bool hasShortDelaySlot,SMLoc IDLoc,const MCSubtargetInfo * STI)296 void MipsTargetStreamer::emitEmptyDelaySlot(bool hasShortDelaySlot, SMLoc IDLoc,
297                                             const MCSubtargetInfo *STI) {
298   if (hasShortDelaySlot)
299     emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
300   else
301     emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
302 }
303 
emitNop(SMLoc IDLoc,const MCSubtargetInfo * STI)304 void MipsTargetStreamer::emitNop(SMLoc IDLoc, const MCSubtargetInfo *STI) {
305   if (isMicroMips(STI))
306     emitRR(Mips::MOVE16_MM, Mips::ZERO, Mips::ZERO, IDLoc, STI);
307   else
308     emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
309 }
310 
311 /// Emit the $gp restore operation for .cprestore.
emitGPRestore(int Offset,SMLoc IDLoc,const MCSubtargetInfo * STI)312 void MipsTargetStreamer::emitGPRestore(int Offset, SMLoc IDLoc,
313                                        const MCSubtargetInfo *STI) {
314   emitLoadWithImmOffset(Mips::LW, GPReg, Mips::SP, Offset, GPReg, IDLoc, STI);
315 }
316 
317 /// Emit a store instruction with an immediate offset.
emitStoreWithImmOffset(unsigned Opcode,unsigned SrcReg,unsigned BaseReg,int64_t Offset,function_ref<unsigned ()> GetATReg,SMLoc IDLoc,const MCSubtargetInfo * STI)318 void MipsTargetStreamer::emitStoreWithImmOffset(
319     unsigned Opcode, unsigned SrcReg, unsigned BaseReg, int64_t Offset,
320     function_ref<unsigned()> GetATReg, SMLoc IDLoc,
321     const MCSubtargetInfo *STI) {
322   if (isInt<16>(Offset)) {
323     emitRRI(Opcode, SrcReg, BaseReg, Offset, IDLoc, STI);
324     return;
325   }
326 
327   // sw $8, offset($8) => lui $at, %hi(offset)
328   //                      add $at, $at, $8
329   //                      sw $8, %lo(offset)($at)
330 
331   unsigned ATReg = GetATReg();
332   if (!ATReg)
333     return;
334 
335   unsigned LoOffset = Offset & 0x0000ffff;
336   unsigned HiOffset = (Offset & 0xffff0000) >> 16;
337 
338   // If msb of LoOffset is 1(negative number) we must increment HiOffset
339   // to account for the sign-extension of the low part.
340   if (LoOffset & 0x8000)
341     HiOffset++;
342 
343   // Generate the base address in ATReg.
344   emitRI(Mips::LUi, ATReg, HiOffset, IDLoc, STI);
345   if (BaseReg != Mips::ZERO)
346     emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI);
347   // Emit the store with the adjusted base and offset.
348   emitRRI(Opcode, SrcReg, ATReg, LoOffset, IDLoc, STI);
349 }
350 
351 /// Emit a load instruction with an immediate offset. DstReg and TmpReg are
352 /// permitted to be the same register iff DstReg is distinct from BaseReg and
353 /// DstReg is a GPR. It is the callers responsibility to identify such cases
354 /// and pass the appropriate register in TmpReg.
emitLoadWithImmOffset(unsigned Opcode,unsigned DstReg,unsigned BaseReg,int64_t Offset,unsigned TmpReg,SMLoc IDLoc,const MCSubtargetInfo * STI)355 void MipsTargetStreamer::emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg,
356                                                unsigned BaseReg, int64_t Offset,
357                                                unsigned TmpReg, SMLoc IDLoc,
358                                                const MCSubtargetInfo *STI) {
359   if (isInt<16>(Offset)) {
360     emitRRI(Opcode, DstReg, BaseReg, Offset, IDLoc, STI);
361     return;
362   }
363 
364   // 1) lw $8, offset($9) => lui $8, %hi(offset)
365   //                         add $8, $8, $9
366   //                         lw $8, %lo(offset)($9)
367   // 2) lw $8, offset($8) => lui $at, %hi(offset)
368   //                         add $at, $at, $8
369   //                         lw $8, %lo(offset)($at)
370 
371   unsigned LoOffset = Offset & 0x0000ffff;
372   unsigned HiOffset = (Offset & 0xffff0000) >> 16;
373 
374   // If msb of LoOffset is 1(negative number) we must increment HiOffset
375   // to account for the sign-extension of the low part.
376   if (LoOffset & 0x8000)
377     HiOffset++;
378 
379   // Generate the base address in TmpReg.
380   emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI);
381   if (BaseReg != Mips::ZERO)
382     emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
383   // Emit the load with the adjusted base and offset.
384   emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI);
385 }
386 
MipsTargetAsmStreamer(MCStreamer & S,formatted_raw_ostream & OS)387 MipsTargetAsmStreamer::MipsTargetAsmStreamer(MCStreamer &S,
388                                              formatted_raw_ostream &OS)
389     : MipsTargetStreamer(S), OS(OS) {}
390 
emitDirectiveSetMicroMips()391 void MipsTargetAsmStreamer::emitDirectiveSetMicroMips() {
392   OS << "\t.set\tmicromips\n";
393   forbidModuleDirective();
394 }
395 
emitDirectiveSetNoMicroMips()396 void MipsTargetAsmStreamer::emitDirectiveSetNoMicroMips() {
397   OS << "\t.set\tnomicromips\n";
398   forbidModuleDirective();
399 }
400 
emitDirectiveSetMips16()401 void MipsTargetAsmStreamer::emitDirectiveSetMips16() {
402   OS << "\t.set\tmips16\n";
403   forbidModuleDirective();
404 }
405 
emitDirectiveSetNoMips16()406 void MipsTargetAsmStreamer::emitDirectiveSetNoMips16() {
407   OS << "\t.set\tnomips16\n";
408   MipsTargetStreamer::emitDirectiveSetNoMips16();
409 }
410 
emitDirectiveSetReorder()411 void MipsTargetAsmStreamer::emitDirectiveSetReorder() {
412   OS << "\t.set\treorder\n";
413   MipsTargetStreamer::emitDirectiveSetReorder();
414 }
415 
emitDirectiveSetNoReorder()416 void MipsTargetAsmStreamer::emitDirectiveSetNoReorder() {
417   OS << "\t.set\tnoreorder\n";
418   forbidModuleDirective();
419 }
420 
emitDirectiveSetMacro()421 void MipsTargetAsmStreamer::emitDirectiveSetMacro() {
422   OS << "\t.set\tmacro\n";
423   MipsTargetStreamer::emitDirectiveSetMacro();
424 }
425 
emitDirectiveSetNoMacro()426 void MipsTargetAsmStreamer::emitDirectiveSetNoMacro() {
427   OS << "\t.set\tnomacro\n";
428   MipsTargetStreamer::emitDirectiveSetNoMacro();
429 }
430 
emitDirectiveSetMsa()431 void MipsTargetAsmStreamer::emitDirectiveSetMsa() {
432   OS << "\t.set\tmsa\n";
433   MipsTargetStreamer::emitDirectiveSetMsa();
434 }
435 
emitDirectiveSetNoMsa()436 void MipsTargetAsmStreamer::emitDirectiveSetNoMsa() {
437   OS << "\t.set\tnomsa\n";
438   MipsTargetStreamer::emitDirectiveSetNoMsa();
439 }
440 
emitDirectiveSetMt()441 void MipsTargetAsmStreamer::emitDirectiveSetMt() {
442   OS << "\t.set\tmt\n";
443   MipsTargetStreamer::emitDirectiveSetMt();
444 }
445 
emitDirectiveSetNoMt()446 void MipsTargetAsmStreamer::emitDirectiveSetNoMt() {
447   OS << "\t.set\tnomt\n";
448   MipsTargetStreamer::emitDirectiveSetNoMt();
449 }
450 
emitDirectiveSetCRC()451 void MipsTargetAsmStreamer::emitDirectiveSetCRC() {
452   OS << "\t.set\tcrc\n";
453   MipsTargetStreamer::emitDirectiveSetCRC();
454 }
455 
emitDirectiveSetNoCRC()456 void MipsTargetAsmStreamer::emitDirectiveSetNoCRC() {
457   OS << "\t.set\tnocrc\n";
458   MipsTargetStreamer::emitDirectiveSetNoCRC();
459 }
460 
emitDirectiveSetVirt()461 void MipsTargetAsmStreamer::emitDirectiveSetVirt() {
462   OS << "\t.set\tvirt\n";
463   MipsTargetStreamer::emitDirectiveSetVirt();
464 }
465 
emitDirectiveSetNoVirt()466 void MipsTargetAsmStreamer::emitDirectiveSetNoVirt() {
467   OS << "\t.set\tnovirt\n";
468   MipsTargetStreamer::emitDirectiveSetNoVirt();
469 }
470 
emitDirectiveSetGINV()471 void MipsTargetAsmStreamer::emitDirectiveSetGINV() {
472   OS << "\t.set\tginv\n";
473   MipsTargetStreamer::emitDirectiveSetGINV();
474 }
475 
emitDirectiveSetNoGINV()476 void MipsTargetAsmStreamer::emitDirectiveSetNoGINV() {
477   OS << "\t.set\tnoginv\n";
478   MipsTargetStreamer::emitDirectiveSetNoGINV();
479 }
480 
emitDirectiveSetAt()481 void MipsTargetAsmStreamer::emitDirectiveSetAt() {
482   OS << "\t.set\tat\n";
483   MipsTargetStreamer::emitDirectiveSetAt();
484 }
485 
emitDirectiveSetAtWithArg(unsigned RegNo)486 void MipsTargetAsmStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
487   OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
488   MipsTargetStreamer::emitDirectiveSetAtWithArg(RegNo);
489 }
490 
emitDirectiveSetNoAt()491 void MipsTargetAsmStreamer::emitDirectiveSetNoAt() {
492   OS << "\t.set\tnoat\n";
493   MipsTargetStreamer::emitDirectiveSetNoAt();
494 }
495 
emitDirectiveEnd(StringRef Name)496 void MipsTargetAsmStreamer::emitDirectiveEnd(StringRef Name) {
497   OS << "\t.end\t" << Name << '\n';
498 }
499 
emitDirectiveEnt(const MCSymbol & Symbol)500 void MipsTargetAsmStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
501   OS << "\t.ent\t" << Symbol.getName() << '\n';
502 }
503 
emitDirectiveAbiCalls()504 void MipsTargetAsmStreamer::emitDirectiveAbiCalls() { OS << "\t.abicalls\n"; }
505 
emitDirectiveNaN2008()506 void MipsTargetAsmStreamer::emitDirectiveNaN2008() { OS << "\t.nan\t2008\n"; }
507 
emitDirectiveNaNLegacy()508 void MipsTargetAsmStreamer::emitDirectiveNaNLegacy() {
509   OS << "\t.nan\tlegacy\n";
510 }
511 
emitDirectiveOptionPic0()512 void MipsTargetAsmStreamer::emitDirectiveOptionPic0() {
513   OS << "\t.option\tpic0\n";
514 }
515 
emitDirectiveOptionPic2()516 void MipsTargetAsmStreamer::emitDirectiveOptionPic2() {
517   OS << "\t.option\tpic2\n";
518 }
519 
emitDirectiveInsn()520 void MipsTargetAsmStreamer::emitDirectiveInsn() {
521   MipsTargetStreamer::emitDirectiveInsn();
522   OS << "\t.insn\n";
523 }
524 
emitFrame(unsigned StackReg,unsigned StackSize,unsigned ReturnReg)525 void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
526                                       unsigned ReturnReg) {
527   OS << "\t.frame\t$"
528      << StringRef(MipsInstPrinter::getRegisterName(StackReg)).lower() << ","
529      << StackSize << ",$"
530      << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
531 }
532 
emitDirectiveSetArch(StringRef Arch)533 void MipsTargetAsmStreamer::emitDirectiveSetArch(StringRef Arch) {
534   OS << "\t.set arch=" << Arch << "\n";
535   MipsTargetStreamer::emitDirectiveSetArch(Arch);
536 }
537 
emitDirectiveSetMips0()538 void MipsTargetAsmStreamer::emitDirectiveSetMips0() {
539   OS << "\t.set\tmips0\n";
540   MipsTargetStreamer::emitDirectiveSetMips0();
541 }
542 
emitDirectiveSetMips1()543 void MipsTargetAsmStreamer::emitDirectiveSetMips1() {
544   OS << "\t.set\tmips1\n";
545   MipsTargetStreamer::emitDirectiveSetMips1();
546 }
547 
emitDirectiveSetMips2()548 void MipsTargetAsmStreamer::emitDirectiveSetMips2() {
549   OS << "\t.set\tmips2\n";
550   MipsTargetStreamer::emitDirectiveSetMips2();
551 }
552 
emitDirectiveSetMips3()553 void MipsTargetAsmStreamer::emitDirectiveSetMips3() {
554   OS << "\t.set\tmips3\n";
555   MipsTargetStreamer::emitDirectiveSetMips3();
556 }
557 
emitDirectiveSetMips4()558 void MipsTargetAsmStreamer::emitDirectiveSetMips4() {
559   OS << "\t.set\tmips4\n";
560   MipsTargetStreamer::emitDirectiveSetMips4();
561 }
562 
emitDirectiveSetMips5()563 void MipsTargetAsmStreamer::emitDirectiveSetMips5() {
564   OS << "\t.set\tmips5\n";
565   MipsTargetStreamer::emitDirectiveSetMips5();
566 }
567 
emitDirectiveSetMips32()568 void MipsTargetAsmStreamer::emitDirectiveSetMips32() {
569   OS << "\t.set\tmips32\n";
570   MipsTargetStreamer::emitDirectiveSetMips32();
571 }
572 
emitDirectiveSetMips32R2()573 void MipsTargetAsmStreamer::emitDirectiveSetMips32R2() {
574   OS << "\t.set\tmips32r2\n";
575   MipsTargetStreamer::emitDirectiveSetMips32R2();
576 }
577 
emitDirectiveSetMips32R3()578 void MipsTargetAsmStreamer::emitDirectiveSetMips32R3() {
579   OS << "\t.set\tmips32r3\n";
580   MipsTargetStreamer::emitDirectiveSetMips32R3();
581 }
582 
emitDirectiveSetMips32R5()583 void MipsTargetAsmStreamer::emitDirectiveSetMips32R5() {
584   OS << "\t.set\tmips32r5\n";
585   MipsTargetStreamer::emitDirectiveSetMips32R5();
586 }
587 
emitDirectiveSetMips32R6()588 void MipsTargetAsmStreamer::emitDirectiveSetMips32R6() {
589   OS << "\t.set\tmips32r6\n";
590   MipsTargetStreamer::emitDirectiveSetMips32R6();
591 }
592 
emitDirectiveSetMips64()593 void MipsTargetAsmStreamer::emitDirectiveSetMips64() {
594   OS << "\t.set\tmips64\n";
595   MipsTargetStreamer::emitDirectiveSetMips64();
596 }
597 
emitDirectiveSetMips64R2()598 void MipsTargetAsmStreamer::emitDirectiveSetMips64R2() {
599   OS << "\t.set\tmips64r2\n";
600   MipsTargetStreamer::emitDirectiveSetMips64R2();
601 }
602 
emitDirectiveSetMips64R3()603 void MipsTargetAsmStreamer::emitDirectiveSetMips64R3() {
604   OS << "\t.set\tmips64r3\n";
605   MipsTargetStreamer::emitDirectiveSetMips64R3();
606 }
607 
emitDirectiveSetMips64R5()608 void MipsTargetAsmStreamer::emitDirectiveSetMips64R5() {
609   OS << "\t.set\tmips64r5\n";
610   MipsTargetStreamer::emitDirectiveSetMips64R5();
611 }
612 
emitDirectiveSetMips64R6()613 void MipsTargetAsmStreamer::emitDirectiveSetMips64R6() {
614   OS << "\t.set\tmips64r6\n";
615   MipsTargetStreamer::emitDirectiveSetMips64R6();
616 }
617 
emitDirectiveSetDsp()618 void MipsTargetAsmStreamer::emitDirectiveSetDsp() {
619   OS << "\t.set\tdsp\n";
620   MipsTargetStreamer::emitDirectiveSetDsp();
621 }
622 
emitDirectiveSetDspr2()623 void MipsTargetAsmStreamer::emitDirectiveSetDspr2() {
624   OS << "\t.set\tdspr2\n";
625   MipsTargetStreamer::emitDirectiveSetDspr2();
626 }
627 
emitDirectiveSetNoDsp()628 void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() {
629   OS << "\t.set\tnodsp\n";
630   MipsTargetStreamer::emitDirectiveSetNoDsp();
631 }
632 
emitDirectiveSetMips3D()633 void MipsTargetAsmStreamer::emitDirectiveSetMips3D() {
634   OS << "\t.set\tmips3d\n";
635   MipsTargetStreamer::emitDirectiveSetMips3D();
636 }
637 
emitDirectiveSetNoMips3D()638 void MipsTargetAsmStreamer::emitDirectiveSetNoMips3D() {
639   OS << "\t.set\tnomips3d\n";
640   MipsTargetStreamer::emitDirectiveSetNoMips3D();
641 }
642 
emitDirectiveSetPop()643 void MipsTargetAsmStreamer::emitDirectiveSetPop() {
644   OS << "\t.set\tpop\n";
645   MipsTargetStreamer::emitDirectiveSetPop();
646 }
647 
emitDirectiveSetPush()648 void MipsTargetAsmStreamer::emitDirectiveSetPush() {
649  OS << "\t.set\tpush\n";
650  MipsTargetStreamer::emitDirectiveSetPush();
651 }
652 
emitDirectiveSetSoftFloat()653 void MipsTargetAsmStreamer::emitDirectiveSetSoftFloat() {
654   OS << "\t.set\tsoftfloat\n";
655   MipsTargetStreamer::emitDirectiveSetSoftFloat();
656 }
657 
emitDirectiveSetHardFloat()658 void MipsTargetAsmStreamer::emitDirectiveSetHardFloat() {
659   OS << "\t.set\thardfloat\n";
660   MipsTargetStreamer::emitDirectiveSetHardFloat();
661 }
662 
663 // Print a 32 bit hex number with all numbers.
printHex32(unsigned Value,raw_ostream & OS)664 static void printHex32(unsigned Value, raw_ostream &OS) {
665   OS << "0x";
666   for (int i = 7; i >= 0; i--)
667     OS.write_hex((Value & (0xF << (i * 4))) >> (i * 4));
668 }
669 
emitMask(unsigned CPUBitmask,int CPUTopSavedRegOff)670 void MipsTargetAsmStreamer::emitMask(unsigned CPUBitmask,
671                                      int CPUTopSavedRegOff) {
672   OS << "\t.mask \t";
673   printHex32(CPUBitmask, OS);
674   OS << ',' << CPUTopSavedRegOff << '\n';
675 }
676 
emitFMask(unsigned FPUBitmask,int FPUTopSavedRegOff)677 void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask,
678                                       int FPUTopSavedRegOff) {
679   OS << "\t.fmask\t";
680   printHex32(FPUBitmask, OS);
681   OS << "," << FPUTopSavedRegOff << '\n';
682 }
683 
emitDirectiveCpAdd(unsigned RegNo)684 void MipsTargetAsmStreamer::emitDirectiveCpAdd(unsigned RegNo) {
685   OS << "\t.cpadd\t$"
686      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
687   forbidModuleDirective();
688 }
689 
emitDirectiveCpLoad(unsigned RegNo)690 void MipsTargetAsmStreamer::emitDirectiveCpLoad(unsigned RegNo) {
691   OS << "\t.cpload\t$"
692      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
693   forbidModuleDirective();
694 }
695 
emitDirectiveCpLocal(unsigned RegNo)696 void MipsTargetAsmStreamer::emitDirectiveCpLocal(unsigned RegNo) {
697   OS << "\t.cplocal\t$"
698      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
699   MipsTargetStreamer::emitDirectiveCpLocal(RegNo);
700 }
701 
emitDirectiveCpRestore(int Offset,function_ref<unsigned ()> GetATReg,SMLoc IDLoc,const MCSubtargetInfo * STI)702 bool MipsTargetAsmStreamer::emitDirectiveCpRestore(
703     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
704     const MCSubtargetInfo *STI) {
705   MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
706   OS << "\t.cprestore\t" << Offset << "\n";
707   return true;
708 }
709 
emitDirectiveCpsetup(unsigned RegNo,int RegOrOffset,const MCSymbol & Sym,bool IsReg)710 void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo,
711                                                  int RegOrOffset,
712                                                  const MCSymbol &Sym,
713                                                  bool IsReg) {
714   OS << "\t.cpsetup\t$"
715      << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", ";
716 
717   if (IsReg)
718     OS << "$"
719        << StringRef(MipsInstPrinter::getRegisterName(RegOrOffset)).lower();
720   else
721     OS << RegOrOffset;
722 
723   OS << ", ";
724 
725   OS << Sym.getName();
726   forbidModuleDirective();
727 }
728 
emitDirectiveCpreturn(unsigned SaveLocation,bool SaveLocationIsRegister)729 void MipsTargetAsmStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
730                                                   bool SaveLocationIsRegister) {
731   OS << "\t.cpreturn";
732   forbidModuleDirective();
733 }
734 
emitDirectiveModuleFP()735 void MipsTargetAsmStreamer::emitDirectiveModuleFP() {
736   MipsABIFlagsSection::FpABIKind FpABI = ABIFlagsSection.getFpABI();
737   if (FpABI == MipsABIFlagsSection::FpABIKind::SOFT)
738     OS << "\t.module\tsoftfloat\n";
739   else
740     OS << "\t.module\tfp=" << ABIFlagsSection.getFpABIString(FpABI) << "\n";
741 }
742 
emitDirectiveSetFp(MipsABIFlagsSection::FpABIKind Value)743 void MipsTargetAsmStreamer::emitDirectiveSetFp(
744     MipsABIFlagsSection::FpABIKind Value) {
745   MipsTargetStreamer::emitDirectiveSetFp(Value);
746 
747   OS << "\t.set\tfp=";
748   OS << ABIFlagsSection.getFpABIString(Value) << "\n";
749 }
750 
emitDirectiveModuleOddSPReg()751 void MipsTargetAsmStreamer::emitDirectiveModuleOddSPReg() {
752   MipsTargetStreamer::emitDirectiveModuleOddSPReg();
753 
754   OS << "\t.module\t" << (ABIFlagsSection.OddSPReg ? "" : "no") << "oddspreg\n";
755 }
756 
emitDirectiveSetOddSPReg()757 void MipsTargetAsmStreamer::emitDirectiveSetOddSPReg() {
758   MipsTargetStreamer::emitDirectiveSetOddSPReg();
759   OS << "\t.set\toddspreg\n";
760 }
761 
emitDirectiveSetNoOddSPReg()762 void MipsTargetAsmStreamer::emitDirectiveSetNoOddSPReg() {
763   MipsTargetStreamer::emitDirectiveSetNoOddSPReg();
764   OS << "\t.set\tnooddspreg\n";
765 }
766 
emitDirectiveModuleSoftFloat()767 void MipsTargetAsmStreamer::emitDirectiveModuleSoftFloat() {
768   OS << "\t.module\tsoftfloat\n";
769 }
770 
emitDirectiveModuleHardFloat()771 void MipsTargetAsmStreamer::emitDirectiveModuleHardFloat() {
772   OS << "\t.module\thardfloat\n";
773 }
774 
emitDirectiveModuleMT()775 void MipsTargetAsmStreamer::emitDirectiveModuleMT() {
776   OS << "\t.module\tmt\n";
777 }
778 
emitDirectiveModuleCRC()779 void MipsTargetAsmStreamer::emitDirectiveModuleCRC() {
780   OS << "\t.module\tcrc\n";
781 }
782 
emitDirectiveModuleNoCRC()783 void MipsTargetAsmStreamer::emitDirectiveModuleNoCRC() {
784   OS << "\t.module\tnocrc\n";
785 }
786 
emitDirectiveModuleVirt()787 void MipsTargetAsmStreamer::emitDirectiveModuleVirt() {
788   OS << "\t.module\tvirt\n";
789 }
790 
emitDirectiveModuleNoVirt()791 void MipsTargetAsmStreamer::emitDirectiveModuleNoVirt() {
792   OS << "\t.module\tnovirt\n";
793 }
794 
emitDirectiveModuleGINV()795 void MipsTargetAsmStreamer::emitDirectiveModuleGINV() {
796   OS << "\t.module\tginv\n";
797 }
798 
emitDirectiveModuleNoGINV()799 void MipsTargetAsmStreamer::emitDirectiveModuleNoGINV() {
800   OS << "\t.module\tnoginv\n";
801 }
802 
803 // This part is for ELF object output.
MipsTargetELFStreamer(MCStreamer & S,const MCSubtargetInfo & STI)804 MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
805                                              const MCSubtargetInfo &STI)
806     : MipsTargetStreamer(S),
807       MicroMipsEnabled(false), STI(STI) {
808   MCAssembler &MCA = getStreamer().getAssembler();
809 
810   // It's possible that MCObjectFileInfo isn't fully initialized at this point
811   // due to an initialization order problem where LLVMTargetMachine creates the
812   // target streamer before TargetLoweringObjectFile calls
813   // InitializeMCObjectFileInfo. There doesn't seem to be a single place that
814   // covers all cases so this statement covers most cases and direct object
815   // emission must call setPic() once MCObjectFileInfo has been initialized. The
816   // cases we don't handle here are covered by MipsAsmPrinter.
817   Pic = MCA.getContext().getObjectFileInfo()->isPositionIndependent();
818 
819   const FeatureBitset &Features = STI.getFeatureBits();
820 
821   // Set the header flags that we can in the constructor.
822   // FIXME: This is a fairly terrible hack. We set the rest
823   // of these in the destructor. The problem here is two-fold:
824   //
825   // a: Some of the eflags can be set/reset by directives.
826   // b: There aren't any usage paths that initialize the ABI
827   //    pointer until after we initialize either an assembler
828   //    or the target machine.
829   // We can fix this by making the target streamer construct
830   // the ABI, but this is fraught with wide ranging dependency
831   // issues as well.
832   unsigned EFlags = MCA.getELFHeaderEFlags();
833 
834   // FIXME: Fix a dependency issue by instantiating the ABI object to some
835   // default based off the triple. The triple doesn't describe the target
836   // fully, but any external user of the API that uses the MCTargetStreamer
837   // would otherwise crash on assertion failure.
838 
839   ABI = MipsABIInfo(
840       STI.getTargetTriple().getArch() == Triple::ArchType::mipsel ||
841               STI.getTargetTriple().getArch() == Triple::ArchType::mips
842           ? MipsABIInfo::O32()
843           : MipsABIInfo::N64());
844 
845   // Architecture
846   if (Features[Mips::FeatureMips64r6])
847     EFlags |= ELF::EF_MIPS_ARCH_64R6;
848   else if (Features[Mips::FeatureMips64r2] ||
849            Features[Mips::FeatureMips64r3] ||
850            Features[Mips::FeatureMips64r5])
851     EFlags |= ELF::EF_MIPS_ARCH_64R2;
852   else if (Features[Mips::FeatureMips64])
853     EFlags |= ELF::EF_MIPS_ARCH_64;
854   else if (Features[Mips::FeatureMips5])
855     EFlags |= ELF::EF_MIPS_ARCH_5;
856   else if (Features[Mips::FeatureMips4])
857     EFlags |= ELF::EF_MIPS_ARCH_4;
858   else if (Features[Mips::FeatureMips3])
859     EFlags |= ELF::EF_MIPS_ARCH_3;
860   else if (Features[Mips::FeatureMips32r6])
861     EFlags |= ELF::EF_MIPS_ARCH_32R6;
862   else if (Features[Mips::FeatureMips32r2] ||
863            Features[Mips::FeatureMips32r3] ||
864            Features[Mips::FeatureMips32r5])
865     EFlags |= ELF::EF_MIPS_ARCH_32R2;
866   else if (Features[Mips::FeatureMips32])
867     EFlags |= ELF::EF_MIPS_ARCH_32;
868   else if (Features[Mips::FeatureMips2])
869     EFlags |= ELF::EF_MIPS_ARCH_2;
870   else
871     EFlags |= ELF::EF_MIPS_ARCH_1;
872 
873   // Machine
874   if (Features[Mips::FeatureCnMips])
875     EFlags |= ELF::EF_MIPS_MACH_OCTEON;
876   else if (Features[Mips::FeatureMipsCheri128])
877     EFlags |= ELF::EF_MIPS_MACH_CHERI128;
878   else if (Features[Mips::FeatureMipsCheri])
879     EFlags |= ELF::EF_MIPS_MACH_CHERI256;
880   else if (Features[Mips::FeatureMipsBeri])
881     EFlags |= ELF::EF_MIPS_MACH_BERI;
882 
883   // Other options.
884   if (Features[Mips::FeatureNaN2008])
885     EFlags |= ELF::EF_MIPS_NAN2008;
886 
887   MCA.setELFHeaderEFlags(EFlags);
888 }
889 
emitLabel(MCSymbol * S)890 void MipsTargetELFStreamer::emitLabel(MCSymbol *S) {
891   auto *Symbol = cast<MCSymbolELF>(S);
892   getStreamer().getAssembler().registerSymbol(*Symbol);
893   uint8_t Type = Symbol->getType();
894   if (Type != ELF::STT_FUNC)
895     return;
896 
897   if (isMicroMipsEnabled())
898     Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
899 }
900 
finish()901 void MipsTargetELFStreamer::finish() {
902   MCAssembler &MCA = getStreamer().getAssembler();
903   const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo();
904 
905   // .bss, .text and .data are always at least 16-byte aligned.
906   MCSection &TextSection = *OFI.getTextSection();
907   MCA.registerSection(TextSection);
908   MCSection &DataSection = *OFI.getDataSection();
909   MCA.registerSection(DataSection);
910   MCSection &BSSSection = *OFI.getBSSSection();
911   MCA.registerSection(BSSSection);
912 
913   TextSection.setAlignment(Align(std::max(16u, TextSection.getAlignment())));
914   DataSection.setAlignment(Align(std::max(16u, DataSection.getAlignment())));
915   BSSSection.setAlignment(Align(std::max(16u, BSSSection.getAlignment())));
916 
917   if (RoundSectionSizes) {
918     // Make sections sizes a multiple of the alignment. This is useful for
919     // verifying the output of IAS against the output of other assemblers but
920     // it's not necessary to produce a correct object and increases section
921     // size.
922     MCStreamer &OS = getStreamer();
923     for (MCSection &S : MCA) {
924       MCSectionELF &Section = static_cast<MCSectionELF &>(S);
925 
926       unsigned Alignment = Section.getAlignment();
927       if (Alignment) {
928         OS.SwitchSection(&Section);
929         if (Section.UseCodeAlign())
930           OS.emitCodeAlignment(Alignment, Alignment);
931         else
932           OS.emitValueToAlignment(Alignment, 0, 1, Alignment);
933       }
934     }
935   }
936 
937   const FeatureBitset &Features = STI.getFeatureBits();
938 
939   // Update e_header flags. See the FIXME and comment above in
940   // the constructor for a full rundown on this.
941   unsigned EFlags = MCA.getELFHeaderEFlags();
942 
943   // ABI
944   // N64 does not require any ABI bits.
945   if (getABI().IsO32())
946     EFlags |= ELF::EF_MIPS_ABI_O32;
947   else if (getABI().IsN32())
948     EFlags |= ELF::EF_MIPS_ABI2;
949 
950   if (Features[Mips::FeatureGP64Bit]) {
951     if (getABI().IsO32())
952       EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
953   } else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
954     EFlags |= ELF::EF_MIPS_32BITMODE;
955 
956   // -mplt is not implemented but we should act as if it was
957   // given.
958   if (!Features[Mips::FeatureNoABICalls])
959     EFlags |= ELF::EF_MIPS_CPIC;
960 
961   if (Pic)
962     EFlags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
963 
964   if (getABI().IsCheriPureCap())
965     EFlags |= ELF::EF_MIPS_ABI_CHERIABI;
966 
967   MCA.setELFHeaderEFlags(EFlags);
968 
969   // Emit all the option records.
970   // At the moment we are only emitting .Mips.options (ODK_REGINFO) and
971   // .reginfo.
972   MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
973   MEF.EmitMipsOptionRecords();
974 
975   emitMipsAbiFlags();
976 }
977 
emitAssignment(MCSymbol * S,const MCExpr * Value)978 void MipsTargetELFStreamer::emitAssignment(MCSymbol *S, const MCExpr *Value) {
979   auto *Symbol = cast<MCSymbolELF>(S);
980   // If on rhs is micromips symbol then mark Symbol as microMips.
981   if (Value->getKind() != MCExpr::SymbolRef)
982     return;
983   const auto &RhsSym = cast<MCSymbolELF>(
984       static_cast<const MCSymbolRefExpr *>(Value)->getSymbol());
985 
986   if (!(RhsSym.getOther() & ELF::STO_MIPS_MICROMIPS))
987     return;
988 
989   Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
990 }
991 
getStreamer()992 MCELFStreamer &MipsTargetELFStreamer::getStreamer() {
993   return static_cast<MCELFStreamer &>(Streamer);
994 }
995 
emitDirectiveSetMicroMips()996 void MipsTargetELFStreamer::emitDirectiveSetMicroMips() {
997   MicroMipsEnabled = true;
998   forbidModuleDirective();
999 }
1000 
emitDirectiveSetNoMicroMips()1001 void MipsTargetELFStreamer::emitDirectiveSetNoMicroMips() {
1002   MicroMipsEnabled = false;
1003   forbidModuleDirective();
1004 }
1005 
setUsesMicroMips()1006 void MipsTargetELFStreamer::setUsesMicroMips() {
1007   MCAssembler &MCA = getStreamer().getAssembler();
1008   unsigned Flags = MCA.getELFHeaderEFlags();
1009   Flags |= ELF::EF_MIPS_MICROMIPS;
1010   MCA.setELFHeaderEFlags(Flags);
1011 }
1012 
emitDirectiveSetMips16()1013 void MipsTargetELFStreamer::emitDirectiveSetMips16() {
1014   MCAssembler &MCA = getStreamer().getAssembler();
1015   unsigned Flags = MCA.getELFHeaderEFlags();
1016   Flags |= ELF::EF_MIPS_ARCH_ASE_M16;
1017   MCA.setELFHeaderEFlags(Flags);
1018   forbidModuleDirective();
1019 }
1020 
emitDirectiveSetNoReorder()1021 void MipsTargetELFStreamer::emitDirectiveSetNoReorder() {
1022   MCAssembler &MCA = getStreamer().getAssembler();
1023   unsigned Flags = MCA.getELFHeaderEFlags();
1024   Flags |= ELF::EF_MIPS_NOREORDER;
1025   MCA.setELFHeaderEFlags(Flags);
1026   forbidModuleDirective();
1027 }
1028 
emitDirectiveEnd(StringRef Name)1029 void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) {
1030   MCAssembler &MCA = getStreamer().getAssembler();
1031   MCContext &Context = MCA.getContext();
1032   MCStreamer &OS = getStreamer();
1033 
1034   MCSectionELF *Sec = Context.getELFSection(".pdr", ELF::SHT_PROGBITS, 0);
1035 
1036   MCSymbol *Sym = Context.getOrCreateSymbol(Name);
1037   const MCSymbolRefExpr *ExprRef =
1038       MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Context);
1039 
1040   MCA.registerSection(*Sec);
1041   Sec->setAlignment(Align(4));
1042 
1043   OS.PushSection();
1044 
1045   OS.SwitchSection(Sec);
1046 
1047   OS.emitValueImpl(ExprRef, 4);
1048 
1049   OS.emitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask
1050   OS.emitIntValue(GPRInfoSet ? GPROffset : 0, 4);  // reg_offset
1051 
1052   OS.emitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask
1053   OS.emitIntValue(FPRInfoSet ? FPROffset : 0, 4);  // fpreg_offset
1054 
1055   OS.emitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset
1056   OS.emitIntValue(FrameInfoSet ? FrameReg : 0, 4);    // frame_reg
1057   OS.emitIntValue(FrameInfoSet ? ReturnReg : 0, 4);   // return_reg
1058 
1059   // The .end directive marks the end of a procedure. Invalidate
1060   // the information gathered up until this point.
1061   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1062 
1063   OS.PopSection();
1064 
1065   // .end also implicitly sets the size.
1066   MCSymbol *CurPCSym = Context.createTempSymbol();
1067   OS.emitLabel(CurPCSym);
1068   const MCExpr *Size = MCBinaryExpr::createSub(
1069       MCSymbolRefExpr::create(CurPCSym, MCSymbolRefExpr::VK_None, Context),
1070       ExprRef, Context);
1071 
1072   // The ELFObjectWriter can determine the absolute size as it has access to
1073   // the layout information of the assembly file, so a size expression rather
1074   // than an absolute value is ok here.
1075   static_cast<MCSymbolELF *>(Sym)->setSize(Size);
1076 }
1077 
emitDirectiveEnt(const MCSymbol & Symbol)1078 void MipsTargetELFStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
1079   GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
1080 
1081   // .ent also acts like an implicit '.type symbol, STT_FUNC'
1082   static_cast<const MCSymbolELF &>(Symbol).setType(ELF::STT_FUNC);
1083 }
1084 
emitDirectiveAbiCalls()1085 void MipsTargetELFStreamer::emitDirectiveAbiCalls() {
1086   MCAssembler &MCA = getStreamer().getAssembler();
1087   unsigned Flags = MCA.getELFHeaderEFlags();
1088   Flags |= ELF::EF_MIPS_CPIC | ELF::EF_MIPS_PIC;
1089   MCA.setELFHeaderEFlags(Flags);
1090 }
1091 
emitDirectiveNaN2008()1092 void MipsTargetELFStreamer::emitDirectiveNaN2008() {
1093   MCAssembler &MCA = getStreamer().getAssembler();
1094   unsigned Flags = MCA.getELFHeaderEFlags();
1095   Flags |= ELF::EF_MIPS_NAN2008;
1096   MCA.setELFHeaderEFlags(Flags);
1097 }
1098 
emitDirectiveNaNLegacy()1099 void MipsTargetELFStreamer::emitDirectiveNaNLegacy() {
1100   MCAssembler &MCA = getStreamer().getAssembler();
1101   unsigned Flags = MCA.getELFHeaderEFlags();
1102   Flags &= ~ELF::EF_MIPS_NAN2008;
1103   MCA.setELFHeaderEFlags(Flags);
1104 }
1105 
emitDirectiveOptionPic0()1106 void MipsTargetELFStreamer::emitDirectiveOptionPic0() {
1107   MCAssembler &MCA = getStreamer().getAssembler();
1108   unsigned Flags = MCA.getELFHeaderEFlags();
1109   // This option overrides other PIC options like -KPIC.
1110   Pic = false;
1111   Flags &= ~ELF::EF_MIPS_PIC;
1112   MCA.setELFHeaderEFlags(Flags);
1113 }
1114 
emitDirectiveOptionPic2()1115 void MipsTargetELFStreamer::emitDirectiveOptionPic2() {
1116   MCAssembler &MCA = getStreamer().getAssembler();
1117   unsigned Flags = MCA.getELFHeaderEFlags();
1118   Pic = true;
1119   // NOTE: We are following the GAS behaviour here which means the directive
1120   // 'pic2' also sets the CPIC bit in the ELF header. This is different from
1121   // what is stated in the SYSV ABI which consider the bits EF_MIPS_PIC and
1122   // EF_MIPS_CPIC to be mutually exclusive.
1123   Flags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
1124   MCA.setELFHeaderEFlags(Flags);
1125 }
1126 
emitDirectiveInsn()1127 void MipsTargetELFStreamer::emitDirectiveInsn() {
1128   MipsTargetStreamer::emitDirectiveInsn();
1129   MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
1130   MEF.createPendingLabelRelocs();
1131 }
1132 
emitFrame(unsigned StackReg,unsigned StackSize,unsigned ReturnReg_)1133 void MipsTargetELFStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
1134                                       unsigned ReturnReg_) {
1135   MCContext &Context = getStreamer().getAssembler().getContext();
1136   const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
1137 
1138   FrameInfoSet = true;
1139   FrameReg = RegInfo->getEncodingValue(StackReg);
1140   FrameOffset = StackSize;
1141   ReturnReg = RegInfo->getEncodingValue(ReturnReg_);
1142 }
1143 
emitMask(unsigned CPUBitmask,int CPUTopSavedRegOff)1144 void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask,
1145                                      int CPUTopSavedRegOff) {
1146   GPRInfoSet = true;
1147   GPRBitMask = CPUBitmask;
1148   GPROffset = CPUTopSavedRegOff;
1149 }
1150 
emitFMask(unsigned FPUBitmask,int FPUTopSavedRegOff)1151 void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask,
1152                                       int FPUTopSavedRegOff) {
1153   FPRInfoSet = true;
1154   FPRBitMask = FPUBitmask;
1155   FPROffset = FPUTopSavedRegOff;
1156 }
1157 
emitDirectiveCpAdd(unsigned RegNo)1158 void MipsTargetELFStreamer::emitDirectiveCpAdd(unsigned RegNo) {
1159   // .cpadd $reg
1160   // This directive inserts code to add $gp to the argument's register
1161   // when support for position independent code is enabled.
1162   if (!Pic)
1163     return;
1164 
1165   emitAddu(RegNo, RegNo, GPReg, getABI().IsN64(), &STI);
1166   forbidModuleDirective();
1167 }
1168 
emitDirectiveCpLoad(unsigned RegNo)1169 void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) {
1170   // .cpload $reg
1171   // This directive expands to:
1172   // lui   $gp, %hi(_gp_disp)
1173   // addui $gp, $gp, %lo(_gp_disp)
1174   // addu  $gp, $gp, $reg
1175   // when support for position independent code is enabled.
1176   if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1177     return;
1178 
1179   // There's a GNU extension controlled by -mno-shared that allows
1180   // locally-binding symbols to be accessed using absolute addresses.
1181   // This is currently not supported. When supported -mno-shared makes
1182   // .cpload expand to:
1183   //   lui     $gp, %hi(__gnu_local_gp)
1184   //   addiu   $gp, $gp, %lo(__gnu_local_gp)
1185 
1186   StringRef SymName("_gp_disp");
1187   MCAssembler &MCA = getStreamer().getAssembler();
1188   MCSymbol *GP_Disp = MCA.getContext().getOrCreateSymbol(SymName);
1189   MCA.registerSymbol(*GP_Disp);
1190 
1191   MCInst TmpInst;
1192   TmpInst.setOpcode(Mips::LUi);
1193   TmpInst.addOperand(MCOperand::createReg(GPReg));
1194   const MCExpr *HiSym = MipsMCExpr::create(
1195       MipsMCExpr::MEK_HI,
1196       MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
1197                               MCA.getContext()),
1198       MCA.getContext());
1199   TmpInst.addOperand(MCOperand::createExpr(HiSym));
1200   getStreamer().emitInstruction(TmpInst, STI);
1201 
1202   TmpInst.clear();
1203 
1204   TmpInst.setOpcode(Mips::ADDiu);
1205   TmpInst.addOperand(MCOperand::createReg(GPReg));
1206   TmpInst.addOperand(MCOperand::createReg(GPReg));
1207   const MCExpr *LoSym = MipsMCExpr::create(
1208       MipsMCExpr::MEK_LO,
1209       MCSymbolRefExpr::create("_gp_disp", MCSymbolRefExpr::VK_None,
1210                               MCA.getContext()),
1211       MCA.getContext());
1212   TmpInst.addOperand(MCOperand::createExpr(LoSym));
1213   getStreamer().emitInstruction(TmpInst, STI);
1214 
1215   TmpInst.clear();
1216 
1217   TmpInst.setOpcode(Mips::ADDu);
1218   TmpInst.addOperand(MCOperand::createReg(GPReg));
1219   TmpInst.addOperand(MCOperand::createReg(GPReg));
1220   TmpInst.addOperand(MCOperand::createReg(RegNo));
1221   getStreamer().emitInstruction(TmpInst, STI);
1222 
1223   forbidModuleDirective();
1224 }
1225 
emitDirectiveCpLocal(unsigned RegNo)1226 void MipsTargetELFStreamer::emitDirectiveCpLocal(unsigned RegNo) {
1227   if (Pic)
1228     MipsTargetStreamer::emitDirectiveCpLocal(RegNo);
1229 }
1230 
emitDirectiveCpRestore(int Offset,function_ref<unsigned ()> GetATReg,SMLoc IDLoc,const MCSubtargetInfo * STI)1231 bool MipsTargetELFStreamer::emitDirectiveCpRestore(
1232     int Offset, function_ref<unsigned()> GetATReg, SMLoc IDLoc,
1233     const MCSubtargetInfo *STI) {
1234   MipsTargetStreamer::emitDirectiveCpRestore(Offset, GetATReg, IDLoc, STI);
1235   // .cprestore offset
1236   // When PIC mode is enabled and the O32 ABI is used, this directive expands
1237   // to:
1238   //    sw $gp, offset($sp)
1239   // and adds a corresponding LW after every JAL.
1240 
1241   // Note that .cprestore is ignored if used with the N32 and N64 ABIs or if it
1242   // is used in non-PIC mode.
1243   if (!Pic || (getABI().IsN32() || getABI().IsN64()))
1244     return true;
1245 
1246   // Store the $gp on the stack.
1247   emitStoreWithImmOffset(Mips::SW, GPReg, Mips::SP, Offset, GetATReg, IDLoc,
1248                          STI);
1249   return true;
1250 }
1251 
emitDirectiveCpsetup(unsigned RegNo,int RegOrOffset,const MCSymbol & Sym,bool IsReg)1252 void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo,
1253                                                  int RegOrOffset,
1254                                                  const MCSymbol &Sym,
1255                                                  bool IsReg) {
1256   // Only N32 and N64 emit anything for .cpsetup iff PIC is set.
1257   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1258     return;
1259 
1260   forbidModuleDirective();
1261 
1262   MCAssembler &MCA = getStreamer().getAssembler();
1263   MCInst Inst;
1264 
1265   // Either store the old $gp in a register or on the stack
1266   if (IsReg) {
1267     // move $save, $gpreg
1268     emitRRR(Mips::OR64, RegOrOffset, GPReg, Mips::ZERO, SMLoc(), &STI);
1269   } else {
1270     // sd $gpreg, offset($sp)
1271     emitRRI(Mips::SD, GPReg, Mips::SP, RegOrOffset, SMLoc(), &STI);
1272   }
1273 
1274   if (getABI().IsN32()) {
1275     MCSymbol *GPSym = MCA.getContext().getOrCreateSymbol("__gnu_local_gp");
1276     const MipsMCExpr *HiExpr = MipsMCExpr::create(
1277         MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
1278         MCA.getContext());
1279     const MipsMCExpr *LoExpr = MipsMCExpr::create(
1280         MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(GPSym, MCA.getContext()),
1281         MCA.getContext());
1282 
1283     // lui $gp, %hi(__gnu_local_gp)
1284     emitRX(Mips::LUi, GPReg, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1285 
1286     // addiu  $gp, $gp, %lo(__gnu_local_gp)
1287     emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(),
1288             &STI);
1289 
1290     return;
1291   }
1292 
1293   const MipsMCExpr *HiExpr = MipsMCExpr::createGpOff(
1294       MipsMCExpr::MEK_HI, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
1295       MCA.getContext());
1296   const MipsMCExpr *LoExpr = MipsMCExpr::createGpOff(
1297       MipsMCExpr::MEK_LO, MCSymbolRefExpr::create(&Sym, MCA.getContext()),
1298       MCA.getContext());
1299 
1300   // lui $gp, %hi(%neg(%gp_rel(funcSym)))
1301   emitRX(Mips::LUi, GPReg, MCOperand::createExpr(HiExpr), SMLoc(), &STI);
1302 
1303   // addiu  $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
1304   emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(),
1305           &STI);
1306 
1307   // daddu  $gp, $gp, $funcreg
1308   emitRRR(Mips::DADDu, GPReg, GPReg, RegNo, SMLoc(), &STI);
1309 }
1310 
emitDirectiveCpreturn(unsigned SaveLocation,bool SaveLocationIsRegister)1311 void MipsTargetELFStreamer::emitDirectiveCpreturn(unsigned SaveLocation,
1312                                                   bool SaveLocationIsRegister) {
1313   // Only N32 and N64 emit anything for .cpreturn iff PIC is set.
1314   if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
1315     return;
1316 
1317   MCInst Inst;
1318   // Either restore the old $gp from a register or on the stack
1319   if (SaveLocationIsRegister) {
1320     Inst.setOpcode(Mips::OR);
1321     Inst.addOperand(MCOperand::createReg(GPReg));
1322     Inst.addOperand(MCOperand::createReg(SaveLocation));
1323     Inst.addOperand(MCOperand::createReg(Mips::ZERO));
1324   } else {
1325     Inst.setOpcode(Mips::LD);
1326     Inst.addOperand(MCOperand::createReg(GPReg));
1327     Inst.addOperand(MCOperand::createReg(Mips::SP));
1328     Inst.addOperand(MCOperand::createImm(SaveLocation));
1329   }
1330   getStreamer().emitInstruction(Inst, STI);
1331 
1332   forbidModuleDirective();
1333 }
1334 
emitMipsAbiFlags()1335 void MipsTargetELFStreamer::emitMipsAbiFlags() {
1336   MCAssembler &MCA = getStreamer().getAssembler();
1337   MCContext &Context = MCA.getContext();
1338   MCStreamer &OS = getStreamer();
1339   MCSectionELF *Sec = Context.getELFSection(
1340       ".MIPS.abiflags", ELF::SHT_MIPS_ABIFLAGS, ELF::SHF_ALLOC, 24, "");
1341   MCA.registerSection(*Sec);
1342   Sec->setAlignment(Align(8));
1343   OS.SwitchSection(Sec);
1344 
1345   OS << ABIFlagsSection;
1346 }
1347