1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
3# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
4# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
5
6# Note: 16-bit instructions generally produce a 0 result in the high 16-bits on GFX8 and GFX9 and preserve high 16 bits on GFX10+
7
8---
9name:            add_s16
10legalized:       true
11regBankSelected: true
12tracksRegLiveness: true
13
14body: |
15  bb.0:
16    liveins: $vgpr0, $vgpr1
17
18    ; GFX6-LABEL: name: add_s16
19    ; GFX6: liveins: $vgpr0, $vgpr1
20    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
21    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
22    ; GFX6: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
23    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
24    ; GFX10-LABEL: name: add_s16
25    ; GFX10: liveins: $vgpr0, $vgpr1
26    ; GFX10: $vcc_hi = IMPLICIT_DEF
27    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
28    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
29    ; GFX10: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
30    ; GFX10: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
31    %0:vgpr(s32) = COPY $vgpr0
32    %1:vgpr(s32) = COPY $vgpr1
33    %2:vgpr(s16) = G_TRUNC %0
34    %3:vgpr(s16) = G_TRUNC %1
35    %4:vgpr(s16) = G_ADD %2, %3
36    S_ENDPGM 0, implicit %4
37
38...
39
40---
41name:            add_s16_zext_to_s32
42legalized:       true
43regBankSelected: true
44tracksRegLiveness: true
45
46body: |
47  bb.0:
48    liveins: $vgpr0, $vgpr1
49
50    ; GFX6-LABEL: name: add_s16_zext_to_s32
51    ; GFX6: liveins: $vgpr0, $vgpr1
52    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
53    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
54    ; GFX6: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
55    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
56    ; GFX10-LABEL: name: add_s16_zext_to_s32
57    ; GFX10: liveins: $vgpr0, $vgpr1
58    ; GFX10: $vcc_hi = IMPLICIT_DEF
59    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
60    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
61    ; GFX10: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
62    ; GFX10: [[V_BFE_U32_:%[0-9]+]]:vgpr_32 = V_BFE_U32 [[V_ADD_U16_e64_]], 0, 16, implicit $exec
63    ; GFX10: S_ENDPGM 0, implicit [[V_BFE_U32_]]
64    %0:vgpr(s32) = COPY $vgpr0
65    %1:vgpr(s32) = COPY $vgpr1
66    %2:vgpr(s16) = G_TRUNC %0
67    %3:vgpr(s16) = G_TRUNC %1
68    %4:vgpr(s16) = G_ADD %2, %3
69    %5:vgpr(s32) = G_ZEXT %4
70    S_ENDPGM 0, implicit %5
71
72...
73
74---
75name:            add_s16_neg_inline_const_64
76legalized:       true
77regBankSelected: true
78tracksRegLiveness: true
79
80body: |
81  bb.0:
82    liveins: $vgpr0
83
84    ; GFX6-LABEL: name: add_s16_neg_inline_const_64
85    ; GFX6: liveins: $vgpr0
86    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
87    ; GFX6: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
88    ; GFX6: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
89    ; GFX10-LABEL: name: add_s16_neg_inline_const_64
90    ; GFX10: liveins: $vgpr0
91    ; GFX10: $vcc_hi = IMPLICIT_DEF
92    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
93    ; GFX10: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
94    ; GFX10: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
95    %0:vgpr(s32) = COPY $vgpr0
96    %1:vgpr(s16) = G_TRUNC %0
97    %2:vgpr(s16) = G_CONSTANT i16 -64
98    %3:vgpr(s16) = G_ADD %1, %2
99    S_ENDPGM 0, implicit %3
100
101...
102
103---
104name:            add_s16_neg_inline_const_64_zext_to_s32
105legalized:       true
106regBankSelected: true
107tracksRegLiveness: true
108
109body: |
110  bb.0:
111    liveins: $vgpr0
112
113    ; GFX6-LABEL: name: add_s16_neg_inline_const_64_zext_to_s32
114    ; GFX6: liveins: $vgpr0
115    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
116    ; GFX6: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
117    ; GFX6: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
118    ; GFX10-LABEL: name: add_s16_neg_inline_const_64_zext_to_s32
119    ; GFX10: liveins: $vgpr0
120    ; GFX10: $vcc_hi = IMPLICIT_DEF
121    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
122    ; GFX10: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
123    ; GFX10: [[V_BFE_U32_:%[0-9]+]]:vgpr_32 = V_BFE_U32 [[V_SUB_U16_e64_]], 0, 16, implicit $exec
124    ; GFX10: S_ENDPGM 0, implicit [[V_BFE_U32_]]
125    %0:vgpr(s32) = COPY $vgpr0
126    %1:vgpr(s16) = G_TRUNC %0
127    %2:vgpr(s16) = G_CONSTANT i16 -64
128    %3:vgpr(s16) = G_ADD %1, %2
129    %4:vgpr(s32) = G_ZEXT %3
130    S_ENDPGM 0, implicit %4
131
132...
133