1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o -  | FileCheck -check-prefix=GCN %s
3# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o -  | FileCheck -check-prefix=GCN %s
4
5---
6name: cvt_pk_u16_vsv
7legalized: true
8regBankSelected: true
9tracksRegLiveness: true
10
11body: |
12  bb.0:
13    liveins: $sgpr0, $vgpr0
14    ; GCN-LABEL: name: cvt_pk_u16_vsv
15    ; GCN: liveins: $sgpr0, $vgpr0
16    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
17    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
18    ; GCN: [[V_CVT_PK_U16_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_U16_U32_e64 [[COPY]], [[COPY1]], implicit $exec
19    ; GCN: S_ENDPGM 0, implicit [[V_CVT_PK_U16_U32_e64_]]
20    %0:sgpr(s32) = COPY $sgpr0
21    %1:vgpr(s32) = COPY $vgpr0
22    %2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.u16), %0, %1
23    S_ENDPGM 0, implicit %2
24...
25
26---
27name: cvt_pk_u16_vvs
28legalized: true
29regBankSelected: true
30tracksRegLiveness: true
31
32body: |
33  bb.0:
34    liveins: $sgpr0, $vgpr0
35
36    ; GCN-LABEL: name: cvt_pk_u16_vvs
37    ; GCN: liveins: $sgpr0, $vgpr0
38    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
39    ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
40    ; GCN: [[V_CVT_PK_U16_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_U16_U32_e64 [[COPY]], [[COPY1]], implicit $exec
41    ; GCN: S_ENDPGM 0, implicit [[V_CVT_PK_U16_U32_e64_]]
42    %0:vgpr(s32) = COPY $vgpr0
43    %1:sgpr(s32) = COPY $sgpr0
44    %2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.u16), %0, %1
45    S_ENDPGM 0, implicit %2
46...
47
48---
49name: cvt_pk_u16_vvv
50legalized: true
51regBankSelected: true
52tracksRegLiveness: true
53
54body: |
55  bb.0:
56    liveins: $vgpr0, $vgpr1
57    ; GCN-LABEL: name: cvt_pk_u16_vvv
58    ; GCN: liveins: $vgpr0, $vgpr1
59    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
60    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
61    ; GCN: [[V_CVT_PK_U16_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_U16_U32_e64 [[COPY]], [[COPY1]], implicit $exec
62    ; GCN: S_ENDPGM 0, implicit [[V_CVT_PK_U16_U32_e64_]]
63    %0:vgpr(s32) = COPY $vgpr0
64    %1:vgpr(s32) = COPY $vgpr1
65    %2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.u16), %0, %1
66    S_ENDPGM 0, implicit %2
67...
68