1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX8 %s
3# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
4# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX10 %s
5
6---
7
8name:            and_or_s32_sgpr_sgpr_sgpr
9legalized:       true
10regBankSelected: true
11tracksRegLiveness: true
12
13body: |
14  bb.0:
15    liveins: $sgpr0, $sgpr1, $sgpr2
16    ; GFX8-LABEL: name: and_or_s32_sgpr_sgpr_sgpr
17    ; GFX8: liveins: $sgpr0, $sgpr1, $sgpr2
18    ; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
19    ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
20    ; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
21    ; GFX8: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
22    ; GFX8: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def $scc
23    ; GFX8: S_ENDPGM 0, implicit [[S_OR_B32_]]
24    ; GFX9-LABEL: name: and_or_s32_sgpr_sgpr_sgpr
25    ; GFX9: liveins: $sgpr0, $sgpr1, $sgpr2
26    ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
27    ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
28    ; GFX9: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
29    ; GFX9: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
30    ; GFX9: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def $scc
31    ; GFX9: S_ENDPGM 0, implicit [[S_OR_B32_]]
32    ; GFX10-LABEL: name: and_or_s32_sgpr_sgpr_sgpr
33    ; GFX10: liveins: $sgpr0, $sgpr1, $sgpr2
34    ; GFX10: $vcc_hi = IMPLICIT_DEF
35    ; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
36    ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
37    ; GFX10: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
38    ; GFX10: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
39    ; GFX10: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[COPY2]], implicit-def $scc
40    ; GFX10: S_ENDPGM 0, implicit [[S_OR_B32_]]
41    %0:sgpr(s32) = COPY $sgpr0
42    %1:sgpr(s32) = COPY $sgpr1
43    %2:sgpr(s32) = COPY $sgpr2
44    %3:sgpr(s32) = G_AND %0, %1
45    %4:sgpr(s32) = G_OR %3, %2
46    S_ENDPGM 0, implicit %4
47...
48
49---
50
51name:            and_or_s32_vgpr_vgpr_vgpr
52legalized:       true
53regBankSelected: true
54tracksRegLiveness: true
55
56body: |
57  bb.0:
58    liveins: $vgpr0, $vgpr1, $vgpr2
59    ; GFX8-LABEL: name: and_or_s32_vgpr_vgpr_vgpr
60    ; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
61    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
62    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
63    ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
64    ; GFX8: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
65    ; GFX8: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_AND_B32_e64_]], [[COPY2]], implicit $exec
66    ; GFX8: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
67    ; GFX9-LABEL: name: and_or_s32_vgpr_vgpr_vgpr
68    ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
69    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
70    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
71    ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
72    ; GFX9: [[V_AND_OR_B32_:%[0-9]+]]:vgpr_32 = V_AND_OR_B32 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
73    ; GFX9: S_ENDPGM 0, implicit [[V_AND_OR_B32_]]
74    ; GFX10-LABEL: name: and_or_s32_vgpr_vgpr_vgpr
75    ; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
76    ; GFX10: $vcc_hi = IMPLICIT_DEF
77    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
78    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
79    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
80    ; GFX10: [[V_AND_OR_B32_:%[0-9]+]]:vgpr_32 = V_AND_OR_B32 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
81    ; GFX10: S_ENDPGM 0, implicit [[V_AND_OR_B32_]]
82    %0:vgpr(s32) = COPY $vgpr0
83    %1:vgpr(s32) = COPY $vgpr1
84    %2:vgpr(s32) = COPY $vgpr2
85    %3:vgpr(s32) = G_AND %0, %1
86    %4:vgpr(s32) = G_OR %3, %2
87    S_ENDPGM 0, implicit %4
88...
89
90---
91
92name:            and_or_s32_vgpr_vgpr_vgpr_commute
93legalized:       true
94regBankSelected: true
95tracksRegLiveness: true
96
97body: |
98  bb.0:
99    liveins: $vgpr0, $vgpr1, $vgpr2
100    ; GFX8-LABEL: name: and_or_s32_vgpr_vgpr_vgpr_commute
101    ; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
102    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
103    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
104    ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
105    ; GFX8: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec
106    ; GFX8: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY2]], [[V_AND_B32_e64_]], implicit $exec
107    ; GFX8: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
108    ; GFX9-LABEL: name: and_or_s32_vgpr_vgpr_vgpr_commute
109    ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
110    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
111    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
112    ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
113    ; GFX9: [[V_AND_OR_B32_:%[0-9]+]]:vgpr_32 = V_AND_OR_B32 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
114    ; GFX9: S_ENDPGM 0, implicit [[V_AND_OR_B32_]]
115    ; GFX10-LABEL: name: and_or_s32_vgpr_vgpr_vgpr_commute
116    ; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
117    ; GFX10: $vcc_hi = IMPLICIT_DEF
118    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
119    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
120    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
121    ; GFX10: [[V_AND_OR_B32_:%[0-9]+]]:vgpr_32 = V_AND_OR_B32 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
122    ; GFX10: S_ENDPGM 0, implicit [[V_AND_OR_B32_]]
123    %0:vgpr(s32) = COPY $vgpr0
124    %1:vgpr(s32) = COPY $vgpr1
125    %2:vgpr(s32) = COPY $vgpr2
126    %3:vgpr(s32) = G_AND %0, %1
127    %4:vgpr(s32) = G_OR %2, %3
128    S_ENDPGM 0, implicit %4
129...
130
131---
132
133name:            and_or_s32_sgpr_sgpr_vgpr
134legalized:       true
135regBankSelected: true
136tracksRegLiveness: true
137
138body: |
139  bb.0:
140    liveins: $sgpr0, $sgpr1, $vgpr0
141    ; GFX8-LABEL: name: and_or_s32_sgpr_sgpr_vgpr
142    ; GFX8: liveins: $sgpr0, $sgpr1, $vgpr0
143    ; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
144    ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
145    ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
146    ; GFX8: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
147    ; GFX8: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[S_AND_B32_]]
148    ; GFX8: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY3]], [[COPY2]], implicit $exec
149    ; GFX8: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
150    ; GFX9-LABEL: name: and_or_s32_sgpr_sgpr_vgpr
151    ; GFX9: liveins: $sgpr0, $sgpr1, $vgpr0
152    ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
153    ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
154    ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
155    ; GFX9: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
156    ; GFX9: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[S_AND_B32_]]
157    ; GFX9: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY3]], [[COPY2]], implicit $exec
158    ; GFX9: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
159    ; GFX10-LABEL: name: and_or_s32_sgpr_sgpr_vgpr
160    ; GFX10: liveins: $sgpr0, $sgpr1, $vgpr0
161    ; GFX10: $vcc_hi = IMPLICIT_DEF
162    ; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
163    ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
164    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
165    ; GFX10: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def $scc
166    ; GFX10: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[S_AND_B32_]]
167    ; GFX10: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY3]], [[COPY2]], implicit $exec
168    ; GFX10: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
169    %0:sgpr(s32) = COPY $sgpr0
170    %1:sgpr(s32) = COPY $sgpr1
171    %2:vgpr(s32) = COPY $vgpr0
172    %3:sgpr(s32) = G_AND %0, %1
173    %4:vgpr(s32) = COPY %3
174    %5:vgpr(s32) = G_OR %4, %2
175    S_ENDPGM 0, implicit %5
176...
177