1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=legalizer -o - %s | FileCheck -check-prefix=UNPACKED %s 3; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=legalizer -o - %s | FileCheck -check-prefix=PACKED %s 4 5define amdgpu_ps void @image_store_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, half %data) { 6 ; UNPACKED-LABEL: name: image_store_f16 7 ; UNPACKED: bb.1 (%ir-block.0): 8 ; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2 9 ; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 10 ; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 11 ; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 12 ; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 13 ; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 14 ; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 15 ; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 16 ; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 17 ; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0 18 ; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1 19 ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2 20 ; UNPACKED: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY10]](s32) 21 ; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) 22 ; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32) 23 ; UNPACKED: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[TRUNC]](s16), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 2 into custom "TargetCustom8") 24 ; UNPACKED: S_ENDPGM 0 25 ; PACKED-LABEL: name: image_store_f16 26 ; PACKED: bb.1 (%ir-block.0): 27 ; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2 28 ; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 29 ; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 30 ; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 31 ; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 32 ; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 33 ; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 34 ; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 35 ; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 36 ; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0 37 ; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1 38 ; PACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2 39 ; PACKED: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY10]](s32) 40 ; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) 41 ; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32) 42 ; PACKED: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[TRUNC]](s16), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 2 into custom "TargetCustom8") 43 ; PACKED: S_ENDPGM 0 44 call void @llvm.amdgcn.image.store.2d.f16.i32(half %data, i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0) 45 ret void 46} 47 48define amdgpu_ps void @image_store_v2f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, <2 x half> %in) { 49 ; UNPACKED-LABEL: name: image_store_v2f16 50 ; UNPACKED: bb.1 (%ir-block.0): 51 ; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2 52 ; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 53 ; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 54 ; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 55 ; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 56 ; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 57 ; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 58 ; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 59 ; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 60 ; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0 61 ; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1 62 ; UNPACKED: [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2 63 ; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) 64 ; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32) 65 ; UNPACKED: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY10]](<2 x s16>) 66 ; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 67 ; UNPACKED: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) 68 ; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) 69 ; UNPACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) 70 ; UNPACKED: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY11]](s32), [[COPY12]](s32) 71 ; UNPACKED: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR2]](<2 x s32>), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 4 into custom "TargetCustom8") 72 ; UNPACKED: S_ENDPGM 0 73 ; PACKED-LABEL: name: image_store_v2f16 74 ; PACKED: bb.1 (%ir-block.0): 75 ; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2 76 ; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 77 ; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 78 ; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 79 ; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 80 ; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 81 ; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 82 ; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 83 ; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 84 ; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0 85 ; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1 86 ; PACKED: [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2 87 ; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) 88 ; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32) 89 ; PACKED: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[COPY10]](<2 x s16>), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 4 into custom "TargetCustom8") 90 ; PACKED: S_ENDPGM 0 91 call void @llvm.amdgcn.image.store.2d.v2f16.i32(<2 x half> %in, i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0) 92 ret void 93} 94 95define amdgpu_ps void @image_store_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, <3 x half> %in) { 96 ; UNPACKED-LABEL: name: image_store_v3f16 97 ; UNPACKED: bb.1 (%ir-block.0): 98 ; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3 99 ; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 100 ; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 101 ; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 102 ; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 103 ; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 104 ; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 105 ; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 106 ; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 107 ; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0 108 ; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1 109 ; UNPACKED: [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2 110 ; UNPACKED: [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3 111 ; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) 112 ; UNPACKED: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF 113 ; UNPACKED: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>), [[DEF]](<2 x s16>) 114 ; UNPACKED: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>) 115 ; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32) 116 ; UNPACKED: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF 117 ; UNPACKED: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[UV]](<3 x s16>), 0 118 ; UNPACKED: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>) 119 ; UNPACKED: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>) 120 ; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 121 ; UNPACKED: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) 122 ; UNPACKED: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>) 123 ; UNPACKED: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) 124 ; UNPACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) 125 ; UNPACKED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) 126 ; UNPACKED: [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32) 127 ; UNPACKED: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32) 128 ; UNPACKED: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR2]](<3 x s32>), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 6 into custom "TargetCustom8", align 8) 129 ; UNPACKED: S_ENDPGM 0 130 ; PACKED-LABEL: name: image_store_v3f16 131 ; PACKED: bb.1 (%ir-block.0): 132 ; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3 133 ; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 134 ; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 135 ; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 136 ; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 137 ; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 138 ; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 139 ; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 140 ; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 141 ; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0 142 ; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1 143 ; PACKED: [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2 144 ; PACKED: [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3 145 ; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) 146 ; PACKED: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF 147 ; PACKED: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>), [[DEF]](<2 x s16>) 148 ; PACKED: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<6 x s16>) 149 ; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32) 150 ; PACKED: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[UV]](<3 x s16>), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 6 into custom "TargetCustom8", align 8) 151 ; PACKED: S_ENDPGM 0 152 call void @llvm.amdgcn.image.store.2d.v3f16.i32(<3 x half> %in, i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0) 153 ret void 154} 155 156define amdgpu_ps void @image_store_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, <4 x half> %in) { 157 ; UNPACKED-LABEL: name: image_store_v4f16 158 ; UNPACKED: bb.1 (%ir-block.0): 159 ; UNPACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3 160 ; UNPACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 161 ; UNPACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 162 ; UNPACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 163 ; UNPACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 164 ; UNPACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 165 ; UNPACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 166 ; UNPACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 167 ; UNPACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 168 ; UNPACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0 169 ; UNPACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1 170 ; UNPACKED: [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2 171 ; UNPACKED: [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3 172 ; UNPACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) 173 ; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32) 174 ; UNPACKED: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY10]](<2 x s16>) 175 ; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 176 ; UNPACKED: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) 177 ; UNPACKED: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY11]](<2 x s16>) 178 ; UNPACKED: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) 179 ; UNPACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) 180 ; UNPACKED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) 181 ; UNPACKED: [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32) 182 ; UNPACKED: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32) 183 ; UNPACKED: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32) 184 ; UNPACKED: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR2]](<4 x s32>), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 8 into custom "TargetCustom8") 185 ; UNPACKED: S_ENDPGM 0 186 ; PACKED-LABEL: name: image_store_v4f16 187 ; PACKED: bb.1 (%ir-block.0): 188 ; PACKED: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3 189 ; PACKED: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 190 ; PACKED: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 191 ; PACKED: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 192 ; PACKED: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 193 ; PACKED: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 194 ; PACKED: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 195 ; PACKED: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 196 ; PACKED: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 197 ; PACKED: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0 198 ; PACKED: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1 199 ; PACKED: [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr2 200 ; PACKED: [[COPY11:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr3 201 ; PACKED: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) 202 ; PACKED: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>) 203 ; PACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32) 204 ; PACKED: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[CONCAT_VECTORS]](<4 x s16>), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store 8 into custom "TargetCustom8") 205 ; PACKED: S_ENDPGM 0 206 call void @llvm.amdgcn.image.store.2d.v4f16.i32(<4 x half> %in, i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0) 207 ret void 208} 209 210declare void @llvm.amdgcn.image.store.2d.f16.i32(half, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0 211declare void @llvm.amdgcn.image.store.2d.v2f16.i32(<2 x half>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0 212declare void @llvm.amdgcn.image.store.2d.v3f16.i32(<3 x half>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0 213declare void @llvm.amdgcn.image.store.2d.v4f16.i32(<4 x half>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0 214 215attributes #0 = { nounwind writeonly } 216