1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=GCN %s
3# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -run-pass=legalizer %s -o - | FileCheck -check-prefix=GCN %s
4
5---
6name: s_buffer_load_s32
7body:             |
8  bb.0:
9    liveins: $sgpr0_sgpr1_sgpr2_sgpr3
10
11    ; GCN-LABEL: name: s_buffer_load_s32
12    ; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
13    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
14    ; GCN: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[C]](s32), 0 :: (dereferenceable invariant load 4)
15    ; GCN: S_ENDPGM 0, implicit [[AMDGPU_S_BUFFER_LOAD]](s32)
16    %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
17    %1:_(s32) = G_CONSTANT i32 0
18    %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0
19    S_ENDPGM 0, implicit %2
20
21...
22
23---
24name: s_buffer_load_v3s32
25body:             |
26  bb.0:
27    liveins: $sgpr0_sgpr1_sgpr2_sgpr3
28
29    ; GCN-LABEL: name: s_buffer_load_v3s32
30    ; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
31    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
32    ; GCN: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[C]](s32), 0 :: (dereferenceable invariant load 12, align 4)
33    ; GCN: [[EXTRACT:%[0-9]+]]:_(<3 x s32>) = G_EXTRACT [[AMDGPU_S_BUFFER_LOAD]](<4 x s32>), 0
34    ; GCN: S_ENDPGM 0, implicit [[EXTRACT]](<3 x s32>)
35    %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
36    %1:_(s32) = G_CONSTANT i32 0
37    %2:_(<3 x s32>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0
38    S_ENDPGM 0, implicit %2
39
40...
41
42---
43name: s_buffer_load_v3p3
44body:             |
45  bb.0:
46    liveins: $sgpr0_sgpr1_sgpr2_sgpr3
47
48    ; GCN-LABEL: name: s_buffer_load_v3p3
49    ; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
50    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
51    ; GCN: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:_(<4 x p3>) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[C]](s32), 0 :: (dereferenceable invariant load 12, align 4)
52    ; GCN: [[EXTRACT:%[0-9]+]]:_(<3 x p3>) = G_EXTRACT [[AMDGPU_S_BUFFER_LOAD]](<4 x p3>), 0
53    ; GCN: S_ENDPGM 0, implicit [[EXTRACT]](<3 x p3>)
54    %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
55    %1:_(s32) = G_CONSTANT i32 0
56    %2:_(<3 x p3>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0
57    S_ENDPGM 0, implicit %2
58
59...
60
61---
62name: s_buffer_load_v6s16
63body:             |
64  bb.0:
65    liveins: $sgpr0_sgpr1_sgpr2_sgpr3
66
67    ; GCN-LABEL: name: s_buffer_load_v6s16
68    ; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
69    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
70    ; GCN: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:_(<8 x s16>) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[C]](s32), 0 :: (dereferenceable invariant load 12, align 4)
71    ; GCN: [[EXTRACT:%[0-9]+]]:_(<6 x s16>) = G_EXTRACT [[AMDGPU_S_BUFFER_LOAD]](<8 x s16>), 0
72    ; GCN: S_ENDPGM 0, implicit [[EXTRACT]](<6 x s16>)
73    %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
74    %1:_(s32) = G_CONSTANT i32 0
75    %2:_(<6 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0
76    S_ENDPGM 0, implicit %2
77
78...
79
80---
81name: s_buffer_load_v6s32
82body:             |
83  bb.0:
84    liveins: $sgpr0_sgpr1_sgpr2_sgpr3
85
86    ; GCN-LABEL: name: s_buffer_load_v6s32
87    ; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
88    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
89    ; GCN: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:_(<8 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[C]](s32), 0 :: (dereferenceable invariant load 24, align 4)
90    ; GCN: [[EXTRACT:%[0-9]+]]:_(<6 x s32>) = G_EXTRACT [[AMDGPU_S_BUFFER_LOAD]](<8 x s32>), 0
91    ; GCN: S_ENDPGM 0, implicit [[EXTRACT]](<6 x s32>)
92    %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
93    %1:_(s32) = G_CONSTANT i32 0
94    %2:_(<6 x s32>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0
95    S_ENDPGM 0, implicit %2
96
97...
98
99---
100name: s_buffer_load_v3s64
101body:             |
102  bb.0:
103    liveins: $sgpr0_sgpr1_sgpr2_sgpr3
104
105    ; GCN-LABEL: name: s_buffer_load_v3s64
106    ; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
107    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
108    ; GCN: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:_(<4 x s64>) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[C]](s32), 0 :: (dereferenceable invariant load 24, align 4)
109    ; GCN: [[EXTRACT:%[0-9]+]]:_(<3 x s64>) = G_EXTRACT [[AMDGPU_S_BUFFER_LOAD]](<4 x s64>), 0
110    ; GCN: S_ENDPGM 0, implicit [[EXTRACT]](<3 x s64>)
111    %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
112    %1:_(s32) = G_CONSTANT i32 0
113    %2:_(<3 x s64>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0
114    S_ENDPGM 0, implicit %2
115
116...
117
118---
119name: s_buffer_load_v12s8
120body:             |
121  bb.0:
122    liveins: $sgpr0_sgpr1_sgpr2_sgpr3
123
124    ; GCN-LABEL: name: s_buffer_load_v12s8
125    ; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
126    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
127    ; GCN: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:_(<16 x s8>) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[C]](s32), 0 :: (dereferenceable invariant load 12, align 4)
128    ; GCN: [[EXTRACT:%[0-9]+]]:_(<12 x s8>) = G_EXTRACT [[AMDGPU_S_BUFFER_LOAD]](<16 x s8>), 0
129    ; GCN: S_ENDPGM 0, implicit [[EXTRACT]](<12 x s8>)
130    %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
131    %1:_(s32) = G_CONSTANT i32 0
132    %2:_(<12 x s8>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0
133    S_ENDPGM 0, implicit %2
134
135...
136
137---
138name: s_buffer_load_s96
139body:             |
140  bb.0:
141    liveins: $sgpr0_sgpr1_sgpr2_sgpr3
142
143    ; GCN-LABEL: name: s_buffer_load_s96
144    ; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
145    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
146    ; GCN: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[C]](s32), 0 :: (dereferenceable invariant load 12, align 4)
147    ; GCN: [[EXTRACT:%[0-9]+]]:_(<3 x s32>) = G_EXTRACT [[AMDGPU_S_BUFFER_LOAD]](<4 x s32>), 0
148    ; GCN: S_ENDPGM 0, implicit [[EXTRACT]](<3 x s32>)
149    %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
150    %1:_(s32) = G_CONSTANT i32 0
151    %2:_(<3 x s32>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0
152    S_ENDPGM 0, implicit %2
153
154...
155