1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3
4define amdgpu_kernel void @test_wave32(i32 %arg0, [8 x i32], i32 %saved) {
5; GCN-LABEL: test_wave32:
6; GCN:       ; %bb.0: ; %entry
7; GCN-NEXT:    s_clause 0x1
8; GCN-NEXT:    s_load_dword s1, s[4:5], 0x0
9; GCN-NEXT:    s_load_dword s0, s[4:5], 0x24
10; GCN-NEXT:    ; implicit-def: $vcc_hi
11; GCN-NEXT:    s_waitcnt lgkmcnt(0)
12; GCN-NEXT:    s_cmp_lg_u32 s1, 0
13; GCN-NEXT:    s_cselect_b32 s1, 1, 0
14; GCN-NEXT:    s_and_b32 s1, s1, 1
15; GCN-NEXT:    s_cmp_lg_u32 s1, 0
16; GCN-NEXT:    s_cbranch_scc1 BB0_2
17; GCN-NEXT:  ; %bb.1: ; %mid
18; GCN-NEXT:    v_mov_b32_e32 v0, 0
19; GCN-NEXT:    global_store_dword v[0:1], v0, off
20; GCN-NEXT:  BB0_2: ; %bb
21; GCN-NEXT:    v_nop
22; GCN-NEXT:    s_or_b32 exec_lo, exec_lo, s0
23; GCN-NEXT:    v_mov_b32_e32 v0, 0
24; GCN-NEXT:    global_store_dword v[0:1], v0, off
25; GCN-NEXT:    s_endpgm
26entry:
27  %cond = icmp eq i32 %arg0, 0
28  br i1 %cond, label %mid, label %bb
29
30mid:
31  store volatile i32 0, i32 addrspace(1)* undef
32  br label %bb
33
34bb:
35  call void @llvm.amdgcn.end.cf.i32(i32 %saved)
36  store volatile i32 0, i32 addrspace(1)* undef
37  ret void
38}
39
40declare void @llvm.amdgcn.end.cf.i32(i32 %val)
41