1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
3# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
4
5---
6name: atomicrmw_and_global_i32_ss
7legalized: true
8
9body: |
10  bb.0:
11    liveins: $sgpr0_sgpr1, $sgpr2
12    ; CHECK-LABEL: name: atomicrmw_and_global_i32_ss
13    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1
14    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
15    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(p1) = COPY [[COPY]](p1)
16    ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
17    ; CHECK: [[ATOMICRMW_AND:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_AND [[COPY2]](p1), [[COPY3]] :: (load store seq_cst 4, addrspace 1)
18    %0:_(p1) = COPY $sgpr0_sgpr1
19    %1:_(s32) = COPY $sgpr2
20    %2:_(s32) = G_ATOMICRMW_AND %0, %1 :: (load store seq_cst 4, addrspace 1)
21...
22
23---
24name: atomicrmw_and_flat_i32_ss
25legalized: true
26
27body: |
28  bb.0:
29    liveins: $sgpr0_sgpr1, $sgpr2
30    ; CHECK-LABEL: name: atomicrmw_and_flat_i32_ss
31    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1
32    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
33    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(p0) = COPY [[COPY]](p0)
34    ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
35    ; CHECK: [[ATOMICRMW_AND:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_AND [[COPY2]](p0), [[COPY3]] :: (load store seq_cst 4)
36    %0:_(p0) = COPY $sgpr0_sgpr1
37    %1:_(s32) = COPY $sgpr2
38    %2:_(s32) = G_ATOMICRMW_AND %0, %1 :: (load store seq_cst 4, addrspace 0)
39...
40
41---
42name: atomicrmw_and_local_i32_ss
43legalized: true
44
45body: |
46  bb.0:
47    liveins: $sgpr0, $sgpr1
48    ; CHECK-LABEL: name: atomicrmw_and_local_i32_ss
49    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
50    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
51    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
52    ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
53    ; CHECK: [[ATOMICRMW_AND:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_AND [[COPY2]](p3), [[COPY3]] :: (load store seq_cst 4, addrspace 3)
54    %0:_(p3) = COPY $sgpr0
55    %1:_(s32) = COPY $sgpr1
56    %2:_(s32) = G_ATOMICRMW_AND %0, %1 :: (load store seq_cst 4, addrspace 3)
57...
58