1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s 3; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN,GFX10 %s 4 5define i32 @s_add_co_select_user() { 6; GFX9-LABEL: s_add_co_select_user: 7; GFX9: ; %bb.0: ; %bb 8; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 9; GFX9-NEXT: s_mov_b64 s[4:5], 0 10; GFX9-NEXT: s_load_dword s6, s[4:5], 0x0 11; GFX9-NEXT: s_waitcnt lgkmcnt(0) 12; GFX9-NEXT: v_add_co_u32_e64 v0, s[4:5], s6, s6 13; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 14; GFX9-NEXT: s_addc_u32 s4, s6, 0 15; GFX9-NEXT: s_cselect_b64 vcc, 1, 0 16; GFX9-NEXT: v_mov_b32_e32 v1, s4 17; GFX9-NEXT: s_cmp_gt_u32 s6, 31 18; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 19; GFX9-NEXT: s_cselect_b64 vcc, -1, 0 20; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc 21; GFX9-NEXT: s_setpc_b64 s[30:31] 22; 23; GFX10-LABEL: s_add_co_select_user: 24; GFX10: ; %bb.0: ; %bb 25; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 26; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 27; GFX10-NEXT: s_mov_b64 s[4:5], 0 28; GFX10-NEXT: ; implicit-def: $vcc_hi 29; GFX10-NEXT: s_load_dword s4, s[4:5], 0x0 30; GFX10-NEXT: s_waitcnt lgkmcnt(0) 31; GFX10-NEXT: v_add_co_u32_e64 v0, s5, s4, s4 32; GFX10-NEXT: s_cmpk_lg_u32 s5, 0x0 33; GFX10-NEXT: s_addc_u32 s5, s4, 0 34; GFX10-NEXT: s_cselect_b32 s6, 1, 0 35; GFX10-NEXT: s_cmp_gt_u32 s4, 31 36; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, s5, s6 37; GFX10-NEXT: s_cselect_b32 vcc_lo, -1, 0 38; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo 39; GFX10-NEXT: s_setpc_b64 s[30:31] 40bb: 41 %i = load volatile i32, i32 addrspace(4)* null, align 8 42 %i1 = add i32 %i, %i 43 %i2 = icmp ult i32 %i1, %i 44 %i3 = zext i1 %i2 to i32 45 %i4 = add nuw nsw i32 %i3, 0 46 %i5 = add i32 %i4, %i 47 %i6 = icmp ult i32 %i5, %i4 48 %i7 = select i1 %i6, i32 %i5, i32 0 49 %i8 = icmp ugt i32 %i, 31 50 %i9 = select i1 %i8, i32 %i1, i32 %i7 51 ret i32 %i9 52} 53 54define amdgpu_kernel void @s_add_co_br_user(i32 %i) { 55; GFX9-LABEL: s_add_co_br_user: 56; GFX9: ; %bb.0: ; %bb 57; GFX9-NEXT: s_load_dword s0, s[4:5], 0x0 58; GFX9-NEXT: s_waitcnt lgkmcnt(0) 59; GFX9-NEXT: s_add_i32 s1, s0, s0 60; GFX9-NEXT: v_mov_b32_e32 v0, s0 61; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s1, v0 62; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 63; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc 64; GFX9-NEXT: s_addc_u32 s0, s0, 0 65; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, s0, v0 66; GFX9-NEXT: s_and_b64 vcc, exec, vcc 67; GFX9-NEXT: s_cbranch_vccnz BB1_2 68; GFX9-NEXT: ; %bb.1: ; %bb0 69; GFX9-NEXT: v_mov_b32_e32 v0, 0 70; GFX9-NEXT: v_mov_b32_e32 v2, 9 71; GFX9-NEXT: v_mov_b32_e32 v1, 0 72; GFX9-NEXT: global_store_dword v[0:1], v2, off 73; GFX9-NEXT: BB1_2: ; %bb1 74; GFX9-NEXT: v_mov_b32_e32 v0, 0 75; GFX9-NEXT: v_mov_b32_e32 v2, 10 76; GFX9-NEXT: v_mov_b32_e32 v1, 0 77; GFX9-NEXT: global_store_dword v[0:1], v2, off 78; GFX9-NEXT: s_endpgm 79; 80; GFX10-LABEL: s_add_co_br_user: 81; GFX10: ; %bb.0: ; %bb 82; GFX10-NEXT: s_load_dword s0, s[4:5], 0x0 83; GFX10-NEXT: ; implicit-def: $vcc_hi 84; GFX10-NEXT: s_waitcnt lgkmcnt(0) 85; GFX10-NEXT: s_add_i32 s1, s0, s0 86; GFX10-NEXT: v_cmp_lt_u32_e64 s1, s1, s0 87; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1 88; GFX10-NEXT: s_cmpk_lg_u32 s1, 0x0 89; GFX10-NEXT: s_addc_u32 s0, s0, 0 90; GFX10-NEXT: v_cmp_ge_u32_e32 vcc_lo, s0, v0 91; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo 92; GFX10-NEXT: s_cbranch_vccnz BB1_2 93; GFX10-NEXT: ; %bb.1: ; %bb0 94; GFX10-NEXT: v_mov_b32_e32 v0, 0 95; GFX10-NEXT: v_mov_b32_e32 v2, 9 96; GFX10-NEXT: v_mov_b32_e32 v1, 0 97; GFX10-NEXT: global_store_dword v[0:1], v2, off 98; GFX10-NEXT: BB1_2: ; %bb1 99; GFX10-NEXT: v_mov_b32_e32 v0, 0 100; GFX10-NEXT: v_mov_b32_e32 v2, 10 101; GFX10-NEXT: v_mov_b32_e32 v1, 0 102; GFX10-NEXT: global_store_dword v[0:1], v2, off 103; GFX10-NEXT: s_endpgm 104bb: 105 %i1 = add i32 %i, %i 106 %i2 = icmp ult i32 %i1, %i 107 %i3 = zext i1 %i2 to i32 108 %i4 = add nuw nsw i32 %i3, 0 109 %i5 = add i32 %i4, %i 110 %i6 = icmp ult i32 %i5, %i4 111 %i7 = select i1 %i6, i32 %i5, i32 0 112 br i1 %i6, label %bb0, label %bb1 113 114bb0: 115 store volatile i32 9, i32 addrspace(1)* null 116 br label %bb1 117 118bb1: 119 store volatile i32 10, i32 addrspace(1)* null 120 ret void 121} 122