1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // REQUIRES: riscv-registered-target
3 // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
4
5 #include <riscv_vector.h>
6
7 // CHECK-RV64-LABEL: @test_vwredsum_vs_i8mf8_i16m1(
8 // CHECK-RV64-NEXT: entry:
9 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 1 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 [[VL:%.*]])
10 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
11 //
test_vwredsum_vs_i8mf8_i16m1(vint16m1_t dst,vint8mf8_t vector,vint16m1_t scalar,size_t vl)12 vint16m1_t test_vwredsum_vs_i8mf8_i16m1(vint16m1_t dst, vint8mf8_t vector,
13 vint16m1_t scalar, size_t vl) {
14 return vwredsum_vs_i8mf8_i16m1(dst, vector, scalar, vl);
15 }
16
17 // CHECK-RV64-LABEL: @test_vwredsum_vs_i8mf4_i16m1(
18 // CHECK-RV64-NEXT: entry:
19 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 2 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 [[VL:%.*]])
20 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
21 //
test_vwredsum_vs_i8mf4_i16m1(vint16m1_t dst,vint8mf4_t vector,vint16m1_t scalar,size_t vl)22 vint16m1_t test_vwredsum_vs_i8mf4_i16m1(vint16m1_t dst, vint8mf4_t vector,
23 vint16m1_t scalar, size_t vl) {
24 return vwredsum_vs_i8mf4_i16m1(dst, vector, scalar, vl);
25 }
26
27 // CHECK-RV64-LABEL: @test_vwredsum_vs_i8mf2_i16m1(
28 // CHECK-RV64-NEXT: entry:
29 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 [[VL:%.*]])
30 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
31 //
test_vwredsum_vs_i8mf2_i16m1(vint16m1_t dst,vint8mf2_t vector,vint16m1_t scalar,size_t vl)32 vint16m1_t test_vwredsum_vs_i8mf2_i16m1(vint16m1_t dst, vint8mf2_t vector,
33 vint16m1_t scalar, size_t vl) {
34 return vwredsum_vs_i8mf2_i16m1(dst, vector, scalar, vl);
35 }
36
37 // CHECK-RV64-LABEL: @test_vwredsum_vs_i8m1_i16m1(
38 // CHECK-RV64-NEXT: entry:
39 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 8 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 [[VL:%.*]])
40 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
41 //
test_vwredsum_vs_i8m1_i16m1(vint16m1_t dst,vint8m1_t vector,vint16m1_t scalar,size_t vl)42 vint16m1_t test_vwredsum_vs_i8m1_i16m1(vint16m1_t dst, vint8m1_t vector,
43 vint16m1_t scalar, size_t vl) {
44 return vwredsum_vs_i8m1_i16m1(dst, vector, scalar, vl);
45 }
46
47 // CHECK-RV64-LABEL: @test_vwredsum_vs_i8m2_i16m1(
48 // CHECK-RV64-NEXT: entry:
49 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 16 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 [[VL:%.*]])
50 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
51 //
test_vwredsum_vs_i8m2_i16m1(vint16m1_t dst,vint8m2_t vector,vint16m1_t scalar,size_t vl)52 vint16m1_t test_vwredsum_vs_i8m2_i16m1(vint16m1_t dst, vint8m2_t vector,
53 vint16m1_t scalar, size_t vl) {
54 return vwredsum_vs_i8m2_i16m1(dst, vector, scalar, vl);
55 }
56
57 // CHECK-RV64-LABEL: @test_vwredsum_vs_i8m4_i16m1(
58 // CHECK-RV64-NEXT: entry:
59 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 32 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 [[VL:%.*]])
60 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
61 //
test_vwredsum_vs_i8m4_i16m1(vint16m1_t dst,vint8m4_t vector,vint16m1_t scalar,size_t vl)62 vint16m1_t test_vwredsum_vs_i8m4_i16m1(vint16m1_t dst, vint8m4_t vector,
63 vint16m1_t scalar, size_t vl) {
64 return vwredsum_vs_i8m4_i16m1(dst, vector, scalar, vl);
65 }
66
67 // CHECK-RV64-LABEL: @test_vwredsum_vs_i8m8_i16m1(
68 // CHECK-RV64-NEXT: entry:
69 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 64 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 [[VL:%.*]])
70 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
71 //
test_vwredsum_vs_i8m8_i16m1(vint16m1_t dst,vint8m8_t vector,vint16m1_t scalar,size_t vl)72 vint16m1_t test_vwredsum_vs_i8m8_i16m1(vint16m1_t dst, vint8m8_t vector,
73 vint16m1_t scalar, size_t vl) {
74 return vwredsum_vs_i8m8_i16m1(dst, vector, scalar, vl);
75 }
76
77 // CHECK-RV64-LABEL: @test_vwredsum_vs_i16mf4_i32m1(
78 // CHECK-RV64-NEXT: entry:
79 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 1 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 [[VL:%.*]])
80 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
81 //
test_vwredsum_vs_i16mf4_i32m1(vint32m1_t dst,vint16mf4_t vector,vint32m1_t scalar,size_t vl)82 vint32m1_t test_vwredsum_vs_i16mf4_i32m1(vint32m1_t dst, vint16mf4_t vector,
83 vint32m1_t scalar, size_t vl) {
84 return vwredsum_vs_i16mf4_i32m1(dst, vector, scalar, vl);
85 }
86
87 // CHECK-RV64-LABEL: @test_vwredsum_vs_i16mf2_i32m1(
88 // CHECK-RV64-NEXT: entry:
89 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 [[VL:%.*]])
90 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
91 //
test_vwredsum_vs_i16mf2_i32m1(vint32m1_t dst,vint16mf2_t vector,vint32m1_t scalar,size_t vl)92 vint32m1_t test_vwredsum_vs_i16mf2_i32m1(vint32m1_t dst, vint16mf2_t vector,
93 vint32m1_t scalar, size_t vl) {
94 return vwredsum_vs_i16mf2_i32m1(dst, vector, scalar, vl);
95 }
96
97 // CHECK-RV64-LABEL: @test_vwredsum_vs_i16m1_i32m1(
98 // CHECK-RV64-NEXT: entry:
99 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv4i16.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 4 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 [[VL:%.*]])
100 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
101 //
test_vwredsum_vs_i16m1_i32m1(vint32m1_t dst,vint16m1_t vector,vint32m1_t scalar,size_t vl)102 vint32m1_t test_vwredsum_vs_i16m1_i32m1(vint32m1_t dst, vint16m1_t vector,
103 vint32m1_t scalar, size_t vl) {
104 return vwredsum_vs_i16m1_i32m1(dst, vector, scalar, vl);
105 }
106
107 // CHECK-RV64-LABEL: @test_vwredsum_vs_i16m2_i32m1(
108 // CHECK-RV64-NEXT: entry:
109 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv8i16.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 8 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 [[VL:%.*]])
110 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
111 //
test_vwredsum_vs_i16m2_i32m1(vint32m1_t dst,vint16m2_t vector,vint32m1_t scalar,size_t vl)112 vint32m1_t test_vwredsum_vs_i16m2_i32m1(vint32m1_t dst, vint16m2_t vector,
113 vint32m1_t scalar, size_t vl) {
114 return vwredsum_vs_i16m2_i32m1(dst, vector, scalar, vl);
115 }
116
117 // CHECK-RV64-LABEL: @test_vwredsum_vs_i16m4_i32m1(
118 // CHECK-RV64-NEXT: entry:
119 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv16i16.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 16 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 [[VL:%.*]])
120 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
121 //
test_vwredsum_vs_i16m4_i32m1(vint32m1_t dst,vint16m4_t vector,vint32m1_t scalar,size_t vl)122 vint32m1_t test_vwredsum_vs_i16m4_i32m1(vint32m1_t dst, vint16m4_t vector,
123 vint32m1_t scalar, size_t vl) {
124 return vwredsum_vs_i16m4_i32m1(dst, vector, scalar, vl);
125 }
126
127 // CHECK-RV64-LABEL: @test_vwredsum_vs_i16m8_i32m1(
128 // CHECK-RV64-NEXT: entry:
129 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv32i16.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 32 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 [[VL:%.*]])
130 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
131 //
test_vwredsum_vs_i16m8_i32m1(vint32m1_t dst,vint16m8_t vector,vint32m1_t scalar,size_t vl)132 vint32m1_t test_vwredsum_vs_i16m8_i32m1(vint32m1_t dst, vint16m8_t vector,
133 vint32m1_t scalar, size_t vl) {
134 return vwredsum_vs_i16m8_i32m1(dst, vector, scalar, vl);
135 }
136
137 // CHECK-RV64-LABEL: @test_vwredsum_vs_i32mf2_i64m1(
138 // CHECK-RV64-NEXT: entry:
139 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 [[VL:%.*]])
140 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
141 //
test_vwredsum_vs_i32mf2_i64m1(vint64m1_t dst,vint32mf2_t vector,vint64m1_t scalar,size_t vl)142 vint64m1_t test_vwredsum_vs_i32mf2_i64m1(vint64m1_t dst, vint32mf2_t vector,
143 vint64m1_t scalar, size_t vl) {
144 return vwredsum_vs_i32mf2_i64m1(dst, vector, scalar, vl);
145 }
146
147 // CHECK-RV64-LABEL: @test_vwredsum_vs_i32m1_i64m1(
148 // CHECK-RV64-NEXT: entry:
149 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv2i32.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 2 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 [[VL:%.*]])
150 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
151 //
test_vwredsum_vs_i32m1_i64m1(vint64m1_t dst,vint32m1_t vector,vint64m1_t scalar,size_t vl)152 vint64m1_t test_vwredsum_vs_i32m1_i64m1(vint64m1_t dst, vint32m1_t vector,
153 vint64m1_t scalar, size_t vl) {
154 return vwredsum_vs_i32m1_i64m1(dst, vector, scalar, vl);
155 }
156
157 // CHECK-RV64-LABEL: @test_vwredsum_vs_i32m2_i64m1(
158 // CHECK-RV64-NEXT: entry:
159 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv4i32.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 4 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 [[VL:%.*]])
160 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
161 //
test_vwredsum_vs_i32m2_i64m1(vint64m1_t dst,vint32m2_t vector,vint64m1_t scalar,size_t vl)162 vint64m1_t test_vwredsum_vs_i32m2_i64m1(vint64m1_t dst, vint32m2_t vector,
163 vint64m1_t scalar, size_t vl) {
164 return vwredsum_vs_i32m2_i64m1(dst, vector, scalar, vl);
165 }
166
167 // CHECK-RV64-LABEL: @test_vwredsum_vs_i32m4_i64m1(
168 // CHECK-RV64-NEXT: entry:
169 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv8i32.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 8 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 [[VL:%.*]])
170 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
171 //
test_vwredsum_vs_i32m4_i64m1(vint64m1_t dst,vint32m4_t vector,vint64m1_t scalar,size_t vl)172 vint64m1_t test_vwredsum_vs_i32m4_i64m1(vint64m1_t dst, vint32m4_t vector,
173 vint64m1_t scalar, size_t vl) {
174 return vwredsum_vs_i32m4_i64m1(dst, vector, scalar, vl);
175 }
176
177 // CHECK-RV64-LABEL: @test_vwredsum_vs_i32m8_i64m1(
178 // CHECK-RV64-NEXT: entry:
179 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv16i32.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 16 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 [[VL:%.*]])
180 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
181 //
test_vwredsum_vs_i32m8_i64m1(vint64m1_t dst,vint32m8_t vector,vint64m1_t scalar,size_t vl)182 vint64m1_t test_vwredsum_vs_i32m8_i64m1(vint64m1_t dst, vint32m8_t vector,
183 vint64m1_t scalar, size_t vl) {
184 return vwredsum_vs_i32m8_i64m1(dst, vector, scalar, vl);
185 }
186
187 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u8mf8_u16m1(
188 // CHECK-RV64-NEXT: entry:
189 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 1 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 [[VL:%.*]])
190 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
191 //
test_vwredsumu_vs_u8mf8_u16m1(vuint16m1_t dst,vuint8mf8_t vector,vuint16m1_t scalar,size_t vl)192 vuint16m1_t test_vwredsumu_vs_u8mf8_u16m1(vuint16m1_t dst, vuint8mf8_t vector,
193 vuint16m1_t scalar, size_t vl) {
194 return vwredsumu_vs_u8mf8_u16m1(dst, vector, scalar, vl);
195 }
196
197 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u8mf4_u16m1(
198 // CHECK-RV64-NEXT: entry:
199 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 2 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 [[VL:%.*]])
200 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
201 //
test_vwredsumu_vs_u8mf4_u16m1(vuint16m1_t dst,vuint8mf4_t vector,vuint16m1_t scalar,size_t vl)202 vuint16m1_t test_vwredsumu_vs_u8mf4_u16m1(vuint16m1_t dst, vuint8mf4_t vector,
203 vuint16m1_t scalar, size_t vl) {
204 return vwredsumu_vs_u8mf4_u16m1(dst, vector, scalar, vl);
205 }
206
207 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u8mf2_u16m1(
208 // CHECK-RV64-NEXT: entry:
209 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 [[VL:%.*]])
210 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
211 //
test_vwredsumu_vs_u8mf2_u16m1(vuint16m1_t dst,vuint8mf2_t vector,vuint16m1_t scalar,size_t vl)212 vuint16m1_t test_vwredsumu_vs_u8mf2_u16m1(vuint16m1_t dst, vuint8mf2_t vector,
213 vuint16m1_t scalar, size_t vl) {
214 return vwredsumu_vs_u8mf2_u16m1(dst, vector, scalar, vl);
215 }
216
217 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u8m1_u16m1(
218 // CHECK-RV64-NEXT: entry:
219 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 8 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 [[VL:%.*]])
220 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
221 //
test_vwredsumu_vs_u8m1_u16m1(vuint16m1_t dst,vuint8m1_t vector,vuint16m1_t scalar,size_t vl)222 vuint16m1_t test_vwredsumu_vs_u8m1_u16m1(vuint16m1_t dst, vuint8m1_t vector,
223 vuint16m1_t scalar, size_t vl) {
224 return vwredsumu_vs_u8m1_u16m1(dst, vector, scalar, vl);
225 }
226
227 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u8m2_u16m1(
228 // CHECK-RV64-NEXT: entry:
229 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 16 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 [[VL:%.*]])
230 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
231 //
test_vwredsumu_vs_u8m2_u16m1(vuint16m1_t dst,vuint8m2_t vector,vuint16m1_t scalar,size_t vl)232 vuint16m1_t test_vwredsumu_vs_u8m2_u16m1(vuint16m1_t dst, vuint8m2_t vector,
233 vuint16m1_t scalar, size_t vl) {
234 return vwredsumu_vs_u8m2_u16m1(dst, vector, scalar, vl);
235 }
236
237 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u8m4_u16m1(
238 // CHECK-RV64-NEXT: entry:
239 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 32 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 [[VL:%.*]])
240 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
241 //
test_vwredsumu_vs_u8m4_u16m1(vuint16m1_t dst,vuint8m4_t vector,vuint16m1_t scalar,size_t vl)242 vuint16m1_t test_vwredsumu_vs_u8m4_u16m1(vuint16m1_t dst, vuint8m4_t vector,
243 vuint16m1_t scalar, size_t vl) {
244 return vwredsumu_vs_u8m4_u16m1(dst, vector, scalar, vl);
245 }
246
247 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u8m8_u16m1(
248 // CHECK-RV64-NEXT: entry:
249 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 64 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], i64 [[VL:%.*]])
250 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
251 //
test_vwredsumu_vs_u8m8_u16m1(vuint16m1_t dst,vuint8m8_t vector,vuint16m1_t scalar,size_t vl)252 vuint16m1_t test_vwredsumu_vs_u8m8_u16m1(vuint16m1_t dst, vuint8m8_t vector,
253 vuint16m1_t scalar, size_t vl) {
254 return vwredsumu_vs_u8m8_u16m1(dst, vector, scalar, vl);
255 }
256
257 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u16mf4_u32m1(
258 // CHECK-RV64-NEXT: entry:
259 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 1 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 [[VL:%.*]])
260 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
261 //
test_vwredsumu_vs_u16mf4_u32m1(vuint32m1_t dst,vuint16mf4_t vector,vuint32m1_t scalar,size_t vl)262 vuint32m1_t test_vwredsumu_vs_u16mf4_u32m1(vuint32m1_t dst, vuint16mf4_t vector,
263 vuint32m1_t scalar, size_t vl) {
264 return vwredsumu_vs_u16mf4_u32m1(dst, vector, scalar, vl);
265 }
266
267 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u16mf2_u32m1(
268 // CHECK-RV64-NEXT: entry:
269 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 [[VL:%.*]])
270 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
271 //
test_vwredsumu_vs_u16mf2_u32m1(vuint32m1_t dst,vuint16mf2_t vector,vuint32m1_t scalar,size_t vl)272 vuint32m1_t test_vwredsumu_vs_u16mf2_u32m1(vuint32m1_t dst, vuint16mf2_t vector,
273 vuint32m1_t scalar, size_t vl) {
274 return vwredsumu_vs_u16mf2_u32m1(dst, vector, scalar, vl);
275 }
276
277 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u16m1_u32m1(
278 // CHECK-RV64-NEXT: entry:
279 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv4i16.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 4 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 [[VL:%.*]])
280 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
281 //
test_vwredsumu_vs_u16m1_u32m1(vuint32m1_t dst,vuint16m1_t vector,vuint32m1_t scalar,size_t vl)282 vuint32m1_t test_vwredsumu_vs_u16m1_u32m1(vuint32m1_t dst, vuint16m1_t vector,
283 vuint32m1_t scalar, size_t vl) {
284 return vwredsumu_vs_u16m1_u32m1(dst, vector, scalar, vl);
285 }
286
287 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u16m2_u32m1(
288 // CHECK-RV64-NEXT: entry:
289 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv8i16.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 8 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 [[VL:%.*]])
290 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
291 //
test_vwredsumu_vs_u16m2_u32m1(vuint32m1_t dst,vuint16m2_t vector,vuint32m1_t scalar,size_t vl)292 vuint32m1_t test_vwredsumu_vs_u16m2_u32m1(vuint32m1_t dst, vuint16m2_t vector,
293 vuint32m1_t scalar, size_t vl) {
294 return vwredsumu_vs_u16m2_u32m1(dst, vector, scalar, vl);
295 }
296
297 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u16m4_u32m1(
298 // CHECK-RV64-NEXT: entry:
299 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv16i16.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 16 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 [[VL:%.*]])
300 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
301 //
test_vwredsumu_vs_u16m4_u32m1(vuint32m1_t dst,vuint16m4_t vector,vuint32m1_t scalar,size_t vl)302 vuint32m1_t test_vwredsumu_vs_u16m4_u32m1(vuint32m1_t dst, vuint16m4_t vector,
303 vuint32m1_t scalar, size_t vl) {
304 return vwredsumu_vs_u16m4_u32m1(dst, vector, scalar, vl);
305 }
306
307 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u16m8_u32m1(
308 // CHECK-RV64-NEXT: entry:
309 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv32i16.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 32 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], i64 [[VL:%.*]])
310 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
311 //
test_vwredsumu_vs_u16m8_u32m1(vuint32m1_t dst,vuint16m8_t vector,vuint32m1_t scalar,size_t vl)312 vuint32m1_t test_vwredsumu_vs_u16m8_u32m1(vuint32m1_t dst, vuint16m8_t vector,
313 vuint32m1_t scalar, size_t vl) {
314 return vwredsumu_vs_u16m8_u32m1(dst, vector, scalar, vl);
315 }
316
317 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u32mf2_u64m1(
318 // CHECK-RV64-NEXT: entry:
319 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 [[VL:%.*]])
320 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
321 //
test_vwredsumu_vs_u32mf2_u64m1(vuint64m1_t dst,vuint32mf2_t vector,vuint64m1_t scalar,size_t vl)322 vuint64m1_t test_vwredsumu_vs_u32mf2_u64m1(vuint64m1_t dst, vuint32mf2_t vector,
323 vuint64m1_t scalar, size_t vl) {
324 return vwredsumu_vs_u32mf2_u64m1(dst, vector, scalar, vl);
325 }
326
327 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u32m1_u64m1(
328 // CHECK-RV64-NEXT: entry:
329 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv2i32.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 2 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 [[VL:%.*]])
330 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
331 //
test_vwredsumu_vs_u32m1_u64m1(vuint64m1_t dst,vuint32m1_t vector,vuint64m1_t scalar,size_t vl)332 vuint64m1_t test_vwredsumu_vs_u32m1_u64m1(vuint64m1_t dst, vuint32m1_t vector,
333 vuint64m1_t scalar, size_t vl) {
334 return vwredsumu_vs_u32m1_u64m1(dst, vector, scalar, vl);
335 }
336
337 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u32m2_u64m1(
338 // CHECK-RV64-NEXT: entry:
339 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv4i32.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 4 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 [[VL:%.*]])
340 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
341 //
test_vwredsumu_vs_u32m2_u64m1(vuint64m1_t dst,vuint32m2_t vector,vuint64m1_t scalar,size_t vl)342 vuint64m1_t test_vwredsumu_vs_u32m2_u64m1(vuint64m1_t dst, vuint32m2_t vector,
343 vuint64m1_t scalar, size_t vl) {
344 return vwredsumu_vs_u32m2_u64m1(dst, vector, scalar, vl);
345 }
346
347 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u32m4_u64m1(
348 // CHECK-RV64-NEXT: entry:
349 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv8i32.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 8 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 [[VL:%.*]])
350 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
351 //
test_vwredsumu_vs_u32m4_u64m1(vuint64m1_t dst,vuint32m4_t vector,vuint64m1_t scalar,size_t vl)352 vuint64m1_t test_vwredsumu_vs_u32m4_u64m1(vuint64m1_t dst, vuint32m4_t vector,
353 vuint64m1_t scalar, size_t vl) {
354 return vwredsumu_vs_u32m4_u64m1(dst, vector, scalar, vl);
355 }
356
357 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u32m8_u64m1(
358 // CHECK-RV64-NEXT: entry:
359 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv16i32.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 16 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], i64 [[VL:%.*]])
360 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
361 //
test_vwredsumu_vs_u32m8_u64m1(vuint64m1_t dst,vuint32m8_t vector,vuint64m1_t scalar,size_t vl)362 vuint64m1_t test_vwredsumu_vs_u32m8_u64m1(vuint64m1_t dst, vuint32m8_t vector,
363 vuint64m1_t scalar, size_t vl) {
364 return vwredsumu_vs_u32m8_u64m1(dst, vector, scalar, vl);
365 }
366
367 // CHECK-RV64-LABEL: @test_vwredsum_vs_i8mf8_i16m1_m(
368 // CHECK-RV64-NEXT: entry:
369 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 1 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
370 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
371 //
test_vwredsum_vs_i8mf8_i16m1_m(vbool64_t mask,vint16m1_t dst,vint8mf8_t vector,vint16m1_t scalar,size_t vl)372 vint16m1_t test_vwredsum_vs_i8mf8_i16m1_m(vbool64_t mask, vint16m1_t dst,
373 vint8mf8_t vector, vint16m1_t scalar,
374 size_t vl) {
375 return vwredsum_vs_i8mf8_i16m1_m(mask, dst, vector, scalar, vl);
376 }
377
378 // CHECK-RV64-LABEL: @test_vwredsum_vs_i8mf4_i16m1_m(
379 // CHECK-RV64-NEXT: entry:
380 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 2 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
381 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
382 //
test_vwredsum_vs_i8mf4_i16m1_m(vbool32_t mask,vint16m1_t dst,vint8mf4_t vector,vint16m1_t scalar,size_t vl)383 vint16m1_t test_vwredsum_vs_i8mf4_i16m1_m(vbool32_t mask, vint16m1_t dst,
384 vint8mf4_t vector, vint16m1_t scalar,
385 size_t vl) {
386 return vwredsum_vs_i8mf4_i16m1_m(mask, dst, vector, scalar, vl);
387 }
388
389 // CHECK-RV64-LABEL: @test_vwredsum_vs_i8mf2_i16m1_m(
390 // CHECK-RV64-NEXT: entry:
391 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
392 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
393 //
test_vwredsum_vs_i8mf2_i16m1_m(vbool16_t mask,vint16m1_t dst,vint8mf2_t vector,vint16m1_t scalar,size_t vl)394 vint16m1_t test_vwredsum_vs_i8mf2_i16m1_m(vbool16_t mask, vint16m1_t dst,
395 vint8mf2_t vector, vint16m1_t scalar,
396 size_t vl) {
397 return vwredsum_vs_i8mf2_i16m1_m(mask, dst, vector, scalar, vl);
398 }
399
400 // CHECK-RV64-LABEL: @test_vwredsum_vs_i8m1_i16m1_m(
401 // CHECK-RV64-NEXT: entry:
402 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 8 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
403 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
404 //
test_vwredsum_vs_i8m1_i16m1_m(vbool8_t mask,vint16m1_t dst,vint8m1_t vector,vint16m1_t scalar,size_t vl)405 vint16m1_t test_vwredsum_vs_i8m1_i16m1_m(vbool8_t mask, vint16m1_t dst,
406 vint8m1_t vector, vint16m1_t scalar,
407 size_t vl) {
408 return vwredsum_vs_i8m1_i16m1_m(mask, dst, vector, scalar, vl);
409 }
410
411 // CHECK-RV64-LABEL: @test_vwredsum_vs_i8m2_i16m1_m(
412 // CHECK-RV64-NEXT: entry:
413 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 16 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
414 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
415 //
test_vwredsum_vs_i8m2_i16m1_m(vbool4_t mask,vint16m1_t dst,vint8m2_t vector,vint16m1_t scalar,size_t vl)416 vint16m1_t test_vwredsum_vs_i8m2_i16m1_m(vbool4_t mask, vint16m1_t dst,
417 vint8m2_t vector, vint16m1_t scalar,
418 size_t vl) {
419 return vwredsum_vs_i8m2_i16m1_m(mask, dst, vector, scalar, vl);
420 }
421
422 // CHECK-RV64-LABEL: @test_vwredsum_vs_i8m4_i16m1_m(
423 // CHECK-RV64-NEXT: entry:
424 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 32 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
425 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
426 //
test_vwredsum_vs_i8m4_i16m1_m(vbool2_t mask,vint16m1_t dst,vint8m4_t vector,vint16m1_t scalar,size_t vl)427 vint16m1_t test_vwredsum_vs_i8m4_i16m1_m(vbool2_t mask, vint16m1_t dst,
428 vint8m4_t vector, vint16m1_t scalar,
429 size_t vl) {
430 return vwredsum_vs_i8m4_i16m1_m(mask, dst, vector, scalar, vl);
431 }
432
433 // CHECK-RV64-LABEL: @test_vwredsum_vs_i8m8_i16m1_m(
434 // CHECK-RV64-NEXT: entry:
435 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 64 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
436 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
437 //
test_vwredsum_vs_i8m8_i16m1_m(vbool1_t mask,vint16m1_t dst,vint8m8_t vector,vint16m1_t scalar,size_t vl)438 vint16m1_t test_vwredsum_vs_i8m8_i16m1_m(vbool1_t mask, vint16m1_t dst,
439 vint8m8_t vector, vint16m1_t scalar,
440 size_t vl) {
441 return vwredsum_vs_i8m8_i16m1_m(mask, dst, vector, scalar, vl);
442 }
443
444 // CHECK-RV64-LABEL: @test_vwredsum_vs_i16mf4_i32m1_m(
445 // CHECK-RV64-NEXT: entry:
446 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 1 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
447 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
448 //
test_vwredsum_vs_i16mf4_i32m1_m(vbool64_t mask,vint32m1_t dst,vint16mf4_t vector,vint32m1_t scalar,size_t vl)449 vint32m1_t test_vwredsum_vs_i16mf4_i32m1_m(vbool64_t mask, vint32m1_t dst,
450 vint16mf4_t vector,
451 vint32m1_t scalar, size_t vl) {
452 return vwredsum_vs_i16mf4_i32m1_m(mask, dst, vector, scalar, vl);
453 }
454
455 // CHECK-RV64-LABEL: @test_vwredsum_vs_i16mf2_i32m1_m(
456 // CHECK-RV64-NEXT: entry:
457 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
458 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
459 //
test_vwredsum_vs_i16mf2_i32m1_m(vbool32_t mask,vint32m1_t dst,vint16mf2_t vector,vint32m1_t scalar,size_t vl)460 vint32m1_t test_vwredsum_vs_i16mf2_i32m1_m(vbool32_t mask, vint32m1_t dst,
461 vint16mf2_t vector,
462 vint32m1_t scalar, size_t vl) {
463 return vwredsum_vs_i16mf2_i32m1_m(mask, dst, vector, scalar, vl);
464 }
465
466 // CHECK-RV64-LABEL: @test_vwredsum_vs_i16m1_i32m1_m(
467 // CHECK-RV64-NEXT: entry:
468 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv4i16.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 4 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
469 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
470 //
test_vwredsum_vs_i16m1_i32m1_m(vbool16_t mask,vint32m1_t dst,vint16m1_t vector,vint32m1_t scalar,size_t vl)471 vint32m1_t test_vwredsum_vs_i16m1_i32m1_m(vbool16_t mask, vint32m1_t dst,
472 vint16m1_t vector, vint32m1_t scalar,
473 size_t vl) {
474 return vwredsum_vs_i16m1_i32m1_m(mask, dst, vector, scalar, vl);
475 }
476
477 // CHECK-RV64-LABEL: @test_vwredsum_vs_i16m2_i32m1_m(
478 // CHECK-RV64-NEXT: entry:
479 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv8i16.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 8 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
480 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
481 //
test_vwredsum_vs_i16m2_i32m1_m(vbool8_t mask,vint32m1_t dst,vint16m2_t vector,vint32m1_t scalar,size_t vl)482 vint32m1_t test_vwredsum_vs_i16m2_i32m1_m(vbool8_t mask, vint32m1_t dst,
483 vint16m2_t vector, vint32m1_t scalar,
484 size_t vl) {
485 return vwredsum_vs_i16m2_i32m1_m(mask, dst, vector, scalar, vl);
486 }
487
488 // CHECK-RV64-LABEL: @test_vwredsum_vs_i16m4_i32m1_m(
489 // CHECK-RV64-NEXT: entry:
490 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv16i16.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 16 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
491 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
492 //
test_vwredsum_vs_i16m4_i32m1_m(vbool4_t mask,vint32m1_t dst,vint16m4_t vector,vint32m1_t scalar,size_t vl)493 vint32m1_t test_vwredsum_vs_i16m4_i32m1_m(vbool4_t mask, vint32m1_t dst,
494 vint16m4_t vector, vint32m1_t scalar,
495 size_t vl) {
496 return vwredsum_vs_i16m4_i32m1_m(mask, dst, vector, scalar, vl);
497 }
498
499 // CHECK-RV64-LABEL: @test_vwredsum_vs_i16m8_i32m1_m(
500 // CHECK-RV64-NEXT: entry:
501 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv32i16.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 32 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
502 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
503 //
test_vwredsum_vs_i16m8_i32m1_m(vbool2_t mask,vint32m1_t dst,vint16m8_t vector,vint32m1_t scalar,size_t vl)504 vint32m1_t test_vwredsum_vs_i16m8_i32m1_m(vbool2_t mask, vint32m1_t dst,
505 vint16m8_t vector, vint32m1_t scalar,
506 size_t vl) {
507 return vwredsum_vs_i16m8_i32m1_m(mask, dst, vector, scalar, vl);
508 }
509
510 // CHECK-RV64-LABEL: @test_vwredsum_vs_i32mf2_i64m1_m(
511 // CHECK-RV64-NEXT: entry:
512 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
513 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
514 //
test_vwredsum_vs_i32mf2_i64m1_m(vbool64_t mask,vint64m1_t dst,vint32mf2_t vector,vint64m1_t scalar,size_t vl)515 vint64m1_t test_vwredsum_vs_i32mf2_i64m1_m(vbool64_t mask, vint64m1_t dst,
516 vint32mf2_t vector,
517 vint64m1_t scalar, size_t vl) {
518 return vwredsum_vs_i32mf2_i64m1_m(mask, dst, vector, scalar, vl);
519 }
520
521 // CHECK-RV64-LABEL: @test_vwredsum_vs_i32m1_i64m1_m(
522 // CHECK-RV64-NEXT: entry:
523 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv2i32.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 2 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
524 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
525 //
test_vwredsum_vs_i32m1_i64m1_m(vbool32_t mask,vint64m1_t dst,vint32m1_t vector,vint64m1_t scalar,size_t vl)526 vint64m1_t test_vwredsum_vs_i32m1_i64m1_m(vbool32_t mask, vint64m1_t dst,
527 vint32m1_t vector, vint64m1_t scalar,
528 size_t vl) {
529 return vwredsum_vs_i32m1_i64m1_m(mask, dst, vector, scalar, vl);
530 }
531
532 // CHECK-RV64-LABEL: @test_vwredsum_vs_i32m2_i64m1_m(
533 // CHECK-RV64-NEXT: entry:
534 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv4i32.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 4 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
535 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
536 //
test_vwredsum_vs_i32m2_i64m1_m(vbool16_t mask,vint64m1_t dst,vint32m2_t vector,vint64m1_t scalar,size_t vl)537 vint64m1_t test_vwredsum_vs_i32m2_i64m1_m(vbool16_t mask, vint64m1_t dst,
538 vint32m2_t vector, vint64m1_t scalar,
539 size_t vl) {
540 return vwredsum_vs_i32m2_i64m1_m(mask, dst, vector, scalar, vl);
541 }
542
543 // CHECK-RV64-LABEL: @test_vwredsum_vs_i32m4_i64m1_m(
544 // CHECK-RV64-NEXT: entry:
545 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv8i32.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 8 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
546 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
547 //
test_vwredsum_vs_i32m4_i64m1_m(vbool8_t mask,vint64m1_t dst,vint32m4_t vector,vint64m1_t scalar,size_t vl)548 vint64m1_t test_vwredsum_vs_i32m4_i64m1_m(vbool8_t mask, vint64m1_t dst,
549 vint32m4_t vector, vint64m1_t scalar,
550 size_t vl) {
551 return vwredsum_vs_i32m4_i64m1_m(mask, dst, vector, scalar, vl);
552 }
553
554 // CHECK-RV64-LABEL: @test_vwredsum_vs_i32m8_i64m1_m(
555 // CHECK-RV64-NEXT: entry:
556 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv16i32.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 16 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
557 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
558 //
test_vwredsum_vs_i32m8_i64m1_m(vbool4_t mask,vint64m1_t dst,vint32m8_t vector,vint64m1_t scalar,size_t vl)559 vint64m1_t test_vwredsum_vs_i32m8_i64m1_m(vbool4_t mask, vint64m1_t dst,
560 vint32m8_t vector, vint64m1_t scalar,
561 size_t vl) {
562 return vwredsum_vs_i32m8_i64m1_m(mask, dst, vector, scalar, vl);
563 }
564
565 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u8mf8_u16m1_m(
566 // CHECK-RV64-NEXT: entry:
567 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv1i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 1 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
568 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
569 //
test_vwredsumu_vs_u8mf8_u16m1_m(vbool64_t mask,vuint16m1_t dst,vuint8mf8_t vector,vuint16m1_t scalar,size_t vl)570 vuint16m1_t test_vwredsumu_vs_u8mf8_u16m1_m(vbool64_t mask, vuint16m1_t dst,
571 vuint8mf8_t vector,
572 vuint16m1_t scalar, size_t vl) {
573 return vwredsumu_vs_u8mf8_u16m1_m(mask, dst, vector, scalar, vl);
574 }
575
576 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u8mf4_u16m1_m(
577 // CHECK-RV64-NEXT: entry:
578 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv2i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 2 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
579 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
580 //
test_vwredsumu_vs_u8mf4_u16m1_m(vbool32_t mask,vuint16m1_t dst,vuint8mf4_t vector,vuint16m1_t scalar,size_t vl)581 vuint16m1_t test_vwredsumu_vs_u8mf4_u16m1_m(vbool32_t mask, vuint16m1_t dst,
582 vuint8mf4_t vector,
583 vuint16m1_t scalar, size_t vl) {
584 return vwredsumu_vs_u8mf4_u16m1_m(mask, dst, vector, scalar, vl);
585 }
586
587 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u8mf2_u16m1_m(
588 // CHECK-RV64-NEXT: entry:
589 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 4 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
590 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
591 //
test_vwredsumu_vs_u8mf2_u16m1_m(vbool16_t mask,vuint16m1_t dst,vuint8mf2_t vector,vuint16m1_t scalar,size_t vl)592 vuint16m1_t test_vwredsumu_vs_u8mf2_u16m1_m(vbool16_t mask, vuint16m1_t dst,
593 vuint8mf2_t vector,
594 vuint16m1_t scalar, size_t vl) {
595 return vwredsumu_vs_u8mf2_u16m1_m(mask, dst, vector, scalar, vl);
596 }
597
598 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u8m1_u16m1_m(
599 // CHECK-RV64-NEXT: entry:
600 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv8i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 8 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
601 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
602 //
test_vwredsumu_vs_u8m1_u16m1_m(vbool8_t mask,vuint16m1_t dst,vuint8m1_t vector,vuint16m1_t scalar,size_t vl)603 vuint16m1_t test_vwredsumu_vs_u8m1_u16m1_m(vbool8_t mask, vuint16m1_t dst,
604 vuint8m1_t vector,
605 vuint16m1_t scalar, size_t vl) {
606 return vwredsumu_vs_u8m1_u16m1_m(mask, dst, vector, scalar, vl);
607 }
608
609 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u8m2_u16m1_m(
610 // CHECK-RV64-NEXT: entry:
611 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv16i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 16 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
612 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
613 //
test_vwredsumu_vs_u8m2_u16m1_m(vbool4_t mask,vuint16m1_t dst,vuint8m2_t vector,vuint16m1_t scalar,size_t vl)614 vuint16m1_t test_vwredsumu_vs_u8m2_u16m1_m(vbool4_t mask, vuint16m1_t dst,
615 vuint8m2_t vector,
616 vuint16m1_t scalar, size_t vl) {
617 return vwredsumu_vs_u8m2_u16m1_m(mask, dst, vector, scalar, vl);
618 }
619
620 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u8m4_u16m1_m(
621 // CHECK-RV64-NEXT: entry:
622 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv32i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 32 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
623 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
624 //
test_vwredsumu_vs_u8m4_u16m1_m(vbool2_t mask,vuint16m1_t dst,vuint8m4_t vector,vuint16m1_t scalar,size_t vl)625 vuint16m1_t test_vwredsumu_vs_u8m4_u16m1_m(vbool2_t mask, vuint16m1_t dst,
626 vuint8m4_t vector,
627 vuint16m1_t scalar, size_t vl) {
628 return vwredsumu_vs_u8m4_u16m1_m(mask, dst, vector, scalar, vl);
629 }
630
631 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u8m8_u16m1_m(
632 // CHECK-RV64-NEXT: entry:
633 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv64i8.i64(<vscale x 4 x i16> [[DST:%.*]], <vscale x 64 x i8> [[VECTOR:%.*]], <vscale x 4 x i16> [[SCALAR:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
634 // CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
635 //
test_vwredsumu_vs_u8m8_u16m1_m(vbool1_t mask,vuint16m1_t dst,vuint8m8_t vector,vuint16m1_t scalar,size_t vl)636 vuint16m1_t test_vwredsumu_vs_u8m8_u16m1_m(vbool1_t mask, vuint16m1_t dst,
637 vuint8m8_t vector,
638 vuint16m1_t scalar, size_t vl) {
639 return vwredsumu_vs_u8m8_u16m1_m(mask, dst, vector, scalar, vl);
640 }
641
642 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u16mf4_u32m1_m(
643 // CHECK-RV64-NEXT: entry:
644 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv1i16.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 1 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
645 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
646 //
test_vwredsumu_vs_u16mf4_u32m1_m(vbool64_t mask,vuint32m1_t dst,vuint16mf4_t vector,vuint32m1_t scalar,size_t vl)647 vuint32m1_t test_vwredsumu_vs_u16mf4_u32m1_m(vbool64_t mask, vuint32m1_t dst,
648 vuint16mf4_t vector,
649 vuint32m1_t scalar, size_t vl) {
650 return vwredsumu_vs_u16mf4_u32m1_m(mask, dst, vector, scalar, vl);
651 }
652
653 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u16mf2_u32m1_m(
654 // CHECK-RV64-NEXT: entry:
655 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 2 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
656 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
657 //
test_vwredsumu_vs_u16mf2_u32m1_m(vbool32_t mask,vuint32m1_t dst,vuint16mf2_t vector,vuint32m1_t scalar,size_t vl)658 vuint32m1_t test_vwredsumu_vs_u16mf2_u32m1_m(vbool32_t mask, vuint32m1_t dst,
659 vuint16mf2_t vector,
660 vuint32m1_t scalar, size_t vl) {
661 return vwredsumu_vs_u16mf2_u32m1_m(mask, dst, vector, scalar, vl);
662 }
663
664 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u16m1_u32m1_m(
665 // CHECK-RV64-NEXT: entry:
666 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv4i16.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 4 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
667 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
668 //
test_vwredsumu_vs_u16m1_u32m1_m(vbool16_t mask,vuint32m1_t dst,vuint16m1_t vector,vuint32m1_t scalar,size_t vl)669 vuint32m1_t test_vwredsumu_vs_u16m1_u32m1_m(vbool16_t mask, vuint32m1_t dst,
670 vuint16m1_t vector,
671 vuint32m1_t scalar, size_t vl) {
672 return vwredsumu_vs_u16m1_u32m1_m(mask, dst, vector, scalar, vl);
673 }
674
675 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u16m2_u32m1_m(
676 // CHECK-RV64-NEXT: entry:
677 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv8i16.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 8 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
678 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
679 //
test_vwredsumu_vs_u16m2_u32m1_m(vbool8_t mask,vuint32m1_t dst,vuint16m2_t vector,vuint32m1_t scalar,size_t vl)680 vuint32m1_t test_vwredsumu_vs_u16m2_u32m1_m(vbool8_t mask, vuint32m1_t dst,
681 vuint16m2_t vector,
682 vuint32m1_t scalar, size_t vl) {
683 return vwredsumu_vs_u16m2_u32m1_m(mask, dst, vector, scalar, vl);
684 }
685
686 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u16m4_u32m1_m(
687 // CHECK-RV64-NEXT: entry:
688 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv16i16.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 16 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
689 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
690 //
test_vwredsumu_vs_u16m4_u32m1_m(vbool4_t mask,vuint32m1_t dst,vuint16m4_t vector,vuint32m1_t scalar,size_t vl)691 vuint32m1_t test_vwredsumu_vs_u16m4_u32m1_m(vbool4_t mask, vuint32m1_t dst,
692 vuint16m4_t vector,
693 vuint32m1_t scalar, size_t vl) {
694 return vwredsumu_vs_u16m4_u32m1_m(mask, dst, vector, scalar, vl);
695 }
696
697 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u16m8_u32m1_m(
698 // CHECK-RV64-NEXT: entry:
699 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv32i16.i64(<vscale x 2 x i32> [[DST:%.*]], <vscale x 32 x i16> [[VECTOR:%.*]], <vscale x 2 x i32> [[SCALAR:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
700 // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
701 //
test_vwredsumu_vs_u16m8_u32m1_m(vbool2_t mask,vuint32m1_t dst,vuint16m8_t vector,vuint32m1_t scalar,size_t vl)702 vuint32m1_t test_vwredsumu_vs_u16m8_u32m1_m(vbool2_t mask, vuint32m1_t dst,
703 vuint16m8_t vector,
704 vuint32m1_t scalar, size_t vl) {
705 return vwredsumu_vs_u16m8_u32m1_m(mask, dst, vector, scalar, vl);
706 }
707
708 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u32mf2_u64m1_m(
709 // CHECK-RV64-NEXT: entry:
710 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 1 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
711 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
712 //
test_vwredsumu_vs_u32mf2_u64m1_m(vbool64_t mask,vuint64m1_t dst,vuint32mf2_t vector,vuint64m1_t scalar,size_t vl)713 vuint64m1_t test_vwredsumu_vs_u32mf2_u64m1_m(vbool64_t mask, vuint64m1_t dst,
714 vuint32mf2_t vector,
715 vuint64m1_t scalar, size_t vl) {
716 return vwredsumu_vs_u32mf2_u64m1_m(mask, dst, vector, scalar, vl);
717 }
718
719 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u32m1_u64m1_m(
720 // CHECK-RV64-NEXT: entry:
721 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv2i32.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 2 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
722 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
723 //
test_vwredsumu_vs_u32m1_u64m1_m(vbool32_t mask,vuint64m1_t dst,vuint32m1_t vector,vuint64m1_t scalar,size_t vl)724 vuint64m1_t test_vwredsumu_vs_u32m1_u64m1_m(vbool32_t mask, vuint64m1_t dst,
725 vuint32m1_t vector,
726 vuint64m1_t scalar, size_t vl) {
727 return vwredsumu_vs_u32m1_u64m1_m(mask, dst, vector, scalar, vl);
728 }
729
730 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u32m2_u64m1_m(
731 // CHECK-RV64-NEXT: entry:
732 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv4i32.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 4 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
733 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
734 //
test_vwredsumu_vs_u32m2_u64m1_m(vbool16_t mask,vuint64m1_t dst,vuint32m2_t vector,vuint64m1_t scalar,size_t vl)735 vuint64m1_t test_vwredsumu_vs_u32m2_u64m1_m(vbool16_t mask, vuint64m1_t dst,
736 vuint32m2_t vector,
737 vuint64m1_t scalar, size_t vl) {
738 return vwredsumu_vs_u32m2_u64m1_m(mask, dst, vector, scalar, vl);
739 }
740
741 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u32m4_u64m1_m(
742 // CHECK-RV64-NEXT: entry:
743 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv8i32.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 8 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
744 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
745 //
test_vwredsumu_vs_u32m4_u64m1_m(vbool8_t mask,vuint64m1_t dst,vuint32m4_t vector,vuint64m1_t scalar,size_t vl)746 vuint64m1_t test_vwredsumu_vs_u32m4_u64m1_m(vbool8_t mask, vuint64m1_t dst,
747 vuint32m4_t vector,
748 vuint64m1_t scalar, size_t vl) {
749 return vwredsumu_vs_u32m4_u64m1_m(mask, dst, vector, scalar, vl);
750 }
751
752 // CHECK-RV64-LABEL: @test_vwredsumu_vs_u32m8_u64m1_m(
753 // CHECK-RV64-NEXT: entry:
754 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv16i32.i64(<vscale x 1 x i64> [[DST:%.*]], <vscale x 16 x i32> [[VECTOR:%.*]], <vscale x 1 x i64> [[SCALAR:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
755 // CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
756 //
test_vwredsumu_vs_u32m8_u64m1_m(vbool4_t mask,vuint64m1_t dst,vuint32m8_t vector,vuint64m1_t scalar,size_t vl)757 vuint64m1_t test_vwredsumu_vs_u32m8_u64m1_m(vbool4_t mask, vuint64m1_t dst,
758 vuint32m8_t vector,
759 vuint64m1_t scalar, size_t vl) {
760 return vwredsumu_vs_u32m8_u64m1_m(mask, dst, vector, scalar, vl);
761 }
762