1 //===-- llvm/CodeGen/MachineCombinerPattern.h - Instruction pattern supported by 2 // combiner ------*- C++ -*-===// 3 // 4 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 5 // See https://llvm.org/LICENSE.txt for license information. 6 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines instruction pattern supported by combiner 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_MACHINECOMBINERPATTERN_H 15 #define LLVM_CODEGEN_MACHINECOMBINERPATTERN_H 16 17 namespace llvm { 18 19 /// These are instruction patterns matched by the machine combiner pass. 20 enum class MachineCombinerPattern { 21 // These are commutative variants for reassociating a computation chain. See 22 // the comments before getMachineCombinerPatterns() in TargetInstrInfo.cpp. 23 REASSOC_AX_BY, 24 REASSOC_AX_YB, 25 REASSOC_XA_BY, 26 REASSOC_XA_YB, 27 28 // These are patterns matched by the PowerPC to reassociate FMA chains. 29 REASSOC_XY_AMM_BMM, 30 REASSOC_XMM_AMM_BMM, 31 32 // These are patterns matched by the PowerPC to reassociate FMA and FSUB to 33 // reduce register pressure. 34 REASSOC_XY_BCA, 35 REASSOC_XY_BAC, 36 37 // These are multiply-add patterns matched by the AArch64 machine combiner. 38 MULADDW_OP1, 39 MULADDW_OP2, 40 MULSUBW_OP1, 41 MULSUBW_OP2, 42 MULADDWI_OP1, 43 MULSUBWI_OP1, 44 MULADDX_OP1, 45 MULADDX_OP2, 46 MULSUBX_OP1, 47 MULSUBX_OP2, 48 MULADDXI_OP1, 49 MULSUBXI_OP1, 50 // NEON integers vectors 51 MULADDv8i8_OP1, 52 MULADDv8i8_OP2, 53 MULADDv16i8_OP1, 54 MULADDv16i8_OP2, 55 MULADDv4i16_OP1, 56 MULADDv4i16_OP2, 57 MULADDv8i16_OP1, 58 MULADDv8i16_OP2, 59 MULADDv2i32_OP1, 60 MULADDv2i32_OP2, 61 MULADDv4i32_OP1, 62 MULADDv4i32_OP2, 63 64 MULSUBv8i8_OP1, 65 MULSUBv8i8_OP2, 66 MULSUBv16i8_OP1, 67 MULSUBv16i8_OP2, 68 MULSUBv4i16_OP1, 69 MULSUBv4i16_OP2, 70 MULSUBv8i16_OP1, 71 MULSUBv8i16_OP2, 72 MULSUBv2i32_OP1, 73 MULSUBv2i32_OP2, 74 MULSUBv4i32_OP1, 75 MULSUBv4i32_OP2, 76 77 MULADDv4i16_indexed_OP1, 78 MULADDv4i16_indexed_OP2, 79 MULADDv8i16_indexed_OP1, 80 MULADDv8i16_indexed_OP2, 81 MULADDv2i32_indexed_OP1, 82 MULADDv2i32_indexed_OP2, 83 MULADDv4i32_indexed_OP1, 84 MULADDv4i32_indexed_OP2, 85 86 MULSUBv4i16_indexed_OP1, 87 MULSUBv4i16_indexed_OP2, 88 MULSUBv8i16_indexed_OP1, 89 MULSUBv8i16_indexed_OP2, 90 MULSUBv2i32_indexed_OP1, 91 MULSUBv2i32_indexed_OP2, 92 MULSUBv4i32_indexed_OP1, 93 MULSUBv4i32_indexed_OP2, 94 95 // Floating Point 96 FMULADDH_OP1, 97 FMULADDH_OP2, 98 FMULSUBH_OP1, 99 FMULSUBH_OP2, 100 FMULADDS_OP1, 101 FMULADDS_OP2, 102 FMULSUBS_OP1, 103 FMULSUBS_OP2, 104 FMULADDD_OP1, 105 FMULADDD_OP2, 106 FMULSUBD_OP1, 107 FMULSUBD_OP2, 108 FNMULSUBH_OP1, 109 FNMULSUBS_OP1, 110 FNMULSUBD_OP1, 111 FMLAv1i32_indexed_OP1, 112 FMLAv1i32_indexed_OP2, 113 FMLAv1i64_indexed_OP1, 114 FMLAv1i64_indexed_OP2, 115 FMLAv4f16_OP1, 116 FMLAv4f16_OP2, 117 FMLAv8f16_OP1, 118 FMLAv8f16_OP2, 119 FMLAv2f32_OP2, 120 FMLAv2f32_OP1, 121 FMLAv2f64_OP1, 122 FMLAv2f64_OP2, 123 FMLAv4i16_indexed_OP1, 124 FMLAv4i16_indexed_OP2, 125 FMLAv8i16_indexed_OP1, 126 FMLAv8i16_indexed_OP2, 127 FMLAv2i32_indexed_OP1, 128 FMLAv2i32_indexed_OP2, 129 FMLAv2i64_indexed_OP1, 130 FMLAv2i64_indexed_OP2, 131 FMLAv4f32_OP1, 132 FMLAv4f32_OP2, 133 FMLAv4i32_indexed_OP1, 134 FMLAv4i32_indexed_OP2, 135 FMLSv1i32_indexed_OP2, 136 FMLSv1i64_indexed_OP2, 137 FMLSv4f16_OP1, 138 FMLSv4f16_OP2, 139 FMLSv8f16_OP1, 140 FMLSv8f16_OP2, 141 FMLSv2f32_OP1, 142 FMLSv2f32_OP2, 143 FMLSv2f64_OP1, 144 FMLSv2f64_OP2, 145 FMLSv4i16_indexed_OP1, 146 FMLSv4i16_indexed_OP2, 147 FMLSv8i16_indexed_OP1, 148 FMLSv8i16_indexed_OP2, 149 FMLSv2i32_indexed_OP1, 150 FMLSv2i32_indexed_OP2, 151 FMLSv2i64_indexed_OP1, 152 FMLSv2i64_indexed_OP2, 153 FMLSv4f32_OP1, 154 FMLSv4f32_OP2, 155 FMLSv4i32_indexed_OP1, 156 FMLSv4i32_indexed_OP2 157 }; 158 159 } // end namespace llvm 160 161 #endif 162