1//==- AArch64SchedKryo.td - Qualcomm Kryo Scheduling Defs ---*- tablegen -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the machine model for Qualcomm Kryo to support
10// instruction scheduling and other instruction cost heuristics.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// The issue width is set to five, matching the five issue queues for expanded
16// uops. Now, the latency spreadsheet has information based on fragmented uops,
17// but these do not actually take up an issue queue.
18
19def KryoModel : SchedMachineModel {
20  let IssueWidth        =   5; // 5-wide issue for expanded uops
21  let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer
22  let LoadLatency       =   4; // Optimistic load latency
23  let MispredictPenalty =  14; // Fetch + Decode/Rename/Dispatch + Branch
24
25  // Enable partial & runtime unrolling. The magic number is chosen based on
26  // experiments and benchmarking data.
27  let LoopMicroOpBufferSize = 16;
28  let CompleteModel = 1;
29
30  list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
31                                                    PAUnsupported.F,
32                                                    SMEUnsupported.F);
33  // FIXME: Remove when all errors have been fixed.
34  let FullInstRWOverlapCheck = 0;
35}
36
37//===----------------------------------------------------------------------===//
38// Define each kind of processor resource and number available on Kryo.
39
40let SchedModel = KryoModel in {
41  def KryoUnitXA : ProcResource<1>;                   // Type X(A) micro-ops
42  def KryoUnitXB : ProcResource<1>;                   // Type X(B) micro-ops
43  def KryoUnitYA : ProcResource<1>;                   // Type Y(A) micro-ops
44  def KryoUnitYB : ProcResource<1>;                   // Type Y(B) micro-ops
45  def KryoUnitX : ProcResGroup<[KryoUnitXA,          // Type X micro-ops
46                                KryoUnitXB]>;
47  def KryoUnitY : ProcResGroup<[KryoUnitYA,          // Type Y micro-ops
48                                KryoUnitYB]>;
49  def KryoUnitXY : ProcResGroup<[KryoUnitXA,         // Type XY micro-ops
50                                 KryoUnitXB,
51                                 KryoUnitYA,
52                                 KryoUnitYB]>;
53  def KryoUnitLSA : ProcResource<1>;                  // Type LS(A) micro-ops
54  def KryoUnitLSB : ProcResource<1>;                  // Type LS(B) micro-ops
55  def KryoUnitLS : ProcResGroup<[KryoUnitLSA,        // Type LS micro-ops
56                                 KryoUnitLSB]>;
57}
58
59let SchedModel = KryoModel in {
60
61//===----------------------------------------------------------------------===//
62// Map the target-defined scheduler read/write resources and latency for
63// Kryo.
64
65def : WriteRes<WriteImm,   [KryoUnitXY]> { let Latency = 1; }
66def : WriteRes<WriteI,     [KryoUnitXY]> { let Latency = 1; }
67def : WriteRes<WriteISReg, [KryoUnitXY, KryoUnitXY]>
68      { let Latency = 2; let NumMicroOps = 2; }
69def : WriteRes<WriteIEReg, [KryoUnitXY, KryoUnitXY]>
70      { let Latency = 2; let NumMicroOps = 2; }
71def : WriteRes<WriteExtr,  [KryoUnitXY, KryoUnitX]>
72      { let Latency = 2; let NumMicroOps = 2; }
73def : WriteRes<WriteIS,    [KryoUnitXY]> { let Latency = 2; }
74def : WriteRes<WriteID32,  [KryoUnitXA, KryoUnitY]>
75      { let Latency = 8; let NumMicroOps = 1; } // Fragent -1
76def : WriteRes<WriteID64,  [KryoUnitXA, KryoUnitY]>
77      { let Latency = 8; let NumMicroOps = 1; } // Fragent -1
78def : WriteRes<WriteIM32,  [KryoUnitX]> { let Latency = 5; }
79def : WriteRes<WriteIM64,  [KryoUnitX]> { let Latency = 5; }
80def : WriteRes<WriteBr,    [KryoUnitXY]> { let Latency = 1; }
81def : WriteRes<WriteBrReg, [KryoUnitXY]> { let Latency = 1; }
82def : WriteRes<WriteLD,    [KryoUnitLS]> { let Latency = 4; }
83def : WriteRes<WriteST,    [KryoUnitLS]> { let Latency = 4; }
84def : WriteRes<WriteSTP,   [KryoUnitLS]> { let Latency = 4; }
85def : WriteRes<WriteAdr,   [KryoUnitXY]> { let Latency = 6; }
86def : WriteRes<WriteLDIdx, [KryoUnitLS]> { let Latency = 4; }
87def : WriteRes<WriteSTIdx, [KryoUnitLS]> { let Latency = 4; }
88def : WriteRes<WriteF,     [KryoUnitXY, KryoUnitXY]>
89      { let Latency = 3; let NumMicroOps = 2; }
90def : WriteRes<WriteFCmp,  [KryoUnitXY]> { let Latency = 2; }
91def : WriteRes<WriteFCvt,  [KryoUnitX]> { let Latency = 4; }
92def : WriteRes<WriteFCopy, [KryoUnitXY]> { let Latency = 6; }
93def : WriteRes<WriteFImm,  [KryoUnitXY]> { let Latency = 6; }
94def : WriteRes<WriteFMul,  [KryoUnitX, KryoUnitX]>
95      { let Latency = 6; let NumMicroOps = 2; }
96def : WriteRes<WriteFDiv,  [KryoUnitXA, KryoUnitY]>
97      { let Latency = 12; let NumMicroOps = 2; } // Fragent -1 / NoRSV +1
98def : WriteRes<WriteVd,    [KryoUnitXY]> { let Latency = 6; }
99def : WriteRes<WriteVq,    [KryoUnitXY]> { let Latency = 6; }
100def : WriteRes<WriteVLD,   [KryoUnitLS]> { let Latency = 4; }
101def : WriteRes<WriteVST,   [KryoUnitLS]> { let Latency = 4; }
102
103def : WriteRes<WriteSys,     []> { let Latency = 1; }
104def : WriteRes<WriteBarrier, []> { let Latency = 1; }
105def : WriteRes<WriteHint,    []> { let Latency = 1; }
106
107def : WriteRes<WriteLDHi,    []> { let Latency = 4; }
108
109def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
110
111// No forwarding logic is modelled yet.
112def : ReadAdvance<ReadI,       0>;
113def : ReadAdvance<ReadISReg,   0>;
114def : ReadAdvance<ReadIEReg,   0>;
115def : ReadAdvance<ReadIM,      0>;
116def : ReadAdvance<ReadIMA,     0>;
117def : ReadAdvance<ReadID,      0>;
118def : ReadAdvance<ReadExtrHi,  0>;
119def : ReadAdvance<ReadAdrBase, 0>;
120def : ReadAdvance<ReadVLD,     0>;
121def : ReadAdvance<ReadST,      0>;
122
123
124//===----------------------------------------------------------------------===//
125// Specialize the coarse model by associating instruction groups with the
126// subtarget-defined types. As the modeled is refined, this will override most
127// of the above SchedWriteRes and SchedAlias mappings.
128
129// Miscellaneous
130// -----------------------------------------------------------------------------
131
132def : InstRW<[WriteI], (instrs COPY)>;
133
134
135// Detailed Refinedments
136// -----------------------------------------------------------------------------
137include "AArch64SchedKryoDetails.td"
138
139
140} // SchedModel = KryoModel
141