1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -stop-after=legalizer -o - %s | FileCheck %s 3 4; Make sure legalizer info doesn't assert on dummy targets 5 6define i16 @vop3p_add_i16(i16 %arg0) #0 { 7 ; CHECK-LABEL: name: vop3p_add_i16 8 ; CHECK: bb.1 (%ir-block.0): 9 ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 10 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 11 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 12 ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 13 ; CHECK: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[TRUNC]] 14 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s16) 15 ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32) 16 ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]] 17 ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0 18 %add = add i16 %arg0, %arg0 19 ret i16 %add 20} 21 22define <2 x i16> @vop3p_add_v2i16(<2 x i16> %arg0) #0 { 23 ; CHECK-LABEL: name: vop3p_add_v2i16 24 ; CHECK: bb.1 (%ir-block.0): 25 ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 26 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 27 ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 28 ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) 29 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32) 30 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 31 ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) 32 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) 33 ; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) 34 ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32) 35 ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) 36 ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32) 37 ; CHECK: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[TRUNC2]] 38 ; CHECK: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[TRUNC1]], [[TRUNC3]] 39 ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ADD]](s16) 40 ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ADD1]](s16) 41 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32) 42 ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]] 43 ; CHECK: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) 44 ; CHECK: $vgpr0 = COPY [[BITCAST2]](<2 x s16>) 45 ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]] 46 ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0 47 %add = add <2 x i16> %arg0, %arg0 48 ret <2 x i16> %add 49} 50 51define i16 @halfinsts_add_i16(i16 %arg0) #1 { 52 ; CHECK-LABEL: name: halfinsts_add_i16 53 ; CHECK: bb.1 (%ir-block.0): 54 ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 55 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 56 ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 57 ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]] 58 ; CHECK: $vgpr0 = COPY [[ADD]](s32) 59 ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]] 60 ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0 61 %add = add i16 %arg0, %arg0 62 ret i16 %add 63} 64 65define <2 x i16> @halfinsts_add_v2i16(<2 x i16> %arg0) #1 { 66 ; CHECK-LABEL: name: halfinsts_add_v2i16 67 ; CHECK: bb.1 (%ir-block.0): 68 ; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31 69 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 70 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 71 ; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 72 ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]] 73 ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY1]] 74 ; CHECK: $vgpr0 = COPY [[ADD]](s32) 75 ; CHECK: $vgpr1 = COPY [[ADD1]](s32) 76 ; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]] 77 ; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0, implicit $vgpr1 78 %add = add <2 x i16> %arg0, %arg0 79 ret <2 x i16> %add 80} 81 82attributes #0 = { "target-features"="+vop3p" } 83attributes #0 = { "target-features"="+16-bit-insts" } 84