1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o -  | FileCheck -check-prefix=GCN %s
3
4---
5name: fmed3_s32_vvvv
6legalized: true
7regBankSelected: true
8tracksRegLiveness: true
9
10body: |
11  bb.0:
12    liveins: $vgpr0, $vgpr1, $vgpr2
13
14    ; GCN-LABEL: name: fmed3_s32_vvvv
15    ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
16    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
17    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
18    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
19    ; GCN: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
20    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
21    %0:vgpr(s32) = COPY $vgpr0
22    %1:vgpr(s32) = COPY $vgpr1
23    %2:vgpr(s32) = COPY $vgpr2
24    %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2
25    S_ENDPGM 0, implicit %3
26...
27
28---
29name: fmed3_s32_vsvv
30legalized: true
31regBankSelected: true
32tracksRegLiveness: true
33
34body: |
35  bb.0:
36    liveins: $sgpr0, $vgpr0, $vgpr1
37
38    ; GCN-LABEL: name: fmed3_s32_vsvv
39    ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
40    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
41    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
42    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
43    ; GCN: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
44    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
45    %0:sgpr(s32) = COPY $sgpr0
46    %1:vgpr(s32) = COPY $vgpr0
47    %2:vgpr(s32) = COPY $vgpr1
48    %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2
49    S_ENDPGM 0, implicit %3
50...
51
52---
53name: fmed3_s32_vvsv
54legalized: true
55regBankSelected: true
56tracksRegLiveness: true
57
58body: |
59  bb.0:
60    liveins: $sgpr0, $vgpr0, $vgpr1
61
62    ; GCN-LABEL: name: fmed3_s32_vvsv
63    ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
64    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
65    ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
66    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
67    ; GCN: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
68    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
69    %0:vgpr(s32) = COPY $vgpr0
70    %1:sgpr(s32) = COPY $sgpr0
71    %2:vgpr(s32) = COPY $vgpr1
72    %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2
73    S_ENDPGM 0, implicit %3
74...
75
76---
77name: fmed3_s32_vvvs
78legalized: true
79regBankSelected: true
80tracksRegLiveness: true
81
82body: |
83  bb.0:
84    liveins: $sgpr0, $vgpr0, $vgpr1
85
86    ; GCN-LABEL: name: fmed3_s32_vvvs
87    ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
88    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
89    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
90    ; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0
91    ; GCN: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
92    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
93    %0:vgpr(s32) = COPY $vgpr0
94    %1:vgpr(s32) = COPY $vgpr0
95    %2:sgpr(s32) = COPY $sgpr0
96    %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2
97    S_ENDPGM 0, implicit %3
98...
99
100
101# Same SGPR used, so doesn't violate the constant bus restriction.
102---
103name: fmed3_s32_vssv
104legalized: true
105regBankSelected: true
106tracksRegLiveness: true
107
108body: |
109  bb.0:
110    liveins: $sgpr0, $vgpr0
111
112    ; GCN-LABEL: name: fmed3_s32_vssv
113    ; GCN: liveins: $sgpr0, $vgpr0
114    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
115    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
116    ; GCN: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
117    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
118    %0:sgpr(s32) = COPY $sgpr0
119    %1:vgpr(s32) = COPY $vgpr0
120    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %0, %1
121    S_ENDPGM 0, implicit %2
122...
123
124---
125name: fmed3_s32_vsvs
126legalized: true
127regBankSelected: true
128tracksRegLiveness: true
129
130body: |
131  bb.0:
132    liveins: $sgpr0, $vgpr0
133
134    ; GCN-LABEL: name: fmed3_s32_vsvs
135    ; GCN: liveins: $sgpr0, $vgpr0
136    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
137    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
138    ; GCN: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
139    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
140    %0:sgpr(s32) = COPY $sgpr0
141    %1:vgpr(s32) = COPY $vgpr0
142    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %0
143    S_ENDPGM 0, implicit %2
144...
145
146---
147name: fmed3_s32_vvss
148legalized: true
149regBankSelected: true
150tracksRegLiveness: true
151
152body: |
153  bb.0:
154    liveins: $sgpr0, $vgpr0
155
156    ; GCN-LABEL: name: fmed3_s32_vvss
157    ; GCN: liveins: $sgpr0, $vgpr0
158    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
159    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
160    ; GCN: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
161    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
162    %0:sgpr(s32) = COPY $sgpr0
163    %1:vgpr(s32) = COPY $vgpr0
164    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %1, %0, %0
165    S_ENDPGM 0, implicit %2
166...
167
168---
169name: fmed3_s32_vsss
170legalized: true
171regBankSelected: true
172tracksRegLiveness: true
173
174body: |
175  bb.0:
176    liveins: $sgpr0, $vgpr0
177
178    ; GCN-LABEL: name: fmed3_s32_vsss
179    ; GCN: liveins: $sgpr0, $vgpr0
180    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
181    ; GCN: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
182    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
183    %0:sgpr(s32) = COPY $sgpr0
184    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %0, %0
185    S_ENDPGM 0, implicit %1
186...
187
188
189# FIXME: This should probably have been fixed by RegBankSelect, but we should fail to select it.
190# ---
191# name: fmed3_s32_vssv_constant_bus_violation
192# legalized: true
193# regBankSelected: true
194# tracksRegLiveness: true
195
196# body: |
197#   bb.0:
198#     liveins: $sgpr0, $sgpr1, $vgpr0
199
200#     %0:sgpr(s32) = COPY $sgpr0
201#     %1:sgpr(s32) = COPY $sgpr1
202#     %2:vgpr(s32) = COPY $vgpr0
203#     %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2
204#     S_ENDPGM 0, implicit %3
205# ...
206