1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s 3 4--- 5name: test_build_vector_v_v2s32_v_s32_v_s32 6legalized: true 7regBankSelected: true 8tracksRegLiveness: true 9 10body: | 11 bb.0: 12 liveins: $vgpr0, $vgpr1 13 14 ; GCN-LABEL: name: test_build_vector_v_v2s32_v_s32_v_s32 15 ; GCN: liveins: $vgpr0, $vgpr1 16 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 17 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 18 ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 19 ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 20 %0:vgpr(s32) = COPY $vgpr0 21 %1:vgpr(s32) = COPY $vgpr1 22 %2:vgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1 23 S_ENDPGM 0, implicit %2 24... 25 26--- 27name: test_build_vector_v_v2s32_s_s32_v_s32 28legalized: true 29regBankSelected: true 30tracksRegLiveness: true 31 32body: | 33 bb.0: 34 liveins: $sgpr0, $vgpr0 35 36 ; GCN-LABEL: name: test_build_vector_v_v2s32_s_s32_v_s32 37 ; GCN: liveins: $sgpr0, $vgpr0 38 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 39 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 40 ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 41 ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 42 %0:sgpr(s32) = COPY $sgpr0 43 %1:vgpr(s32) = COPY $vgpr0 44 %2:vgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1 45 S_ENDPGM 0, implicit %2 46... 47 48--- 49name: test_build_vector_v_v2s32_v_s32_s_s32 50legalized: true 51regBankSelected: true 52tracksRegLiveness: true 53 54body: | 55 bb.0: 56 liveins: $sgpr0, $vgpr0 57 58 ; GCN-LABEL: name: test_build_vector_v_v2s32_v_s32_s_s32 59 ; GCN: liveins: $sgpr0, $vgpr0 60 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 61 ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 62 ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 63 ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 64 %0:vgpr(s32) = COPY $vgpr0 65 %1:sgpr(s32) = COPY $sgpr0 66 %2:vgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1 67 S_ENDPGM 0, implicit %2 68... 69 70--- 71name: test_build_vector_s_v2s32_s_s32_s_s32 72legalized: true 73regBankSelected: true 74tracksRegLiveness: true 75 76body: | 77 bb.0: 78 liveins: $sgpr0, $sgpr1 79 80 ; GCN-LABEL: name: test_build_vector_s_v2s32_s_s32_s_s32 81 ; GCN: liveins: $sgpr0, $sgpr1 82 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 83 ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 84 ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 85 ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]] 86 %0:sgpr(s32) = COPY $sgpr0 87 %1:sgpr(s32) = COPY $sgpr1 88 %2:sgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1 89 S_ENDPGM 0, implicit %2 90... 91 92--- 93name: test_build_vector_s_v2s64_s_s64_s_s64 94legalized: true 95regBankSelected: true 96tracksRegLiveness: true 97 98body: | 99 bb.0: 100 liveins: $sgpr0_sgpr1, $sgpr2_sgpr3 101 102 ; GCN-LABEL: name: test_build_vector_s_v2s64_s_s64_s_s64 103 ; GCN: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3 104 ; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 105 ; GCN: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3 106 ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3 107 ; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]] 108 %0:sgpr(s64) = COPY $sgpr0_sgpr1 109 %1:sgpr(s64) = COPY $sgpr2_sgpr3 110 %4:sgpr(<2 x s64>) = G_BUILD_VECTOR %0, %1 111 $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %4 112... 113