1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s 3# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s 4# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s 5 6--- 7name: fminnum_f16_vv 8legalized: true 9regBankSelected: true 10 11body: | 12 bb.0: 13 liveins: $vgpr0, $vgpr1 14 15 ; CHECK-LABEL: name: fminnum_f16_vv 16 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 17 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 18 ; CHECK: %4:vgpr_32 = nofpexcept V_MIN_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec 19 ; CHECK: S_ENDPGM 0, implicit %4 20 %0:vgpr(s32) = COPY $vgpr0 21 %1:vgpr(s32) = COPY $vgpr1 22 %2:vgpr(s16) = G_TRUNC %0 23 %3:vgpr(s16) = G_TRUNC %1 24 %4:vgpr(s16) = G_FMINNUM %2, %3 25 S_ENDPGM 0, implicit %4 26... 27 28--- 29name: fminnum_f16_v_fneg_v 30legalized: true 31regBankSelected: true 32 33body: | 34 bb.0: 35 liveins: $vgpr0, $vgpr1 36 37 ; CHECK-LABEL: name: fminnum_f16_v_fneg_v 38 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 39 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 40 ; CHECK: %5:vgpr_32 = nofpexcept V_MIN_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $mode, implicit $exec 41 ; CHECK: S_ENDPGM 0, implicit %5 42 %0:vgpr(s32) = COPY $vgpr0 43 %1:vgpr(s32) = COPY $vgpr1 44 %2:vgpr(s16) = G_TRUNC %0 45 %3:vgpr(s16) = G_TRUNC %1 46 %4:vgpr(s16) = G_FNEG %3 47 %5:vgpr(s16) = G_FMINNUM %2, %4 48 S_ENDPGM 0, implicit %5 49... 50