1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs  -o - %s | FileCheck -check-prefixes=GCN %s
3
4---
5
6name:            implicit_def_s32_sgpr
7legalized:       true
8regBankSelected: true
9
10body: |
11  bb.0:
12    ; GCN-LABEL: name: implicit_def_s32_sgpr
13    ; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
14    ; GCN: S_ENDPGM 0, implicit [[DEF]]
15    %0:sgpr(s32) = G_IMPLICIT_DEF
16    S_ENDPGM 0, implicit %0
17...
18---
19
20name:            implicit_def_s32_vgpr
21legalized:       true
22regBankSelected: true
23
24body: |
25  bb.0:
26    ; GCN-LABEL: name: implicit_def_s32_vgpr
27    ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
28    ; GCN: S_ENDPGM 0, implicit [[DEF]]
29    %0:vgpr(s32) = G_IMPLICIT_DEF
30    S_ENDPGM 0, implicit %0
31...
32
33---
34
35name:            implicit_def_s64_sgpr
36legalized:       true
37regBankSelected: true
38
39body: |
40  bb.0:
41    ; GCN-LABEL: name: implicit_def_s64_sgpr
42    ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
43    ; GCN: S_ENDPGM 0, implicit [[DEF]]
44    %0:sgpr(s64) = G_IMPLICIT_DEF
45    S_ENDPGM 0, implicit %0
46...
47
48---
49
50name:            implicit_def_s64_vgpr
51legalized:       true
52regBankSelected: true
53
54body: |
55  bb.0:
56    ; GCN-LABEL: name: implicit_def_s64_vgpr
57    ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
58    ; GCN: S_ENDPGM 0, implicit [[DEF]]
59    %0:vgpr(s64) = G_IMPLICIT_DEF
60    S_ENDPGM 0, implicit %0
61...
62
63---
64name:            implicit_def_p0_sgpr
65legalized:       true
66regBankSelected: true
67
68body: |
69  bb.0:
70    ; GCN-LABEL: name: implicit_def_p0_sgpr
71    ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
72    ; GCN: S_ENDPGM 0, implicit [[DEF]]
73    %0:sgpr(p0) = G_IMPLICIT_DEF
74    S_ENDPGM 0, implicit %0
75...
76
77---
78name:            implicit_def_p0_vgpr
79legalized:       true
80regBankSelected: true
81
82body: |
83  bb.0:
84    ; GCN-LABEL: name: implicit_def_p0_vgpr
85    ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
86    ; GCN: S_ENDPGM 0, implicit [[DEF]]
87    %0:vgpr(p0) = G_IMPLICIT_DEF
88    S_ENDPGM 0, implicit %0
89...
90
91---
92
93name:            implicit_def_p1_vgpr
94legalized:       true
95regBankSelected: true
96
97body: |
98  bb.0:
99    ; GCN-LABEL: name: implicit_def_p1_vgpr
100    ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
101    ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
102    ; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32), addrspace 1)
103    %0:vgpr(p1) = G_IMPLICIT_DEF
104    %1:vgpr(s32) = G_CONSTANT i32 4
105    G_STORE %1, %0 :: (store (s32), addrspace 1)
106...
107
108---
109
110name:            implicit_def_p3_vgpr
111legalized:       true
112regBankSelected: true
113
114body: |
115  bb.0:
116    ; GCN-LABEL: name: implicit_def_p3_vgpr
117    ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
118    ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
119    ; GCN: $m0 = S_MOV_B32 -1
120    ; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32), addrspace 1)
121    %0:vgpr(p3) = G_IMPLICIT_DEF
122    %1:vgpr(s32) = G_CONSTANT i32 4
123    G_STORE %1, %0 :: (store (s32), addrspace 1)
124...
125
126---
127
128name:            implicit_def_p4_vgpr
129legalized:       true
130regBankSelected: true
131
132body: |
133  bb.0:
134    ; GCN-LABEL: name: implicit_def_p4_vgpr
135    ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
136    ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
137    ; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32), addrspace 1)
138    %0:vgpr(p4) = G_IMPLICIT_DEF
139    %1:vgpr(s32) = G_CONSTANT i32 4
140    G_STORE %1, %0 :: (store (s32), addrspace 1)
141...
142
143---
144
145name:            implicit_def_s1_vgpr
146legalized:       true
147regBankSelected: true
148
149body: |
150  bb.0:
151    ; GCN-LABEL: name: implicit_def_s1_vgpr
152    ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
153    ; GCN: S_ENDPGM 0, implicit [[DEF]]
154    %0:vgpr(s1) = G_IMPLICIT_DEF
155    S_ENDPGM 0, implicit %0
156...
157
158---
159
160name:            implicit_def_s1_sgpr
161legalized:       true
162regBankSelected: true
163
164body: |
165  bb.0:
166    ; GCN-LABEL: name: implicit_def_s1_sgpr
167    ; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
168    ; GCN: S_ENDPGM 0, implicit [[DEF]]
169    %0:sgpr(s1) = G_IMPLICIT_DEF
170    S_ENDPGM 0, implicit %0
171...
172
173---
174
175name:            implicit_def_s1_vcc
176legalized:       true
177regBankSelected: true
178
179body: |
180  bb.0:
181    ; GCN-LABEL: name: implicit_def_s1_vcc
182    ; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
183    ; GCN: S_ENDPGM 0, implicit [[DEF]]
184    %0:vcc(s1) = G_IMPLICIT_DEF
185    S_ENDPGM 0, implicit %0
186...
187
188---
189
190name:            implicit_def_s1024_sgpr
191legalized:       true
192regBankSelected: true
193
194body: |
195  bb.0:
196    ; GCN-LABEL: name: implicit_def_s1024_sgpr
197    ; GCN: [[DEF:%[0-9]+]]:sgpr_1024 = IMPLICIT_DEF
198    ; GCN: S_ENDPGM 0, implicit [[DEF]]
199    %0:sgpr(s1024) = G_IMPLICIT_DEF
200    S_ENDPGM 0, implicit %0
201...
202---
203
204name:            implicit_def_s1024_vgpr
205legalized:       true
206regBankSelected: true
207
208body: |
209  bb.0:
210    ; GCN-LABEL: name: implicit_def_s1024_vgpr
211    ; GCN: [[DEF:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF
212    ; GCN: S_ENDPGM 0, implicit [[DEF]]
213    %0:vgpr(s1024) = G_IMPLICIT_DEF
214    S_ENDPGM 0, implicit %0
215...
216