1# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel-abort=2 -pass-remarks-missed='gisel*' -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERR %s 2 3# Make sure incorrect usage of control flow intrinsics fails to select in case some transform separated the intrinsic from its branch. 4 5# ERR: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: brcond_si_if_different_block) 6# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: si_if_not_brcond_user) 7# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: si_if_multi_user) 8# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: brcond_si_if_xor_0) 9# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: brcond_si_if_or_neg1) 10# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: brcond_si_if_negated_multi_use) 11 12 13--- 14name: brcond_si_if_different_block 15body: | 16 bb.0: 17 successors: %bb.1 18 liveins: $vgpr0, $vgpr1 19 %0:_(s32) = COPY $vgpr0 20 %1:_(s32) = COPY $vgpr1 21 %2:_(s1) = G_ICMP intpred(ne), %0, %1 22 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2 23 24 bb.1: 25 G_BRCOND %3, %bb.1 26 27... 28 29--- 30name: si_if_not_brcond_user 31body: | 32 bb.0: 33 liveins: $vgpr0, $vgpr1 34 %0:_(s32) = COPY $vgpr0 35 %1:_(s32) = COPY $vgpr1 36 %2:_(s1) = G_ICMP intpred(ne), %0, %1 37 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2 38 %5:_(s32) = G_SELECT %3, %0, %1 39 S_ENDPGM 0, implicit %5 40 41... 42 43--- 44name: si_if_multi_user 45body: | 46 bb.0: 47 liveins: $vgpr0, $vgpr1 48 %0:_(s32) = COPY $vgpr0 49 %1:_(s32) = COPY $vgpr1 50 %2:_(s1) = G_ICMP intpred(ne), %0, %1 51 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2 52 %5:_(s32) = G_SELECT %3, %0, %1 53 G_BRCOND %3, %bb.1 54 55 bb.1: 56 S_ENDPGM 0, implicit %5 57 58... 59 60# Make sure we only match G_XOR (if), -1 61--- 62name: brcond_si_if_xor_0 63body: | 64 bb.0: 65 successors: %bb.1 66 liveins: $vgpr0, $vgpr1 67 %0:_(s32) = COPY $vgpr0 68 %1:_(s32) = COPY $vgpr1 69 %2:_(s1) = G_ICMP intpred(ne), %0, %1 70 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2 71 %5:_(s1) = G_CONSTANT i1 false 72 %6:_(s1) = G_XOR %3, %5 73 G_BRCOND %6, %bb.2 74 G_BR %bb.3 75 76 bb.1: 77 S_NOP 0 78 79 bb.2: 80 S_NOP 1 81 82 bb.3: 83 S_NOP 2 84... 85 86# Make sure we only match G_XOR (if), -1 87--- 88name: brcond_si_if_or_neg1 89body: | 90 bb.0: 91 successors: %bb.1 92 liveins: $vgpr0, $vgpr1 93 %0:_(s32) = COPY $vgpr0 94 %1:_(s32) = COPY $vgpr1 95 %2:_(s1) = G_ICMP intpred(ne), %0, %1 96 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2 97 %5:_(s1) = G_CONSTANT i1 true 98 %6:_(s1) = G_OR %3, %5 99 G_BRCOND %6, %bb.2 100 G_BR %bb.3 101 102 bb.1: 103 S_NOP 0 104 105 bb.2: 106 S_NOP 1 107 108 bb.3: 109 S_NOP 2 110... 111 112--- 113name: brcond_si_if_negated_multi_use 114body: | 115 bb.0: 116 successors: %bb.1 117 liveins: $vgpr0, $vgpr1 118 %0:_(s32) = COPY $vgpr0 119 %1:_(s32) = COPY $vgpr1 120 %2:_(s1) = G_ICMP intpred(ne), %0, %1 121 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2 122 %5:_(s1) = G_CONSTANT i1 true 123 %6:_(s1) = G_XOR %3, %5 124 S_NOP 0, implicit %6 125 G_BRCOND %6, %bb.2 126 G_BR %bb.3 127 128 bb.1: 129 S_NOP 0 130 131 bb.2: 132 S_NOP 1 133 134 bb.3: 135 S_NOP 2 136... 137