1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - %s | FileCheck -check-prefix=GFX6 %s
3; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - %s | FileCheck -check-prefix=GFX8 %s
4; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10 %s
5
6define amdgpu_ps void @image_store_f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t, float %data) {
7; GFX6-LABEL: image_store_f32:
8; GFX6:       ; %bb.0:
9; GFX6-NEXT:    s_mov_b32 s0, s2
10; GFX6-NEXT:    s_mov_b32 s1, s3
11; GFX6-NEXT:    s_mov_b32 s2, s4
12; GFX6-NEXT:    s_mov_b32 s3, s5
13; GFX6-NEXT:    s_mov_b32 s4, s6
14; GFX6-NEXT:    s_mov_b32 s5, s7
15; GFX6-NEXT:    s_mov_b32 s6, s8
16; GFX6-NEXT:    s_mov_b32 s7, s9
17; GFX6-NEXT:    image_store v2, v[0:1], s[0:7] dmask:0x1 unorm
18; GFX6-NEXT:    s_endpgm
19;
20; GFX8-LABEL: image_store_f32:
21; GFX8:       ; %bb.0:
22; GFX8-NEXT:    s_mov_b32 s0, s2
23; GFX8-NEXT:    s_mov_b32 s1, s3
24; GFX8-NEXT:    s_mov_b32 s2, s4
25; GFX8-NEXT:    s_mov_b32 s3, s5
26; GFX8-NEXT:    s_mov_b32 s4, s6
27; GFX8-NEXT:    s_mov_b32 s5, s7
28; GFX8-NEXT:    s_mov_b32 s6, s8
29; GFX8-NEXT:    s_mov_b32 s7, s9
30; GFX8-NEXT:    image_store v2, v[0:1], s[0:7] dmask:0x1 unorm
31; GFX8-NEXT:    s_endpgm
32;
33; GFX10-LABEL: image_store_f32:
34; GFX10:       ; %bb.0:
35; GFX10-NEXT:    s_mov_b32 s0, s2
36; GFX10-NEXT:    s_mov_b32 s1, s3
37; GFX10-NEXT:    s_mov_b32 s2, s4
38; GFX10-NEXT:    s_mov_b32 s3, s5
39; GFX10-NEXT:    s_mov_b32 s4, s6
40; GFX10-NEXT:    s_mov_b32 s5, s7
41; GFX10-NEXT:    s_mov_b32 s6, s8
42; GFX10-NEXT:    s_mov_b32 s7, s9
43; GFX10-NEXT:    image_store v2, v[0:1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm
44; GFX10-NEXT:    s_endpgm
45  call void @llvm.amdgcn.image.store.2d.f32.i32(float %data, i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
46  ret void
47}
48
49define amdgpu_ps void @image_store_v2f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t, <2 x float> %in) {
50; GFX6-LABEL: image_store_v2f32:
51; GFX6:       ; %bb.0:
52; GFX6-NEXT:    s_mov_b32 s0, s2
53; GFX6-NEXT:    s_mov_b32 s1, s3
54; GFX6-NEXT:    s_mov_b32 s2, s4
55; GFX6-NEXT:    s_mov_b32 s3, s5
56; GFX6-NEXT:    s_mov_b32 s4, s6
57; GFX6-NEXT:    s_mov_b32 s5, s7
58; GFX6-NEXT:    s_mov_b32 s6, s8
59; GFX6-NEXT:    s_mov_b32 s7, s9
60; GFX6-NEXT:    image_store v[2:3], v[0:1], s[0:7] dmask:0x3 unorm
61; GFX6-NEXT:    s_endpgm
62;
63; GFX8-LABEL: image_store_v2f32:
64; GFX8:       ; %bb.0:
65; GFX8-NEXT:    s_mov_b32 s0, s2
66; GFX8-NEXT:    s_mov_b32 s1, s3
67; GFX8-NEXT:    s_mov_b32 s2, s4
68; GFX8-NEXT:    s_mov_b32 s3, s5
69; GFX8-NEXT:    s_mov_b32 s4, s6
70; GFX8-NEXT:    s_mov_b32 s5, s7
71; GFX8-NEXT:    s_mov_b32 s6, s8
72; GFX8-NEXT:    s_mov_b32 s7, s9
73; GFX8-NEXT:    image_store v[2:3], v[0:1], s[0:7] dmask:0x3 unorm
74; GFX8-NEXT:    s_endpgm
75;
76; GFX10-LABEL: image_store_v2f32:
77; GFX10:       ; %bb.0:
78; GFX10-NEXT:    s_mov_b32 s0, s2
79; GFX10-NEXT:    s_mov_b32 s1, s3
80; GFX10-NEXT:    s_mov_b32 s2, s4
81; GFX10-NEXT:    s_mov_b32 s3, s5
82; GFX10-NEXT:    s_mov_b32 s4, s6
83; GFX10-NEXT:    s_mov_b32 s5, s7
84; GFX10-NEXT:    s_mov_b32 s6, s8
85; GFX10-NEXT:    s_mov_b32 s7, s9
86; GFX10-NEXT:    image_store v[2:3], v[0:1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm
87; GFX10-NEXT:    s_endpgm
88  call void @llvm.amdgcn.image.store.2d.v2f32.i32(<2 x float> %in, i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
89  ret void
90}
91
92define amdgpu_ps void @image_store_v3f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t, <3 x float> %in) {
93; GFX6-LABEL: image_store_v3f32:
94; GFX6:       ; %bb.0:
95; GFX6-NEXT:    s_mov_b32 s0, s2
96; GFX6-NEXT:    s_mov_b32 s1, s3
97; GFX6-NEXT:    s_mov_b32 s2, s4
98; GFX6-NEXT:    s_mov_b32 s3, s5
99; GFX6-NEXT:    s_mov_b32 s4, s6
100; GFX6-NEXT:    s_mov_b32 s5, s7
101; GFX6-NEXT:    s_mov_b32 s6, s8
102; GFX6-NEXT:    s_mov_b32 s7, s9
103; GFX6-NEXT:    image_store v[2:4], v[0:1], s[0:7] dmask:0x7 unorm
104; GFX6-NEXT:    s_endpgm
105;
106; GFX8-LABEL: image_store_v3f32:
107; GFX8:       ; %bb.0:
108; GFX8-NEXT:    s_mov_b32 s0, s2
109; GFX8-NEXT:    s_mov_b32 s1, s3
110; GFX8-NEXT:    s_mov_b32 s2, s4
111; GFX8-NEXT:    s_mov_b32 s3, s5
112; GFX8-NEXT:    s_mov_b32 s4, s6
113; GFX8-NEXT:    s_mov_b32 s5, s7
114; GFX8-NEXT:    s_mov_b32 s6, s8
115; GFX8-NEXT:    s_mov_b32 s7, s9
116; GFX8-NEXT:    image_store v[2:4], v[0:1], s[0:7] dmask:0x7 unorm
117; GFX8-NEXT:    s_endpgm
118;
119; GFX10-LABEL: image_store_v3f32:
120; GFX10:       ; %bb.0:
121; GFX10-NEXT:    s_mov_b32 s0, s2
122; GFX10-NEXT:    s_mov_b32 s1, s3
123; GFX10-NEXT:    s_mov_b32 s2, s4
124; GFX10-NEXT:    s_mov_b32 s3, s5
125; GFX10-NEXT:    s_mov_b32 s4, s6
126; GFX10-NEXT:    s_mov_b32 s5, s7
127; GFX10-NEXT:    s_mov_b32 s6, s8
128; GFX10-NEXT:    s_mov_b32 s7, s9
129; GFX10-NEXT:    image_store v[2:4], v[0:1], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_2D unorm
130; GFX10-NEXT:    s_endpgm
131  call void @llvm.amdgcn.image.store.2d.v3f32.i32(<3 x float> %in, i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
132  ret void
133}
134
135define amdgpu_ps void @image_store_v4f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t, <4 x float> %in) {
136; GFX6-LABEL: image_store_v4f32:
137; GFX6:       ; %bb.0:
138; GFX6-NEXT:    s_mov_b32 s0, s2
139; GFX6-NEXT:    s_mov_b32 s1, s3
140; GFX6-NEXT:    s_mov_b32 s2, s4
141; GFX6-NEXT:    s_mov_b32 s3, s5
142; GFX6-NEXT:    s_mov_b32 s4, s6
143; GFX6-NEXT:    s_mov_b32 s5, s7
144; GFX6-NEXT:    s_mov_b32 s6, s8
145; GFX6-NEXT:    s_mov_b32 s7, s9
146; GFX6-NEXT:    image_store v[2:5], v[0:1], s[0:7] dmask:0xf unorm
147; GFX6-NEXT:    s_endpgm
148;
149; GFX8-LABEL: image_store_v4f32:
150; GFX8:       ; %bb.0:
151; GFX8-NEXT:    s_mov_b32 s0, s2
152; GFX8-NEXT:    s_mov_b32 s1, s3
153; GFX8-NEXT:    s_mov_b32 s2, s4
154; GFX8-NEXT:    s_mov_b32 s3, s5
155; GFX8-NEXT:    s_mov_b32 s4, s6
156; GFX8-NEXT:    s_mov_b32 s5, s7
157; GFX8-NEXT:    s_mov_b32 s6, s8
158; GFX8-NEXT:    s_mov_b32 s7, s9
159; GFX8-NEXT:    image_store v[2:5], v[0:1], s[0:7] dmask:0xf unorm
160; GFX8-NEXT:    s_endpgm
161;
162; GFX10-LABEL: image_store_v4f32:
163; GFX10:       ; %bb.0:
164; GFX10-NEXT:    s_mov_b32 s0, s2
165; GFX10-NEXT:    s_mov_b32 s1, s3
166; GFX10-NEXT:    s_mov_b32 s2, s4
167; GFX10-NEXT:    s_mov_b32 s3, s5
168; GFX10-NEXT:    s_mov_b32 s4, s6
169; GFX10-NEXT:    s_mov_b32 s5, s7
170; GFX10-NEXT:    s_mov_b32 s6, s8
171; GFX10-NEXT:    s_mov_b32 s7, s9
172; GFX10-NEXT:    image_store v[2:5], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm
173; GFX10-NEXT:    s_endpgm
174  call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %in, i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
175  ret void
176}
177
178define amdgpu_ps void @image_store_v4f32_dmask_0001(<8 x i32> inreg %rsrc, i32 %s, i32 %t, <4 x float> %in) {
179; GFX6-LABEL: image_store_v4f32_dmask_0001:
180; GFX6:       ; %bb.0:
181; GFX6-NEXT:    s_mov_b32 s0, s2
182; GFX6-NEXT:    s_mov_b32 s1, s3
183; GFX6-NEXT:    s_mov_b32 s2, s4
184; GFX6-NEXT:    s_mov_b32 s3, s5
185; GFX6-NEXT:    s_mov_b32 s4, s6
186; GFX6-NEXT:    s_mov_b32 s5, s7
187; GFX6-NEXT:    s_mov_b32 s6, s8
188; GFX6-NEXT:    s_mov_b32 s7, s9
189; GFX6-NEXT:    image_store v[2:5], v[0:1], s[0:7] dmask:0x1 unorm
190; GFX6-NEXT:    s_endpgm
191;
192; GFX8-LABEL: image_store_v4f32_dmask_0001:
193; GFX8:       ; %bb.0:
194; GFX8-NEXT:    s_mov_b32 s0, s2
195; GFX8-NEXT:    s_mov_b32 s1, s3
196; GFX8-NEXT:    s_mov_b32 s2, s4
197; GFX8-NEXT:    s_mov_b32 s3, s5
198; GFX8-NEXT:    s_mov_b32 s4, s6
199; GFX8-NEXT:    s_mov_b32 s5, s7
200; GFX8-NEXT:    s_mov_b32 s6, s8
201; GFX8-NEXT:    s_mov_b32 s7, s9
202; GFX8-NEXT:    image_store v[2:5], v[0:1], s[0:7] dmask:0x1 unorm
203; GFX8-NEXT:    s_endpgm
204;
205; GFX10-LABEL: image_store_v4f32_dmask_0001:
206; GFX10:       ; %bb.0:
207; GFX10-NEXT:    s_mov_b32 s0, s2
208; GFX10-NEXT:    s_mov_b32 s1, s3
209; GFX10-NEXT:    s_mov_b32 s2, s4
210; GFX10-NEXT:    s_mov_b32 s3, s5
211; GFX10-NEXT:    s_mov_b32 s4, s6
212; GFX10-NEXT:    s_mov_b32 s5, s7
213; GFX10-NEXT:    s_mov_b32 s6, s8
214; GFX10-NEXT:    s_mov_b32 s7, s9
215; GFX10-NEXT:    image_store v[2:5], v[0:1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm
216; GFX10-NEXT:    s_endpgm
217  call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %in, i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
218  ret void
219}
220
221define amdgpu_ps void @image_store_v4f32_dmask_0010(<8 x i32> inreg %rsrc, i32 %s, i32 %t, <4 x float> %in) {
222; GFX6-LABEL: image_store_v4f32_dmask_0010:
223; GFX6:       ; %bb.0:
224; GFX6-NEXT:    s_mov_b32 s0, s2
225; GFX6-NEXT:    s_mov_b32 s1, s3
226; GFX6-NEXT:    s_mov_b32 s2, s4
227; GFX6-NEXT:    s_mov_b32 s3, s5
228; GFX6-NEXT:    s_mov_b32 s4, s6
229; GFX6-NEXT:    s_mov_b32 s5, s7
230; GFX6-NEXT:    s_mov_b32 s6, s8
231; GFX6-NEXT:    s_mov_b32 s7, s9
232; GFX6-NEXT:    image_store v[2:5], v[0:1], s[0:7] dmask:0x2 unorm
233; GFX6-NEXT:    s_endpgm
234;
235; GFX8-LABEL: image_store_v4f32_dmask_0010:
236; GFX8:       ; %bb.0:
237; GFX8-NEXT:    s_mov_b32 s0, s2
238; GFX8-NEXT:    s_mov_b32 s1, s3
239; GFX8-NEXT:    s_mov_b32 s2, s4
240; GFX8-NEXT:    s_mov_b32 s3, s5
241; GFX8-NEXT:    s_mov_b32 s4, s6
242; GFX8-NEXT:    s_mov_b32 s5, s7
243; GFX8-NEXT:    s_mov_b32 s6, s8
244; GFX8-NEXT:    s_mov_b32 s7, s9
245; GFX8-NEXT:    image_store v[2:5], v[0:1], s[0:7] dmask:0x2 unorm
246; GFX8-NEXT:    s_endpgm
247;
248; GFX10-LABEL: image_store_v4f32_dmask_0010:
249; GFX10:       ; %bb.0:
250; GFX10-NEXT:    s_mov_b32 s0, s2
251; GFX10-NEXT:    s_mov_b32 s1, s3
252; GFX10-NEXT:    s_mov_b32 s2, s4
253; GFX10-NEXT:    s_mov_b32 s3, s5
254; GFX10-NEXT:    s_mov_b32 s4, s6
255; GFX10-NEXT:    s_mov_b32 s5, s7
256; GFX10-NEXT:    s_mov_b32 s6, s8
257; GFX10-NEXT:    s_mov_b32 s7, s9
258; GFX10-NEXT:    image_store v[2:5], v[0:1], s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_2D unorm
259; GFX10-NEXT:    s_endpgm
260  call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %in, i32 2, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
261  ret void
262}
263
264define amdgpu_ps void @image_store_v4f32_dmask_0100(<8 x i32> inreg %rsrc, i32 %s, i32 %t, <4 x float> %in) {
265; GFX6-LABEL: image_store_v4f32_dmask_0100:
266; GFX6:       ; %bb.0:
267; GFX6-NEXT:    s_mov_b32 s0, s2
268; GFX6-NEXT:    s_mov_b32 s1, s3
269; GFX6-NEXT:    s_mov_b32 s2, s4
270; GFX6-NEXT:    s_mov_b32 s3, s5
271; GFX6-NEXT:    s_mov_b32 s4, s6
272; GFX6-NEXT:    s_mov_b32 s5, s7
273; GFX6-NEXT:    s_mov_b32 s6, s8
274; GFX6-NEXT:    s_mov_b32 s7, s9
275; GFX6-NEXT:    image_store v[2:5], v[0:1], s[0:7] dmask:0x4 unorm
276; GFX6-NEXT:    s_endpgm
277;
278; GFX8-LABEL: image_store_v4f32_dmask_0100:
279; GFX8:       ; %bb.0:
280; GFX8-NEXT:    s_mov_b32 s0, s2
281; GFX8-NEXT:    s_mov_b32 s1, s3
282; GFX8-NEXT:    s_mov_b32 s2, s4
283; GFX8-NEXT:    s_mov_b32 s3, s5
284; GFX8-NEXT:    s_mov_b32 s4, s6
285; GFX8-NEXT:    s_mov_b32 s5, s7
286; GFX8-NEXT:    s_mov_b32 s6, s8
287; GFX8-NEXT:    s_mov_b32 s7, s9
288; GFX8-NEXT:    image_store v[2:5], v[0:1], s[0:7] dmask:0x4 unorm
289; GFX8-NEXT:    s_endpgm
290;
291; GFX10-LABEL: image_store_v4f32_dmask_0100:
292; GFX10:       ; %bb.0:
293; GFX10-NEXT:    s_mov_b32 s0, s2
294; GFX10-NEXT:    s_mov_b32 s1, s3
295; GFX10-NEXT:    s_mov_b32 s2, s4
296; GFX10-NEXT:    s_mov_b32 s3, s5
297; GFX10-NEXT:    s_mov_b32 s4, s6
298; GFX10-NEXT:    s_mov_b32 s5, s7
299; GFX10-NEXT:    s_mov_b32 s6, s8
300; GFX10-NEXT:    s_mov_b32 s7, s9
301; GFX10-NEXT:    image_store v[2:5], v[0:1], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D unorm
302; GFX10-NEXT:    s_endpgm
303  call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %in, i32 4, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
304  ret void
305}
306
307define amdgpu_ps void @image_store_v4f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t, <4 x float> %in) {
308; GFX6-LABEL: image_store_v4f32_dmask_1000:
309; GFX6:       ; %bb.0:
310; GFX6-NEXT:    s_mov_b32 s0, s2
311; GFX6-NEXT:    s_mov_b32 s1, s3
312; GFX6-NEXT:    s_mov_b32 s2, s4
313; GFX6-NEXT:    s_mov_b32 s3, s5
314; GFX6-NEXT:    s_mov_b32 s4, s6
315; GFX6-NEXT:    s_mov_b32 s5, s7
316; GFX6-NEXT:    s_mov_b32 s6, s8
317; GFX6-NEXT:    s_mov_b32 s7, s9
318; GFX6-NEXT:    image_store v[2:5], v[0:1], s[0:7] dmask:0x8 unorm
319; GFX6-NEXT:    s_endpgm
320;
321; GFX8-LABEL: image_store_v4f32_dmask_1000:
322; GFX8:       ; %bb.0:
323; GFX8-NEXT:    s_mov_b32 s0, s2
324; GFX8-NEXT:    s_mov_b32 s1, s3
325; GFX8-NEXT:    s_mov_b32 s2, s4
326; GFX8-NEXT:    s_mov_b32 s3, s5
327; GFX8-NEXT:    s_mov_b32 s4, s6
328; GFX8-NEXT:    s_mov_b32 s5, s7
329; GFX8-NEXT:    s_mov_b32 s6, s8
330; GFX8-NEXT:    s_mov_b32 s7, s9
331; GFX8-NEXT:    image_store v[2:5], v[0:1], s[0:7] dmask:0x8 unorm
332; GFX8-NEXT:    s_endpgm
333;
334; GFX10-LABEL: image_store_v4f32_dmask_1000:
335; GFX10:       ; %bb.0:
336; GFX10-NEXT:    s_mov_b32 s0, s2
337; GFX10-NEXT:    s_mov_b32 s1, s3
338; GFX10-NEXT:    s_mov_b32 s2, s4
339; GFX10-NEXT:    s_mov_b32 s3, s5
340; GFX10-NEXT:    s_mov_b32 s4, s6
341; GFX10-NEXT:    s_mov_b32 s5, s7
342; GFX10-NEXT:    s_mov_b32 s6, s8
343; GFX10-NEXT:    s_mov_b32 s7, s9
344; GFX10-NEXT:    image_store v[2:5], v[0:1], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_2D unorm
345; GFX10-NEXT:    s_endpgm
346  call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %in, i32 8, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
347  ret void
348}
349
350define amdgpu_ps void @image_store_v4f32_dmask_0011(<8 x i32> inreg %rsrc, i32 %s, i32 %t, <4 x float> %in) {
351; GFX6-LABEL: image_store_v4f32_dmask_0011:
352; GFX6:       ; %bb.0:
353; GFX6-NEXT:    s_mov_b32 s0, s2
354; GFX6-NEXT:    s_mov_b32 s1, s3
355; GFX6-NEXT:    s_mov_b32 s2, s4
356; GFX6-NEXT:    s_mov_b32 s3, s5
357; GFX6-NEXT:    s_mov_b32 s4, s6
358; GFX6-NEXT:    s_mov_b32 s5, s7
359; GFX6-NEXT:    s_mov_b32 s6, s8
360; GFX6-NEXT:    s_mov_b32 s7, s9
361; GFX6-NEXT:    image_store v[2:5], v[0:1], s[0:7] dmask:0x3 unorm
362; GFX6-NEXT:    s_endpgm
363;
364; GFX8-LABEL: image_store_v4f32_dmask_0011:
365; GFX8:       ; %bb.0:
366; GFX8-NEXT:    s_mov_b32 s0, s2
367; GFX8-NEXT:    s_mov_b32 s1, s3
368; GFX8-NEXT:    s_mov_b32 s2, s4
369; GFX8-NEXT:    s_mov_b32 s3, s5
370; GFX8-NEXT:    s_mov_b32 s4, s6
371; GFX8-NEXT:    s_mov_b32 s5, s7
372; GFX8-NEXT:    s_mov_b32 s6, s8
373; GFX8-NEXT:    s_mov_b32 s7, s9
374; GFX8-NEXT:    image_store v[2:5], v[0:1], s[0:7] dmask:0x3 unorm
375; GFX8-NEXT:    s_endpgm
376;
377; GFX10-LABEL: image_store_v4f32_dmask_0011:
378; GFX10:       ; %bb.0:
379; GFX10-NEXT:    s_mov_b32 s0, s2
380; GFX10-NEXT:    s_mov_b32 s1, s3
381; GFX10-NEXT:    s_mov_b32 s2, s4
382; GFX10-NEXT:    s_mov_b32 s3, s5
383; GFX10-NEXT:    s_mov_b32 s4, s6
384; GFX10-NEXT:    s_mov_b32 s5, s7
385; GFX10-NEXT:    s_mov_b32 s6, s8
386; GFX10-NEXT:    s_mov_b32 s7, s9
387; GFX10-NEXT:    image_store v[2:5], v[0:1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm
388; GFX10-NEXT:    s_endpgm
389  call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %in, i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
390  ret void
391}
392
393define amdgpu_ps void @image_store_v4f32_dmask_0110(<8 x i32> inreg %rsrc, i32 %s, i32 %t, <4 x float> %in) {
394; GFX6-LABEL: image_store_v4f32_dmask_0110:
395; GFX6:       ; %bb.0:
396; GFX6-NEXT:    s_mov_b32 s0, s2
397; GFX6-NEXT:    s_mov_b32 s1, s3
398; GFX6-NEXT:    s_mov_b32 s2, s4
399; GFX6-NEXT:    s_mov_b32 s3, s5
400; GFX6-NEXT:    s_mov_b32 s4, s6
401; GFX6-NEXT:    s_mov_b32 s5, s7
402; GFX6-NEXT:    s_mov_b32 s6, s8
403; GFX6-NEXT:    s_mov_b32 s7, s9
404; GFX6-NEXT:    image_store v[2:5], v[0:1], s[0:7] dmask:0x6 unorm
405; GFX6-NEXT:    s_endpgm
406;
407; GFX8-LABEL: image_store_v4f32_dmask_0110:
408; GFX8:       ; %bb.0:
409; GFX8-NEXT:    s_mov_b32 s0, s2
410; GFX8-NEXT:    s_mov_b32 s1, s3
411; GFX8-NEXT:    s_mov_b32 s2, s4
412; GFX8-NEXT:    s_mov_b32 s3, s5
413; GFX8-NEXT:    s_mov_b32 s4, s6
414; GFX8-NEXT:    s_mov_b32 s5, s7
415; GFX8-NEXT:    s_mov_b32 s6, s8
416; GFX8-NEXT:    s_mov_b32 s7, s9
417; GFX8-NEXT:    image_store v[2:5], v[0:1], s[0:7] dmask:0x6 unorm
418; GFX8-NEXT:    s_endpgm
419;
420; GFX10-LABEL: image_store_v4f32_dmask_0110:
421; GFX10:       ; %bb.0:
422; GFX10-NEXT:    s_mov_b32 s0, s2
423; GFX10-NEXT:    s_mov_b32 s1, s3
424; GFX10-NEXT:    s_mov_b32 s2, s4
425; GFX10-NEXT:    s_mov_b32 s3, s5
426; GFX10-NEXT:    s_mov_b32 s4, s6
427; GFX10-NEXT:    s_mov_b32 s5, s7
428; GFX10-NEXT:    s_mov_b32 s6, s8
429; GFX10-NEXT:    s_mov_b32 s7, s9
430; GFX10-NEXT:    image_store v[2:5], v[0:1], s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_2D unorm
431; GFX10-NEXT:    s_endpgm
432  call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %in, i32 6, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
433  ret void
434}
435
436declare void @llvm.amdgcn.image.store.2d.f32.i32(float, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
437declare void @llvm.amdgcn.image.store.2d.v2f32.i32(<2 x float>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
438declare void @llvm.amdgcn.image.store.2d.v3f32.i32(<3 x float>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
439declare void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
440
441attributes #0 = { nounwind writeonly }
442