1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -march=amdgcn -verify-machineinstrs -o - %s | FileCheck %s
3
4define amdgpu_cs void @test1(i32 %arg1, <4 x i32> inreg %arg2, i32, i32 addrspace(6)* inreg %arg3) {
5; CHECK-LABEL: test1:
6; CHECK:       ; %bb.0: ; %.entry
7; CHECK-NEXT:    v_and_b32_e32 v3, 0x3ffffffc, v0
8; CHECK-NEXT:    v_mov_b32_e32 v0, 11
9; CHECK-NEXT:    v_mov_b32_e32 v1, 22
10; CHECK-NEXT:    v_mov_b32_e32 v2, 33
11; CHECK-NEXT:    v_lshlrev_b32_e32 v3, 2, v3
12; CHECK-NEXT:    v_add_i32_e32 v4, vcc, s4, v3
13; CHECK-NEXT:    v_mov_b32_e32 v3, 44
14; CHECK-NEXT:    buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 offen
15; CHECK-NEXT:    s_endpgm
16.entry:
17  %bs1 = and i32 %arg1, 1073741820
18  %ep1 = getelementptr i32, i32 addrspace(6)* %arg3, i32 %bs1
19  %ad1 = ptrtoint i32 addrspace(6)* %ep1 to i32
20  call void @llvm.amdgcn.raw.buffer.store.i32(i32 11, <4 x i32> %arg2, i32 %ad1, i32 0, i32 0)
21
22  %bs2 = or i32 %bs1, 1
23  %ep2 = getelementptr i32, i32 addrspace(6)* %arg3, i32 %bs2
24  %ad2 = ptrtoint i32 addrspace(6)* %ep2 to i32
25  call void @llvm.amdgcn.raw.buffer.store.i32(i32 22, <4 x i32> %arg2, i32 %ad2, i32 0, i32 0)
26
27  %bs3 = or i32 %bs1, 2
28  %ep3 = getelementptr i32, i32 addrspace(6)* %arg3, i32 %bs3
29  %ad3 = ptrtoint i32 addrspace(6)* %ep3 to i32
30  call void @llvm.amdgcn.raw.buffer.store.i32(i32 33, <4 x i32> %arg2, i32 %ad3, i32 0, i32 0)
31
32  %bs4 = or i32 %bs1, 3
33  %ep4 = getelementptr i32, i32 addrspace(6)* %arg3, i32 %bs4
34  %ad4 = ptrtoint i32 addrspace(6)* %ep4 to i32
35  call void @llvm.amdgcn.raw.buffer.store.i32(i32 44, <4 x i32> %arg2, i32 %ad4, i32 0, i32 0)
36
37  ret void
38}
39
40define amdgpu_cs void @test2(i32 %arg1, <4 x i32> inreg %arg2) {
41; CHECK-LABEL: test2:
42; CHECK:       ; %bb.0: ; %.entry
43; CHECK-NEXT:    v_and_b32_e32 v3, 0x3ffffffc, v0
44; CHECK-NEXT:    v_mov_b32_e32 v0, 11
45; CHECK-NEXT:    v_mov_b32_e32 v1, 22
46; CHECK-NEXT:    v_mov_b32_e32 v2, 33
47; CHECK-NEXT:    v_lshlrev_b32_e32 v4, 2, v3
48; CHECK-NEXT:    v_mov_b32_e32 v3, 44
49; CHECK-NEXT:    buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 offen
50; CHECK-NEXT:    s_endpgm
51.entry:
52  %bs1 = and i32 %arg1, 1073741820
53  %ep1 = getelementptr <{ [64 x i32] }>, <{ [64 x i32] }> addrspace(6)* null, i32 0, i32 0, i32 %bs1
54  %ad1 = ptrtoint i32 addrspace(6)* %ep1 to i32
55  call void @llvm.amdgcn.raw.buffer.store.i32(i32 11, <4 x i32> %arg2, i32 %ad1, i32 0, i32 0)
56
57  %bs2 = or i32 %bs1, 1
58  %ep2 = getelementptr <{ [64 x i32] }>, <{ [64 x i32] }> addrspace(6)* null, i32 0, i32 0, i32 %bs2
59  %ad2 = ptrtoint i32 addrspace(6)* %ep2 to i32
60  call void @llvm.amdgcn.raw.buffer.store.i32(i32 22, <4 x i32> %arg2, i32 %ad2, i32 0, i32 0)
61
62  %bs3 = or i32 %bs1, 2
63  %ep3 = getelementptr <{ [64 x i32] }>, <{ [64 x i32] }> addrspace(6)* null, i32 0, i32 0, i32 %bs3
64  %ad3 = ptrtoint i32 addrspace(6)* %ep3 to i32
65  call void @llvm.amdgcn.raw.buffer.store.i32(i32 33, <4 x i32> %arg2, i32 %ad3, i32 0, i32 0)
66
67  %bs4 = or i32 %bs1, 3
68  %ep4 = getelementptr <{ [64 x i32] }>, <{ [64 x i32] }> addrspace(6)* null, i32 0, i32 0, i32 %bs4
69  %ad4 = ptrtoint i32 addrspace(6)* %ep4 to i32
70  call void @llvm.amdgcn.raw.buffer.store.i32(i32 44, <4 x i32> %arg2, i32 %ad4, i32 0, i32 0)
71
72  ret void
73}
74
75declare void @llvm.amdgcn.raw.buffer.store.i32(i32, <4 x i32>, i32, i32, i32 immarg)
76