1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
3
4define i32 @test_min_max_ValK0_K1_u32(i32 %a) {
5; GFX10-LABEL: test_min_max_ValK0_K1_u32:
6; GFX10:       ; %bb.0:
7; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
8; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
9; GFX10-NEXT:    v_med3_u32 v0, v0, 12, 17
10; GFX10-NEXT:    s_setpc_b64 s[30:31]
11  %umax = call i32 @llvm.umax.i32(i32 %a, i32 12)
12  %umed = call i32 @llvm.umin.i32(i32 %umax, i32 17)
13  ret i32 %umed
14}
15
16define i32 @min_max_ValK0_K1_i32(i32 %a) {
17; GFX10-LABEL: min_max_ValK0_K1_i32:
18; GFX10:       ; %bb.0:
19; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
20; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
21; GFX10-NEXT:    v_med3_u32 v0, v0, 12, 17
22; GFX10-NEXT:    s_setpc_b64 s[30:31]
23  %umax = call i32 @llvm.umax.i32(i32 12, i32 %a)
24  %umed = call i32 @llvm.umin.i32(i32 %umax, i32 17)
25  ret i32 %umed
26}
27
28define i32 @test_min_K1max_ValK0__u32(i32 %a) {
29; GFX10-LABEL: test_min_K1max_ValK0__u32:
30; GFX10:       ; %bb.0:
31; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
32; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
33; GFX10-NEXT:    v_med3_u32 v0, v0, 12, 17
34; GFX10-NEXT:    s_setpc_b64 s[30:31]
35  %umax = call i32 @llvm.umax.i32(i32 %a, i32 12)
36  %umed = call i32 @llvm.umin.i32(i32 17, i32 %umax)
37  ret i32 %umed
38}
39
40define i32 @test_min_K1max_K0Val__u32(i32 %a) {
41; GFX10-LABEL: test_min_K1max_K0Val__u32:
42; GFX10:       ; %bb.0:
43; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
44; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
45; GFX10-NEXT:    v_med3_u32 v0, v0, 12, 17
46; GFX10-NEXT:    s_setpc_b64 s[30:31]
47  %umax = call i32 @llvm.umax.i32(i32 12, i32 %a)
48  %umed = call i32 @llvm.umin.i32(i32 17, i32 %umax)
49  ret i32 %umed
50}
51
52define i32 @test_max_min_ValK1_K0_u32(i32 %a) {
53; GFX10-LABEL: test_max_min_ValK1_K0_u32:
54; GFX10:       ; %bb.0:
55; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
56; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
57; GFX10-NEXT:    v_med3_u32 v0, v0, 12, 17
58; GFX10-NEXT:    s_setpc_b64 s[30:31]
59  %umin = call i32 @llvm.umin.i32(i32 %a, i32 17)
60  %umed = call i32 @llvm.umax.i32(i32 %umin, i32 12)
61  ret i32 %umed
62}
63
64define i32 @test_max_min_K1Val_K0_u32(i32 %a) {
65; GFX10-LABEL: test_max_min_K1Val_K0_u32:
66; GFX10:       ; %bb.0:
67; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
68; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
69; GFX10-NEXT:    v_med3_u32 v0, v0, 12, 17
70; GFX10-NEXT:    s_setpc_b64 s[30:31]
71  %umin = call i32 @llvm.umin.i32(i32 17, i32 %a)
72  %umed = call i32 @llvm.umax.i32(i32 %umin, i32 12)
73  ret i32 %umed
74}
75
76define i32 @test_max_K0min_ValK1__u32(i32 %a) {
77; GFX10-LABEL: test_max_K0min_ValK1__u32:
78; GFX10:       ; %bb.0:
79; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
80; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
81; GFX10-NEXT:    v_med3_u32 v0, v0, 12, 17
82; GFX10-NEXT:    s_setpc_b64 s[30:31]
83  %umin = call i32 @llvm.umin.i32(i32 %a, i32 17)
84  %umed = call i32 @llvm.umax.i32(i32 12, i32 %umin)
85  ret i32 %umed
86}
87
88define i32 @test_max_K0min_K1Val__u32(i32 %a) {
89; GFX10-LABEL: test_max_K0min_K1Val__u32:
90; GFX10:       ; %bb.0:
91; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
92; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
93; GFX10-NEXT:    v_med3_u32 v0, v0, 12, 17
94; GFX10-NEXT:    s_setpc_b64 s[30:31]
95  %umin = call i32 @llvm.umin.i32(i32 17, i32 %a)
96  %umed = call i32 @llvm.umax.i32(i32 12, i32 %umin)
97  ret i32 %umed
98}
99
100define <2 x i16> @test_max_K0min_K1Val__v2u16(<2 x i16> %a) {
101; GFX10-LABEL: test_max_K0min_K1Val__v2u16:
102; GFX10:       ; %bb.0:
103; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
104; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
105; GFX10-NEXT:    v_pk_min_u16 v0, 17, v0 op_sel_hi:[0,1]
106; GFX10-NEXT:    v_pk_max_u16 v0, 12, v0 op_sel_hi:[0,1]
107; GFX10-NEXT:    s_setpc_b64 s[30:31]
108  %umin = call <2 x i16> @llvm.umin.v2i16(<2 x i16> <i16 17, i16 17>, <2 x i16> %a)
109  %umed = call <2 x i16> @llvm.umax.v2i16(<2 x i16> <i16 12, i16 12>, <2 x i16> %umin)
110  ret <2 x i16> %umed
111}
112
113define amdgpu_ps i32 @test_uniform_min_max(i32 inreg %a) {
114; GFX10-LABEL: test_uniform_min_max:
115; GFX10:       ; %bb.0:
116; GFX10-NEXT:    s_max_u32 s0, s2, 12
117; GFX10-NEXT:    s_min_u32 s0, s0, 17
118; GFX10-NEXT:    ; return to shader part epilog
119  %umax = call i32 @llvm.umax.i32(i32 %a, i32 12)
120  %umed = call i32 @llvm.umin.i32(i32 %umax, i32 17)
121  ret i32 %umed
122}
123
124declare i32 @llvm.umin.i32(i32, i32)
125declare i32 @llvm.umax.i32(i32, i32)
126declare <2 x i16> @llvm.umin.v2i16(<2 x i16>, <2 x i16>)
127declare <2 x i16> @llvm.umax.v2i16(<2 x i16>, <2 x i16>)
128