1# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass post-RA-sched  %s -o - | FileCheck %s
2
3# This tests a situation where a sub-register of a killed super-register operand
4# of V_MOVRELS happens to have an undef use later on. This leads to the post RA
5# scheduler adding additional implicit operands to the V_MOVRELS, which used
6# to fail machine instruction verification.
7
8--- |
9
10  define amdgpu_vs void @main(i32 %arg) { ret void }
11
12...
13---
14# CHECK-LABEL: name: main
15# CHECK-LABEL: bb.0:
16# CHECK: V_MOVRELS_B32_e32
17# CHECK: V_MAC_F32_e32
18
19name:            main
20tracksRegLiveness: true
21body:             |
22  bb.0:
23    $m0 = S_MOV_B32 undef $sgpr0
24    V_MOVRELD_B32_e32 undef $vgpr2, 0, implicit $m0, implicit $exec, implicit-def $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8, implicit undef $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8(tied-def 4)
25    $m0 = S_MOV_B32 undef $sgpr0
26    $vgpr1 = V_MOVRELS_B32_e32 undef $vgpr1, implicit $m0, implicit $exec, implicit killed $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8
27    $vgpr4 = nofpexcept V_MAC_F32_e32 undef $vgpr0, undef $vgpr0, undef $vgpr4, implicit $mode, implicit $exec
28    EXP_DONE 15, undef $vgpr0, killed $vgpr1, killed $vgpr4, undef $vgpr0, 0, 0, 12, implicit $exec
29    S_ENDPGM 0
30
31...
32