1; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32,MIPS32-EL %s 2; RUN: llc -march=mips -mcpu=mips32 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32,MIPS32-EB %s 3; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32,MIPS32-EL %s 4; RUN: llc -march=mips -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32,MIPS32-EB %s 5; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32R6,MIPS32R6-EL %s 6; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32R6,MIPS32R6-EB %s 7; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EL %s 8; RUN: llc -march=mips64 -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EB %s 9; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EL %s 10; RUN: llc -march=mips64 -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EB %s 11; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64R2-EL %s 12; RUN: llc -march=mips64 -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64R2-EB %s 13; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64R6 %s 14; RUN: llc -march=mips64 -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64R6 %s 15 16%struct.SLL = type { i64 } 17%struct.SI = type { i32 } 18%struct.SUI = type { i32 } 19 20@sll = common global %struct.SLL zeroinitializer, align 1 21@si = common global %struct.SI zeroinitializer, align 1 22@sui = common global %struct.SUI zeroinitializer, align 1 23 24define i32 @load_SI() nounwind readonly { 25entry: 26; ALL-LABEL: load_SI: 27 28; MIPS32-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) 29; MIPS32-EL: lwr $[[R0]], 0($[[R1]]) 30 31; MIPS32-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 32; MIPS32-EB: lwr $[[R0]], 3($[[R1]]) 33 34; MIPS32R6: lw $[[PTR:[0-9]+]], %got(si)( 35; MIPS32R6: lw $2, 0($[[PTR]]) 36 37; MIPS64-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) 38; MIPS64-EL: lwr $[[R0]], 0($[[R1]]) 39 40; MIPS64R2-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) 41; MIPS64R2-EL: lwr $[[R0]], 0($[[R1]]) 42 43; MIPS64-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 44; MIPS64-EB: lwr $[[R0]], 3($[[R1]]) 45 46; MIPS64R2-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 47; MIPS64R2-EB: lwr $[[R0]], 3($[[R1]]) 48 49; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(si)( 50; MIPS64R6: lw $2, 0($[[PTR]]) 51 52 %0 = load i32, i32* getelementptr inbounds (%struct.SI, %struct.SI* @si, i32 0, i32 0), align 1 53 ret i32 %0 54} 55 56define void @store_SI(i32 signext %a) nounwind { 57entry: 58; ALL-LABEL: store_SI: 59 60; MIPS32-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) 61; MIPS32-EL: swr $[[R0]], 0($[[R1]]) 62 63; MIPS32-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 64; MIPS32-EB: swr $[[R0]], 3($[[R1]]) 65 66; MIPS32R6: lw $[[PTR:[0-9]+]], %got(si)( 67; MIPS32R6: sw $4, 0($[[PTR]]) 68 69; MIPS64-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) 70; MIPS64-EL: swr $[[R0]], 0($[[R1]]) 71 72; MIPS64R2-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) 73; MIPS64R2-EL: swr $[[R0]], 0($[[R1]]) 74 75; MIPS64-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 76; MIPS64-EB: swr $[[R0]], 3($[[R1]]) 77 78; MIPS64R2-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 79; MIPS64R2-EB: swr $[[R0]], 3($[[R1]]) 80 81; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(si)( 82; MIPS64R6: sw $4, 0($[[PTR]]) 83 84 store i32 %a, i32* getelementptr inbounds (%struct.SI, %struct.SI* @si, i32 0, i32 0), align 1 85 ret void 86} 87 88define i64 @load_SLL() nounwind readonly { 89entry: 90; ALL-LABEL: load_SLL: 91 92; MIPS32-EL: lwl $2, 3($[[R1:[0-9]+]]) 93; MIPS32-EL: lwr $2, 0($[[R1]]) 94; MIPS32-EL: lwl $3, 7($[[R1:[0-9]+]]) 95; MIPS32-EL: lwr $3, 4($[[R1]]) 96 97; MIPS32-EB: lwl $2, 0($[[R1:[0-9]+]]) 98; MIPS32-EB: lwr $2, 3($[[R1]]) 99; MIPS32-EB: lwl $3, 4($[[R1:[0-9]+]]) 100; MIPS32-EB: lwr $3, 7($[[R1]]) 101 102; MIPS32R6: lw $[[PTR:[0-9]+]], %got(sll)( 103; MIPS32R6-DAG: lw $2, 0($[[PTR]]) 104; MIPS32R6-DAG: lw $3, 4($[[PTR]]) 105 106; MIPS64-EL: ldl $[[R0:[0-9]+]], 7($[[R1:[0-9]+]]) 107; MIPS64-EL: ldr $[[R0]], 0($[[R1]]) 108 109; MIPS64R2-EL: ldl $[[R0:[0-9]+]], 7($[[R1:[0-9]+]]) 110; MIPS64R2-EL: ldr $[[R0]], 0($[[R1]]) 111 112; MIPS64-EB: ldl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 113; MIPS64-EB: ldr $[[R0]], 7($[[R1]]) 114 115; MIPS64R2-EB: ldl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 116; MIPS64R2-EB: ldr $[[R0]], 7($[[R1]]) 117 118; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(sll)( 119; MIPS64R6: ld $2, 0($[[PTR]]) 120 121 %0 = load i64, i64* getelementptr inbounds (%struct.SLL, %struct.SLL* @sll, i64 0, i32 0), align 1 122 ret i64 %0 123} 124 125define i64 @load_SI_sext_to_i64() nounwind readonly { 126entry: 127; ALL-LABEL: load_SI_sext_to_i64: 128 129; MIPS32-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) 130; MIPS32-EL: lwr $[[R0]], 0($[[R1]]) 131 132; MIPS32-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 133; MIPS32-EB: lwr $[[R0]], 3($[[R1]]) 134 135; MIPS32R6: lw $[[PTR:[0-9]+]], %got(si)( 136; MIPS32R6-EL: lw $2, 0($[[PTR]]) 137; MIPS32R6-EL: sra $3, $2, 31 138; MIPS32R6-EB: lw $3, 0($[[PTR]]) 139; MIPS32R6-EB: sra $2, $3, 31 140 141; MIPS64-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) 142; MIPS64-EL: lwr $[[R0]], 0($[[R1]]) 143 144; MIPS64R2-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) 145; MIPS64R2-EL: lwr $[[R0]], 0($[[R1]]) 146 147; MIPS64-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 148; MIPS64-EB: lwr $[[R0]], 3($[[R1]]) 149 150; MIPS64R2-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 151; MIPS64R2-EB: lwr $[[R0]], 3($[[R1]]) 152 153; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(si)( 154; MIPS64R6: lw $2, 0($[[PTR]]) 155 156 %0 = load i32, i32* getelementptr inbounds (%struct.SI, %struct.SI* @si, i64 0, i32 0), align 1 157 %conv = sext i32 %0 to i64 158 ret i64 %conv 159} 160 161define i64 @load_UI() nounwind readonly { 162entry: 163; ALL-LABEL: load_UI: 164 165; MIPS32-EL-DAG: lwl $[[R2:2]], 3($[[R1:[0-9]+]]) 166; MIPS32-EL-DAG: lwr $[[R2]], 0($[[R1]]) 167; MIPS32-EL-DAG: addiu $3, $zero, 0 168 169; MIPS32-EB-DAG: lwl $[[R2:3]], 0($[[R1:[0-9]+]]) 170; MIPS32-EB-DAG: lwr $[[R2]], 3($[[R1]]) 171; MIPS32-EB-DAG: addiu $2, $zero, 0 172 173; MIPS32R6: lw $[[PTR:[0-9]+]], %got(sui)( 174; MIPS32R6-EL-DAG: lw $2, 0($[[PTR]]) 175; MIPS32R6-EL-DAG: addiu $3, $zero, 0 176; MIPS32R6-EB-DAG: lw $3, 0($[[PTR]]) 177; MIPS32R6-EB-DAG: addiu $2, $zero, 0 178 179; MIPS64-EL-DAG: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) 180; MIPS64-EL-DAG: lwr $[[R0]], 0($[[R1]]) 181; MIPS64-EL-DAG: daddiu $[[R2:[0-9]+]], $zero, 1 182; MIPS64-EL-DAG: dsll $[[R3:[0-9]+]], $[[R2]], 32 183; MIPS64-EL-DAG: daddiu $[[R4:[0-9]+]], $[[R3]], -1 184; MIPS64-EL-DAG: and ${{[0-9]+}}, $[[R0]], $[[R4]] 185 186; MIPS64R2-EL-DAG: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) 187; MIPS64R2-EL-DAG: lwr $[[R0]], 0($[[R1]]) 188; MIPS64R2-EL-DAG: dext $[[R0]], $[[R0]], 0, 32 189 190; MIPS64-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 191; MIPS64-EB: lwr $[[R0]], 3($[[R1]]) 192 193; MIPS64R2-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 194; MIPS64R2-EB: lwr $[[R0]], 3($[[R1]]) 195; MIPS64R2-EB: dext $[[R0]], $[[R0]], 0, 32 196 197; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(sui)( 198; MIPS64R6: lwu $2, 0($[[PTR]]) 199 200 %0 = load i32, i32* getelementptr inbounds (%struct.SUI, %struct.SUI* @sui, i64 0, i32 0), align 1 201 %conv = zext i32 %0 to i64 202 ret i64 %conv 203} 204 205define void @store_SLL(i64 %a) nounwind { 206entry: 207; ALL-LABEL: store_SLL: 208 209; MIPS32-EL-DAG: swl $[[A1:4]], 3($[[R1:[0-9]+]]) 210; MIPS32-EL-DAG: swr $[[A1]], 0($[[R1]]) 211; MIPS32-EL-DAG: swl $[[A2:5]], 7($[[R1:[0-9]+]]) 212; MIPS32-EL-DAG: swr $[[A2]], 4($[[R1]]) 213 214; MIPS32-EB-DAG: swl $[[A1:4]], 0($[[R1:[0-9]+]]) 215; MIPS32-EB-DAG: swr $[[A1]], 3($[[R1]]) 216; MIPS32-EB-DAG: swl $[[A1:5]], 4($[[R1:[0-9]+]]) 217; MIPS32-EB-DAG: swr $[[A1]], 7($[[R1]]) 218 219; MIPS32R6-DAG: lw $[[PTR:[0-9]+]], %got(sll)( 220; MIPS32R6-DAG: sw $4, 0($[[PTR]]) 221; MIPS32R6-DAG: sw $5, 4($[[PTR]]) 222 223; MIPS64-EL: sdl $[[R0:[0-9]+]], 7($[[R1:[0-9]+]]) 224; MIPS64-EL: sdr $[[R0]], 0($[[R1]]) 225 226; MIPS64R2-EL: sdl $[[R0:[0-9]+]], 7($[[R1:[0-9]+]]) 227; MIPS64R2-EL: sdr $[[R0]], 0($[[R1]]) 228 229; MIPS64-EB: sdl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 230; MIPS64-EB: sdr $[[R0]], 7($[[R1]]) 231 232; MIPS64R2-EB: sdl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 233; MIPS64R2-EB: sdr $[[R0]], 7($[[R1]]) 234 235; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(sll)( 236; MIPS64R6: sd $4, 0($[[PTR]]) 237 238 store i64 %a, i64* getelementptr inbounds (%struct.SLL, %struct.SLL* @sll, i64 0, i32 0), align 1 239 ret void 240} 241 242define void @store_SI_trunc_from_i64(i32 signext %a) nounwind { 243entry: 244; ALL-LABEL: store_SI_trunc_from_i64: 245 246; MIPS32-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) 247; MIPS32-EL: swr $[[R0]], 0($[[R1]]) 248 249; MIPS32-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 250; MIPS32-EB: swr $[[R0]], 3($[[R1]]) 251 252; MIPS32R6: lw $[[PTR:[0-9]+]], %got(si)( 253; MIPS32R6: sw $4, 0($[[PTR]]) 254 255; MIPS64-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) 256; MIPS64-EL: swr $[[R0]], 0($[[R1]]) 257 258; MIPS64R2-EL: swl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]]) 259; MIPS64R2-EL: swr $[[R0]], 0($[[R1]]) 260 261; MIPS64-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 262; MIPS64-EB: swr $[[R0]], 3($[[R1]]) 263 264; MIPS64R2-EB: swl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]]) 265; MIPS64R2-EB: swr $[[R0]], 3($[[R1]]) 266 267; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(si)( 268; MIPS64R6: sw $4, 0($[[PTR]]) 269 270 store i32 %a, i32* getelementptr inbounds (%struct.SI, %struct.SI* @si, i64 0, i32 0), align 1 271 ret void 272} 273 274; 275; Structures are simply concatenations of the members. They are unaffected by 276; endianness 277; 278 279%struct.S0 = type { i8, i8 } 280@struct_s0 = common global %struct.S0 zeroinitializer, align 1 281%struct.S1 = type { i16, i16 } 282@struct_s1 = common global %struct.S1 zeroinitializer, align 1 283%struct.S2 = type { i32, i32 } 284@struct_s2 = common global %struct.S2 zeroinitializer, align 1 285 286define void @copy_struct_S0() nounwind { 287entry: 288; ALL-LABEL: copy_struct_S0: 289 290; MIPS32-EL: lw $[[PTR:[0-9]+]], %got(struct_s0)( 291; MIPS32-EB: lw $[[PTR:[0-9]+]], %got(struct_s0)( 292; MIPS32R6: lw $[[PTR:[0-9]+]], %got(struct_s0)( 293; MIPS64-EL: ld $[[PTR:[0-9]+]], %got_disp(struct_s0)( 294; MIPS64R2-EL: ld $[[PTR:[0-9]+]], %got_disp(struct_s0)( 295; MIPS64-EB: ld $[[PTR:[0-9]+]], %got_disp(struct_s0)( 296; MIPS64R2-EB: ld $[[PTR:[0-9]+]], %got_disp(struct_s0)( 297; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(struct_s0)( 298 299; MIPS32-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]]) 300; MIPS32-DAG: sb $[[R1]], 2($[[PTR]]) 301; MIPS32-DAG: lbu $[[R2:[0-9]+]], 1($[[PTR]]) 302; MIPS32-DAG: sb $[[R2]], 3($[[PTR]]) 303 304; MIPS32R6: lhu $[[R1:[0-9]+]], 0($[[PTR]]) 305; MIPS32R6: sh $[[R1]], 2($[[PTR]]) 306 307; MIPS64-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]]) 308; MIPS64-DAG: sb $[[R1]], 2($[[PTR]]) 309; MIPS64-DAG: lbu $[[R2:[0-9]+]], 1($[[PTR]]) 310; MIPS64-DAG: sb $[[R2]], 3($[[PTR]]) 311 312 %0 = load %struct.S0, %struct.S0* getelementptr inbounds (%struct.S0, %struct.S0* @struct_s0, i32 0), align 1 313 store %struct.S0 %0, %struct.S0* getelementptr inbounds (%struct.S0, %struct.S0* @struct_s0, i32 1), align 1 314 ret void 315} 316 317define void @copy_struct_S1() nounwind { 318entry: 319; ALL-LABEL: copy_struct_S1: 320 321; MIPS32-EL: lw $[[PTR:[0-9]+]], %got(struct_s1)( 322; MIPS32-EB: lw $[[PTR:[0-9]+]], %got(struct_s1)( 323; MIPS32-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]]) 324; MIPS32-EL-DAG: lwr $[[R1]], 0($[[PTR]]) 325; MIPS32-EL-DAG: swl $[[R1]], 7($[[PTR]]) 326; MIPS32-EL-DAG: swr $[[R1]], 4($[[PTR]]) 327; MIPS32-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]]) 328; MIPS32-EB-DAG: lwr $[[R1]], 3($[[PTR]]) 329; MIPS32-EB-DAG: swl $[[R1]], 4($[[PTR]]) 330; MIPS32-EB-DAG: swr $[[R1]], 7($[[PTR]]) 331 332; MIPS32-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]]) 333; MIPS32-NOLEFTRIGHT-DAG: sb $[[R1]], 4($[[PTR]]) 334; MIPS32-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]]) 335; MIPS32-NOLEFTRIGHT-DAG: sb $[[R1]], 5($[[PTR]]) 336; MIPS32-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]]) 337; MIPS32-NOLEFTRIGHT-DAG: sb $[[R1]], 6($[[PTR]]) 338; MIPS32-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]]) 339; MIPS32-NOLEFTRIGHT-DAG: sb $[[R1]], 7($[[PTR]]) 340 341; MIPS32R6: lw $[[PTR:[0-9]+]], %got(struct_s1)( 342; MIPS32R6-DAG: lw $[[R1:[0-9]+]], 0($[[PTR]]) 343; MIPS32R6-DAG: sw $[[R1]], 4($[[PTR]]) 344 345; MIPS64-EL: ld $[[PTR:[0-9]+]], %got_disp(struct_s1)( 346; MIPS64R2-EL: ld $[[PTR:[0-9]+]], %got_disp(struct_s1)( 347; MIPS64-EB: ld $[[PTR:[0-9]+]], %got_disp(struct_s1)( 348; MIPS64R2-EB: ld $[[PTR:[0-9]+]], %got_disp(struct_s1)( 349 350; MIPS64-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]]) 351; MIPS64-EL-DAG: lwr $[[R1]], 0($[[PTR]]) 352; MIPS64-EL-DAG: swl $[[R1]], 7($[[PTR]]) 353; MIPS64-EL-DAG: swr $[[R1]], 4($[[PTR]]) 354 355; MIPS64R2-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]]) 356; MIPS64R2-EL-DAG: lwr $[[R1]], 0($[[PTR]]) 357; MIPS64R2-EL-DAG: swl $[[R1]], 7($[[PTR]]) 358; MIPS64R2-EL-DAG: swr $[[R1]], 4($[[PTR]]) 359 360; MIPS64-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]]) 361; MIPS64-EB-DAG: lwr $[[R1]], 3($[[PTR]]) 362; MIPS64-EB-DAG: swl $[[R1]], 4($[[PTR]]) 363; MIPS64-EB-DAG: swr $[[R1]], 7($[[PTR]]) 364 365; MIPS64R2-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]]) 366; MIPS64R2-EB-DAG: lwr $[[R1]], 3($[[PTR]]) 367; MIPS64R2-EB-DAG: swl $[[R1]], 4($[[PTR]]) 368; MIPS64R2-EB-DAG: swr $[[R1]], 7($[[PTR]]) 369 370; MIPS64-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]]) 371; MIPS64-NOLEFTRIGHT-DAG: sb $[[R1]], 4($[[PTR]]) 372; MIPS64-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]]) 373; MIPS64-NOLEFTRIGHT-DAG: sb $[[R1]], 5($[[PTR]]) 374; MIPS64-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]]) 375; MIPS64-NOLEFTRIGHT-DAG: sb $[[R1]], 6($[[PTR]]) 376; MIPS64-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]]) 377; MIPS64-NOLEFTRIGHT-DAG: sb $[[R1]], 7($[[PTR]]) 378 379; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(struct_s1)( 380; MIPS64R6-DAG: lw $[[R1:[0-9]+]], 0($[[PTR]]) 381; MIPS64R6-DAG: sw $[[R1]], 4($[[PTR]]) 382 383 %0 = load %struct.S1, %struct.S1* getelementptr inbounds (%struct.S1, %struct.S1* @struct_s1, i32 0), align 1 384 store %struct.S1 %0, %struct.S1* getelementptr inbounds (%struct.S1, %struct.S1* @struct_s1, i32 1), align 1 385 ret void 386} 387 388define void @copy_struct_S2() nounwind { 389entry: 390; ALL-LABEL: copy_struct_S2: 391 392; MIPS32-EL: lw $[[PTR:[0-9]+]], %got(struct_s2)( 393; MIPS32-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]]) 394; MIPS32-EL-DAG: lwr $[[R1]], 0($[[PTR]]) 395; MIPS32-EL-DAG: swl $[[R1]], 11($[[PTR]]) 396; MIPS32-EL-DAG: swr $[[R1]], 8($[[PTR]]) 397; MIPS32-EL-DAG: lwl $[[R1:[0-9]+]], 7($[[PTR]]) 398; MIPS32-EL-DAG: lwr $[[R1]], 4($[[PTR]]) 399; MIPS32-EL-DAG: swl $[[R1]], 15($[[PTR]]) 400; MIPS32-EL-DAG: swr $[[R1]], 12($[[PTR]]) 401 402; MIPS32-EB: lw $[[PTR:[0-9]+]], %got(struct_s2)( 403; MIPS32-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]]) 404; MIPS32-EB-DAG: lwr $[[R1]], 3($[[PTR]]) 405; MIPS32-EB-DAG: swl $[[R1]], 8($[[PTR]]) 406; MIPS32-EB-DAG: swr $[[R1]], 11($[[PTR]]) 407; MIPS32-EB-DAG: lwl $[[R1:[0-9]+]], 4($[[PTR]]) 408; MIPS32-EB-DAG: lwr $[[R1]], 7($[[PTR]]) 409; MIPS32-EB-DAG: swl $[[R1]], 12($[[PTR]]) 410; MIPS32-EB-DAG: swr $[[R1]], 15($[[PTR]]) 411 412; MIPS32R6: lw $[[PTR:[0-9]+]], %got(struct_s2)( 413; MIPS32R6-DAG: lw $[[R1:[0-9]+]], 0($[[PTR]]) 414; MIPS32R6-DAG: sw $[[R1]], 8($[[PTR]]) 415; MIPS32R6-DAG: lw $[[R1:[0-9]+]], 4($[[PTR]]) 416; MIPS32R6-DAG: sw $[[R1]], 12($[[PTR]]) 417 418; MIPS64-EL: ld $[[PTR:[0-9]+]], %got_disp(struct_s2)( 419 420; MIPS64-EL-DAG: ldl $[[R1:[0-9]+]], 7($[[PTR]]) 421; MIPS64-EL-DAG: ldr $[[R1]], 0($[[PTR]]) 422; MIPS64-EL-DAG: sdl $[[R1]], 15($[[PTR]]) 423; MIPS64-EL-DAG: sdr $[[R1]], 8($[[PTR]]) 424 425; MIPS64R2-EL: ld $[[PTR:[0-9]+]], %got_disp(struct_s2)( 426 427; MIPS64R2-EL-DAG: ldl $[[R1:[0-9]+]], 7($[[PTR]]) 428; MIPS64R2-EL-DAG: ldr $[[R1]], 0($[[PTR]]) 429; MIPS64R2-EL-DAG: sdl $[[R1]], 15($[[PTR]]) 430; MIPS64R2-EL-DAG: sdr $[[R1]], 8($[[PTR]]) 431 432; MIPS64-EB: ld $[[PTR:[0-9]+]], %got_disp(struct_s2)( 433; MIPS64-EB-DAG: ldl $[[R1:[0-9]+]], 0($[[PTR]]) 434; MIPS64-EB-DAG: ldr $[[R1]], 7($[[PTR]]) 435; MIPS64-EB-DAG: sdl $[[R1]], 8($[[PTR]]) 436; MIPS64-EB-DAG: sdr $[[R1]], 15($[[PTR]]) 437 438; MIPS64R2-EB: ld $[[PTR:[0-9]+]], %got_disp(struct_s2)( 439; MIPS64R2-EB-DAG: ldl $[[R1:[0-9]+]], 0($[[PTR]]) 440; MIPS64R2-EB-DAG: ldr $[[R1]], 7($[[PTR]]) 441; MIPS64R2-EB-DAG: sdl $[[R1]], 8($[[PTR]]) 442; MIPS64R2-EB-DAG: sdr $[[R1]], 15($[[PTR]]) 443 444; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(struct_s2)( 445; MIPS64R6-DAG: ld $[[R1:[0-9]+]], 0($[[PTR]]) 446; MIPS64R6-DAG: sd $[[R1]], 8($[[PTR]]) 447 448 %0 = load %struct.S2, %struct.S2* getelementptr inbounds (%struct.S2, %struct.S2* @struct_s2, i32 0), align 1 449 store %struct.S2 %0, %struct.S2* getelementptr inbounds (%struct.S2, %struct.S2* @struct_s2, i32 1), align 1 450 ret void 451} 452 453; 454; Arrays are simply concatenations of the members. They are unaffected by 455; endianness 456; 457 458@arr = common global [7 x i8] zeroinitializer, align 1 459 460define void @pass_array_byval() nounwind { 461entry: 462; ALL-LABEL: pass_array_byval: 463 464; MIPS32-EL: lw $[[SPTR:[0-9]+]], %got(arr)( 465; MIPS32-EL-DAG: lwl $[[R1:4]], 3($[[PTR]]) 466; MIPS32-EL-DAG: lwr $[[R1]], 0($[[PTR]]) 467; MIPS32-EL-DAG: lbu $[[R2:[0-9]+]], 4($[[PTR]]) 468; MIPS32-EL-DAG: lbu $[[R3:[0-9]+]], 5($[[PTR]]) 469; MIPS32-EL-DAG: sll $[[T0:[0-9]+]], $[[R3]], 8 470; MIPS32-EL-DAG: or $[[T1:[0-9]+]], $[[T0]], $[[R2]] 471; MIPS32-EL-DAG: lbu $[[R4:[0-9]+]], 6($[[PTR]]) 472; MIPS32-EL-DAG: sll $[[T2:[0-9]+]], $[[R4]], 16 473; MIPS32-EL-DAG: or $5, $[[T1]], $[[T2]] 474 475; MIPS32-EB: lw $[[SPTR:[0-9]+]], %got(arr)( 476; MIPS32-EB-DAG: lwl $[[R1:4]], 0($[[PTR]]) 477; MIPS32-EB-DAG: lwr $[[R1]], 3($[[PTR]]) 478; MIPS32-EB-DAG: lbu $[[R2:[0-9]+]], 5($[[PTR]]) 479; MIPS32-EB-DAG: lbu $[[R3:[0-9]+]], 4($[[PTR]]) 480; MIPS32-EB-DAG: sll $[[T0:[0-9]+]], $[[R3]], 8 481; MIPS32-EB-DAG: or $[[T1:[0-9]+]], $[[T0]], $[[R2]] 482; MIPS32-EB-DAG: sll $[[T1]], $[[T1]], 16 483; MIPS32-EB-DAG: lbu $[[R4:[0-9]+]], 6($[[PTR]]) 484; MIPS32-EB-DAG: sll $[[T2:[0-9]+]], $[[R4]], 8 485; MIPS32-EB-DAG: or $5, $[[T1]], $[[T2]] 486 487; MIPS32R6: lw $[[SPTR:[0-9]+]], %got(arr)( 488; MIPS32R6-DAG: lw $4, 0($[[PTR]]) 489; MIPS32R6-EL-DAG: lhu $[[R2:[0-9]+]], 4($[[PTR]]) 490; MIPS32R6-EL-DAG: lbu $[[R3:[0-9]+]], 6($[[PTR]]) 491; MIPS32R6-EL-DAG: sll $[[T0:[0-9]+]], $[[R3]], 16 492; MIPS32R6-EL-DAG: or $5, $[[R2]], $[[T0]] 493 494; MIPS32R6-EB-DAG: lhu $[[R2:[0-9]+]], 4($[[PTR]]) 495; MIPS32R6-EB-DAG: lbu $[[R3:[0-9]+]], 6($[[PTR]]) 496; MIPS32R6-EB-DAG: sll $[[T0:[0-9]+]], $[[R2]], 16 497; MIPS32R6-EB-DAG: or $5, $[[T0]], $[[R3]] 498 499; MIPS64-EL: ld $[[SPTR:[0-9]+]], %got_disp(arr)( 500; MIPS64-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]]) 501; MIPS64-EL-DAG: lwr $[[R1]], 0($[[PTR]]) 502 503; MIPS64R2-EL: ld $[[SPTR:[0-9]+]], %got_disp(arr)( 504; MIPS64R2-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]]) 505; MIPS64R2-EL-DAG: lwr $[[R1]], 0($[[PTR]]) 506 507; MIPS64-EB: ld $[[SPTR:[0-9]+]], %got_disp(arr)( 508; MIPS64-EB-DAG: lbu $[[R2:[0-9]+]], 5($[[PTR]]) 509; MIPS64-EB-DAG: lbu $[[R3:[0-9]+]], 4($[[PTR]]) 510; MIPS64-EB-DAG: dsll $[[T0:[0-9]+]], $[[R3]], 8 511; MIPS64-EB-DAG: or $[[T1:[0-9]+]], $[[T0]], $[[R2]] 512; MIPS64-EB-DAG: lbu $[[R4:[0-9]+]], 6($[[PTR]]) 513; MIPS64-EB-DAG: dsll $[[T1]], $[[T1]], 16 514; MIPS64-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]]) 515; MIPS64-EB-DAG: lwr $[[R1]], 3($[[PTR]]) 516; MIPS64-EB-DAG: dsll $[[R5:[0-9]+]], $[[R1]], 32 517; MIPS64-EB-DAG: or $[[T3:[0-9]+]], $[[R5]], $[[T1]] 518; MIPS64-EB-DAG: dsll $[[T4:[0-9]+]], $[[R4]], 8 519; MIPS64-EB-DAG: or $4, $[[T3]], $[[T4]] 520 521; MIPS64R2-EB: ld $[[SPTR:[0-9]+]], %got_disp(arr)( 522; MIPS64R2-EB-DAG: lbu $[[R1:[0-9]+]], 5($[[PTR]]) 523; MIPS64R2-EB-DAG: lbu $[[R2:[0-9]+]], 4($[[PTR]]) 524; MIPS64R2-EB-DAG: dsll $[[T0:[0-9]+]], $[[R2]], 8 525; MIPS64R2-EB-DAG: or $[[T1:[0-9]+]], $[[T0]], $[[R1]] 526; MIPS64R2-EB-DAG: dsll $[[T1]], $[[T1]], 16 527; MIPS64R2-EB-DAG: lwl $[[R3:[0-9]+]], 0($[[PTR]]) 528; MIPS64R2-EB-DAG: lwr $[[R3]], 3($[[PTR]]) 529; MIPS64R2-EB-DAG: dext $[[R3]], $[[R3]], 0, 32 530; MIPS64R2-EB-DAG: dsll $[[R3]], $[[R3]], 32 531; MIPS64R2-EB-DAG: or $[[T2:[0-9]+]], $[[R3]], $[[T1]] 532; MIPS64R2-EB-DAG: lbu $[[R4:[0-9]+]], 6($[[PTR]]) 533; MIPS64R2-EB-DAG: dsll $[[T3:[0-9]+]], $[[R4]], 8 534; MIPS64R2-EB-DAG: or $4, $[[T2]], $[[T3]] 535 536; MIPS64R6: ld $[[SPTR:[0-9]+]], %got_disp(arr)( 537 538 tail call void @extern_func([7 x i8]* byval([7 x i8]) @arr) nounwind 539 ret void 540} 541 542declare void @extern_func([7 x i8]* byval([7 x i8])) 543