1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=mipsel-unknown-linux-gnu   -mcpu=mips32   -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=32
3; RUN: llc < %s -mtriple=mipsel-unknown-linux-gnu   -mcpu=mips32r2 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=32R2
4; RUN: llc < %s -mtriple=mipsel-unknown-linux-gnu   -mcpu=mips32r6 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=32R6
5; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -mcpu=mips64   -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=64
6; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -mcpu=mips64r2 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=64R2
7; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -mcpu=mips64r6 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=64R6
8
9@d2 = external global double
10@d3 = external global double
11
12define i32 @i32_icmp_ne_i32_val(i32 signext %s, i32 signext %f0, i32 signext %f1) nounwind readnone {
13; 32-LABEL: i32_icmp_ne_i32_val:
14; 32:       # %bb.0: # %entry
15; 32-NEXT:    movn $5, $6, $4
16; 32-NEXT:    jr $ra
17; 32-NEXT:    move $2, $5
18;
19; 32R2-LABEL: i32_icmp_ne_i32_val:
20; 32R2:       # %bb.0: # %entry
21; 32R2-NEXT:    movn $5, $6, $4
22; 32R2-NEXT:    jr $ra
23; 32R2-NEXT:    move $2, $5
24;
25; 32R6-LABEL: i32_icmp_ne_i32_val:
26; 32R6:       # %bb.0: # %entry
27; 32R6-NEXT:    seleqz $1, $5, $4
28; 32R6-NEXT:    selnez $2, $6, $4
29; 32R6-NEXT:    jr $ra
30; 32R6-NEXT:    or $2, $2, $1
31;
32; 64-LABEL: i32_icmp_ne_i32_val:
33; 64:       # %bb.0: # %entry
34; 64-NEXT:    movn $5, $6, $4
35; 64-NEXT:    jr $ra
36; 64-NEXT:    move $2, $5
37;
38; 64R2-LABEL: i32_icmp_ne_i32_val:
39; 64R2:       # %bb.0: # %entry
40; 64R2-NEXT:    movn $5, $6, $4
41; 64R2-NEXT:    jr $ra
42; 64R2-NEXT:    move $2, $5
43;
44; 64R6-LABEL: i32_icmp_ne_i32_val:
45; 64R6:       # %bb.0: # %entry
46; 64R6-NEXT:    seleqz $1, $5, $4
47; 64R6-NEXT:    selnez $2, $6, $4
48; 64R6-NEXT:    jr $ra
49; 64R6-NEXT:    or $2, $2, $1
50entry:
51  %tobool = icmp ne i32 %s, 0
52  %cond = select i1 %tobool, i32 %f1, i32 %f0
53  ret i32 %cond
54}
55
56; FIXME: The sll works around an implementation detail in the code generator
57;        (setcc's result is i32 so bits 32-63 are undefined). It's not really
58;        needed.
59
60define i64 @i32_icmp_ne_i64_val(i32 signext %s, i64 %f0, i64 %f1) nounwind readnone {
61; 32-LABEL: i32_icmp_ne_i64_val:
62; 32:       # %bb.0: # %entry
63; 32-NEXT:    lw $1, 16($sp)
64; 32-NEXT:    movn $6, $1, $4
65; 32-NEXT:    lw $1, 20($sp)
66; 32-NEXT:    movn $7, $1, $4
67; 32-NEXT:    move $2, $6
68; 32-NEXT:    jr $ra
69; 32-NEXT:    move $3, $7
70;
71; 32R2-LABEL: i32_icmp_ne_i64_val:
72; 32R2:       # %bb.0: # %entry
73; 32R2-NEXT:    lw $1, 16($sp)
74; 32R2-NEXT:    movn $6, $1, $4
75; 32R2-NEXT:    lw $1, 20($sp)
76; 32R2-NEXT:    movn $7, $1, $4
77; 32R2-NEXT:    move $2, $6
78; 32R2-NEXT:    jr $ra
79; 32R2-NEXT:    move $3, $7
80;
81; 32R6-LABEL: i32_icmp_ne_i64_val:
82; 32R6:       # %bb.0: # %entry
83; 32R6-NEXT:    seleqz $1, $6, $4
84; 32R6-NEXT:    lw $2, 16($sp)
85; 32R6-NEXT:    selnez $2, $2, $4
86; 32R6-NEXT:    or $2, $2, $1
87; 32R6-NEXT:    seleqz $1, $7, $4
88; 32R6-NEXT:    lw $3, 20($sp)
89; 32R6-NEXT:    selnez $3, $3, $4
90; 32R6-NEXT:    jr $ra
91; 32R6-NEXT:    or $3, $3, $1
92;
93; 64-LABEL: i32_icmp_ne_i64_val:
94; 64:       # %bb.0: # %entry
95; 64-NEXT:    movn $5, $6, $4
96; 64-NEXT:    jr $ra
97; 64-NEXT:    move $2, $5
98;
99; 64R2-LABEL: i32_icmp_ne_i64_val:
100; 64R2:       # %bb.0: # %entry
101; 64R2-NEXT:    movn $5, $6, $4
102; 64R2-NEXT:    jr $ra
103; 64R2-NEXT:    move $2, $5
104;
105; 64R6-LABEL: i32_icmp_ne_i64_val:
106; 64R6:       # %bb.0: # %entry
107; 64R6-NEXT:    sll $1, $4, 0
108; 64R6-NEXT:    seleqz $2, $5, $1
109; 64R6-NEXT:    selnez $1, $6, $1
110; 64R6-NEXT:    jr $ra
111; 64R6-NEXT:    or $2, $1, $2
112entry:
113  %tobool = icmp ne i32 %s, 0
114  %cond = select i1 %tobool, i64 %f1, i64 %f0
115  ret i64 %cond
116}
117
118define i64 @i64_icmp_ne_i64_val(i64 %s, i64 %f0, i64 %f1) nounwind readnone {
119; 32-LABEL: i64_icmp_ne_i64_val:
120; 32:       # %bb.0: # %entry
121; 32-NEXT:    or $1, $4, $5
122; 32-NEXT:    lw $2, 16($sp)
123; 32-NEXT:    movn $6, $2, $1
124; 32-NEXT:    lw $2, 20($sp)
125; 32-NEXT:    movn $7, $2, $1
126; 32-NEXT:    move $2, $6
127; 32-NEXT:    jr $ra
128; 32-NEXT:    move $3, $7
129;
130; 32R2-LABEL: i64_icmp_ne_i64_val:
131; 32R2:       # %bb.0: # %entry
132; 32R2-NEXT:    or $1, $4, $5
133; 32R2-NEXT:    lw $2, 16($sp)
134; 32R2-NEXT:    movn $6, $2, $1
135; 32R2-NEXT:    lw $2, 20($sp)
136; 32R2-NEXT:    movn $7, $2, $1
137; 32R2-NEXT:    move $2, $6
138; 32R2-NEXT:    jr $ra
139; 32R2-NEXT:    move $3, $7
140;
141; 32R6-LABEL: i64_icmp_ne_i64_val:
142; 32R6:       # %bb.0: # %entry
143; 32R6-NEXT:    or $1, $4, $5
144; 32R6-NEXT:    seleqz $2, $6, $1
145; 32R6-NEXT:    lw $3, 16($sp)
146; 32R6-NEXT:    selnez $3, $3, $1
147; 32R6-NEXT:    or $2, $3, $2
148; 32R6-NEXT:    seleqz $3, $7, $1
149; 32R6-NEXT:    lw $4, 20($sp)
150; 32R6-NEXT:    selnez $1, $4, $1
151; 32R6-NEXT:    jr $ra
152; 32R6-NEXT:    or $3, $1, $3
153;
154; 64-LABEL: i64_icmp_ne_i64_val:
155; 64:       # %bb.0: # %entry
156; 64-NEXT:    movn $5, $6, $4
157; 64-NEXT:    jr $ra
158; 64-NEXT:    move $2, $5
159;
160; 64R2-LABEL: i64_icmp_ne_i64_val:
161; 64R2:       # %bb.0: # %entry
162; 64R2-NEXT:    movn $5, $6, $4
163; 64R2-NEXT:    jr $ra
164; 64R2-NEXT:    move $2, $5
165;
166; 64R6-LABEL: i64_icmp_ne_i64_val:
167; 64R6:       # %bb.0: # %entry
168; 64R6-NEXT:    seleqz $1, $5, $4
169; 64R6-NEXT:    selnez $2, $6, $4
170; 64R6-NEXT:    jr $ra
171; 64R6-NEXT:    or $2, $2, $1
172entry:
173  %tobool = icmp ne i64 %s, 0
174  %cond = select i1 %tobool, i64 %f1, i64 %f0
175  ret i64 %cond
176}
177
178define float @i32_icmp_ne_f32_val(i32 signext %s, float %f0, float %f1) nounwind readnone {
179; 32-LABEL: i32_icmp_ne_f32_val:
180; 32:       # %bb.0: # %entry
181; 32-NEXT:    mtc1 $6, $f0
182; 32-NEXT:    mtc1 $5, $f1
183; 32-NEXT:    jr $ra
184; 32-NEXT:    movn.s $f0, $f1, $4
185;
186; 32R2-LABEL: i32_icmp_ne_f32_val:
187; 32R2:       # %bb.0: # %entry
188; 32R2-NEXT:    mtc1 $6, $f0
189; 32R2-NEXT:    mtc1 $5, $f1
190; 32R2-NEXT:    jr $ra
191; 32R2-NEXT:    movn.s $f0, $f1, $4
192;
193; 32R6-LABEL: i32_icmp_ne_f32_val:
194; 32R6:       # %bb.0: # %entry
195; 32R6-NEXT:    sltu $1, $zero, $4
196; 32R6-NEXT:    negu $1, $1
197; 32R6-NEXT:    mtc1 $5, $f1
198; 32R6-NEXT:    mtc1 $6, $f2
199; 32R6-NEXT:    mtc1 $1, $f0
200; 32R6-NEXT:    jr $ra
201; 32R6-NEXT:    sel.s $f0, $f2, $f1
202;
203; 64-LABEL: i32_icmp_ne_f32_val:
204; 64:       # %bb.0: # %entry
205; 64-NEXT:    mov.s $f0, $f14
206; 64-NEXT:    jr $ra
207; 64-NEXT:    movn.s $f0, $f13, $4
208;
209; 64R2-LABEL: i32_icmp_ne_f32_val:
210; 64R2:       # %bb.0: # %entry
211; 64R2-NEXT:    mov.s $f0, $f14
212; 64R2-NEXT:    jr $ra
213; 64R2-NEXT:    movn.s $f0, $f13, $4
214;
215; 64R6-LABEL: i32_icmp_ne_f32_val:
216; 64R6:       # %bb.0: # %entry
217; 64R6-NEXT:    sltu $1, $zero, $4
218; 64R6-NEXT:    negu $1, $1
219; 64R6-NEXT:    mtc1 $1, $f0
220; 64R6-NEXT:    jr $ra
221; 64R6-NEXT:    sel.s $f0, $f14, $f13
222entry:
223  %tobool = icmp ne i32 %s, 0
224  %cond = select i1 %tobool, float %f0, float %f1
225  ret float %cond
226}
227
228define double @i32_icmp_ne_f64_val(i32 signext %s, double %f0, double %f1) nounwind readnone {
229; 32-LABEL: i32_icmp_ne_f64_val:
230; 32:       # %bb.0: # %entry
231; 32-NEXT:    mtc1 $6, $f2
232; 32-NEXT:    mtc1 $7, $f3
233; 32-NEXT:    ldc1 $f0, 16($sp)
234; 32-NEXT:    jr $ra
235; 32-NEXT:    movn.d $f0, $f2, $4
236;
237; 32R2-LABEL: i32_icmp_ne_f64_val:
238; 32R2:       # %bb.0: # %entry
239; 32R2-NEXT:    mtc1 $6, $f2
240; 32R2-NEXT:    mthc1 $7, $f2
241; 32R2-NEXT:    ldc1 $f0, 16($sp)
242; 32R2-NEXT:    jr $ra
243; 32R2-NEXT:    movn.d $f0, $f2, $4
244;
245; 32R6-LABEL: i32_icmp_ne_f64_val:
246; 32R6:       # %bb.0: # %entry
247; 32R6-NEXT:    mtc1 $6, $f1
248; 32R6-NEXT:    mthc1 $7, $f1
249; 32R6-NEXT:    sltu $1, $zero, $4
250; 32R6-NEXT:    negu $1, $1
251; 32R6-NEXT:    mtc1 $1, $f0
252; 32R6-NEXT:    ldc1 $f2, 16($sp)
253; 32R6-NEXT:    jr $ra
254; 32R6-NEXT:    sel.d $f0, $f2, $f1
255;
256; 64-LABEL: i32_icmp_ne_f64_val:
257; 64:       # %bb.0: # %entry
258; 64-NEXT:    mov.d $f0, $f14
259; 64-NEXT:    jr $ra
260; 64-NEXT:    movn.d $f0, $f13, $4
261;
262; 64R2-LABEL: i32_icmp_ne_f64_val:
263; 64R2:       # %bb.0: # %entry
264; 64R2-NEXT:    mov.d $f0, $f14
265; 64R2-NEXT:    jr $ra
266; 64R2-NEXT:    movn.d $f0, $f13, $4
267;
268; 64R6-LABEL: i32_icmp_ne_f64_val:
269; 64R6:       # %bb.0: # %entry
270; 64R6-NEXT:    sltu $1, $zero, $4
271; 64R6-NEXT:    negu $1, $1
272; 64R6-NEXT:    mtc1 $1, $f0
273; 64R6-NEXT:    jr $ra
274; 64R6-NEXT:    sel.d $f0, $f14, $f13
275entry:
276  %tobool = icmp ne i32 %s, 0
277  %cond = select i1 %tobool, double %f0, double %f1
278  ret double %cond
279}
280
281define float @f32_fcmp_oeq_f32_val(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
282; 32-LABEL: f32_fcmp_oeq_f32_val:
283; 32:       # %bb.0: # %entry
284; 32-NEXT:    mov.s $f0, $f14
285; 32-NEXT:    mtc1 $7, $f1
286; 32-NEXT:    mtc1 $6, $f2
287; 32-NEXT:    c.eq.s $f2, $f1
288; 32-NEXT:    jr $ra
289; 32-NEXT:    movt.s $f0, $f12, $fcc0
290;
291; 32R2-LABEL: f32_fcmp_oeq_f32_val:
292; 32R2:       # %bb.0: # %entry
293; 32R2-NEXT:    mov.s $f0, $f14
294; 32R2-NEXT:    mtc1 $7, $f1
295; 32R2-NEXT:    mtc1 $6, $f2
296; 32R2-NEXT:    c.eq.s $f2, $f1
297; 32R2-NEXT:    jr $ra
298; 32R2-NEXT:    movt.s $f0, $f12, $fcc0
299;
300; 32R6-LABEL: f32_fcmp_oeq_f32_val:
301; 32R6:       # %bb.0: # %entry
302; 32R6-NEXT:    mtc1 $7, $f0
303; 32R6-NEXT:    mtc1 $6, $f1
304; 32R6-NEXT:    cmp.eq.s $f0, $f1, $f0
305; 32R6-NEXT:    jr $ra
306; 32R6-NEXT:    sel.s $f0, $f14, $f12
307;
308; 64-LABEL: f32_fcmp_oeq_f32_val:
309; 64:       # %bb.0: # %entry
310; 64-NEXT:    mov.s $f0, $f13
311; 64-NEXT:    c.eq.s $f14, $f15
312; 64-NEXT:    jr $ra
313; 64-NEXT:    movt.s $f0, $f12, $fcc0
314;
315; 64R2-LABEL: f32_fcmp_oeq_f32_val:
316; 64R2:       # %bb.0: # %entry
317; 64R2-NEXT:    mov.s $f0, $f13
318; 64R2-NEXT:    c.eq.s $f14, $f15
319; 64R2-NEXT:    jr $ra
320; 64R2-NEXT:    movt.s $f0, $f12, $fcc0
321;
322; 64R6-LABEL: f32_fcmp_oeq_f32_val:
323; 64R6:       # %bb.0: # %entry
324; 64R6-NEXT:    cmp.eq.s $f0, $f14, $f15
325; 64R6-NEXT:    jr $ra
326; 64R6-NEXT:    sel.s $f0, $f13, $f12
327entry:
328  %cmp = fcmp oeq float %f2, %f3
329  %cond = select i1 %cmp, float %f0, float %f1
330  ret float %cond
331}
332
333define float @f32_fcmp_olt_f32_val(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
334; 32-LABEL: f32_fcmp_olt_f32_val:
335; 32:       # %bb.0: # %entry
336; 32-NEXT:    mov.s $f0, $f14
337; 32-NEXT:    mtc1 $7, $f1
338; 32-NEXT:    mtc1 $6, $f2
339; 32-NEXT:    c.olt.s $f2, $f1
340; 32-NEXT:    jr $ra
341; 32-NEXT:    movt.s $f0, $f12, $fcc0
342;
343; 32R2-LABEL: f32_fcmp_olt_f32_val:
344; 32R2:       # %bb.0: # %entry
345; 32R2-NEXT:    mov.s $f0, $f14
346; 32R2-NEXT:    mtc1 $7, $f1
347; 32R2-NEXT:    mtc1 $6, $f2
348; 32R2-NEXT:    c.olt.s $f2, $f1
349; 32R2-NEXT:    jr $ra
350; 32R2-NEXT:    movt.s $f0, $f12, $fcc0
351;
352; 32R6-LABEL: f32_fcmp_olt_f32_val:
353; 32R6:       # %bb.0: # %entry
354; 32R6-NEXT:    mtc1 $7, $f0
355; 32R6-NEXT:    mtc1 $6, $f1
356; 32R6-NEXT:    cmp.lt.s $f0, $f1, $f0
357; 32R6-NEXT:    jr $ra
358; 32R6-NEXT:    sel.s $f0, $f14, $f12
359;
360; 64-LABEL: f32_fcmp_olt_f32_val:
361; 64:       # %bb.0: # %entry
362; 64-NEXT:    mov.s $f0, $f13
363; 64-NEXT:    c.olt.s $f14, $f15
364; 64-NEXT:    jr $ra
365; 64-NEXT:    movt.s $f0, $f12, $fcc0
366;
367; 64R2-LABEL: f32_fcmp_olt_f32_val:
368; 64R2:       # %bb.0: # %entry
369; 64R2-NEXT:    mov.s $f0, $f13
370; 64R2-NEXT:    c.olt.s $f14, $f15
371; 64R2-NEXT:    jr $ra
372; 64R2-NEXT:    movt.s $f0, $f12, $fcc0
373;
374; 64R6-LABEL: f32_fcmp_olt_f32_val:
375; 64R6:       # %bb.0: # %entry
376; 64R6-NEXT:    cmp.lt.s $f0, $f14, $f15
377; 64R6-NEXT:    jr $ra
378; 64R6-NEXT:    sel.s $f0, $f13, $f12
379entry:
380  %cmp = fcmp olt float %f2, %f3
381  %cond = select i1 %cmp, float %f0, float %f1
382  ret float %cond
383}
384
385define float @f32_fcmp_ogt_f32_val(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
386; 32-LABEL: f32_fcmp_ogt_f32_val:
387; 32:       # %bb.0: # %entry
388; 32-NEXT:    mov.s $f0, $f14
389; 32-NEXT:    mtc1 $7, $f1
390; 32-NEXT:    mtc1 $6, $f2
391; 32-NEXT:    c.ule.s $f2, $f1
392; 32-NEXT:    jr $ra
393; 32-NEXT:    movf.s $f0, $f12, $fcc0
394;
395; 32R2-LABEL: f32_fcmp_ogt_f32_val:
396; 32R2:       # %bb.0: # %entry
397; 32R2-NEXT:    mov.s $f0, $f14
398; 32R2-NEXT:    mtc1 $7, $f1
399; 32R2-NEXT:    mtc1 $6, $f2
400; 32R2-NEXT:    c.ule.s $f2, $f1
401; 32R2-NEXT:    jr $ra
402; 32R2-NEXT:    movf.s $f0, $f12, $fcc0
403;
404; 32R6-LABEL: f32_fcmp_ogt_f32_val:
405; 32R6:       # %bb.0: # %entry
406; 32R6-NEXT:    mtc1 $6, $f0
407; 32R6-NEXT:    mtc1 $7, $f1
408; 32R6-NEXT:    cmp.lt.s $f0, $f1, $f0
409; 32R6-NEXT:    jr $ra
410; 32R6-NEXT:    sel.s $f0, $f14, $f12
411;
412; 64-LABEL: f32_fcmp_ogt_f32_val:
413; 64:       # %bb.0: # %entry
414; 64-NEXT:    mov.s $f0, $f13
415; 64-NEXT:    c.ule.s $f14, $f15
416; 64-NEXT:    jr $ra
417; 64-NEXT:    movf.s $f0, $f12, $fcc0
418;
419; 64R2-LABEL: f32_fcmp_ogt_f32_val:
420; 64R2:       # %bb.0: # %entry
421; 64R2-NEXT:    mov.s $f0, $f13
422; 64R2-NEXT:    c.ule.s $f14, $f15
423; 64R2-NEXT:    jr $ra
424; 64R2-NEXT:    movf.s $f0, $f12, $fcc0
425;
426; 64R6-LABEL: f32_fcmp_ogt_f32_val:
427; 64R6:       # %bb.0: # %entry
428; 64R6-NEXT:    cmp.lt.s $f0, $f15, $f14
429; 64R6-NEXT:    jr $ra
430; 64R6-NEXT:    sel.s $f0, $f13, $f12
431entry:
432  %cmp = fcmp ogt float %f2, %f3
433  %cond = select i1 %cmp, float %f0, float %f1
434  ret float %cond
435}
436
437define double @f32_fcmp_ogt_f64_val(double %f0, double %f1, float %f2, float %f3) nounwind readnone {
438; 32-LABEL: f32_fcmp_ogt_f64_val:
439; 32:       # %bb.0: # %entry
440; 32-NEXT:    mov.d $f0, $f14
441; 32-NEXT:    lwc1 $f2, 20($sp)
442; 32-NEXT:    lwc1 $f3, 16($sp)
443; 32-NEXT:    c.ule.s $f3, $f2
444; 32-NEXT:    jr $ra
445; 32-NEXT:    movf.d $f0, $f12, $fcc0
446;
447; 32R2-LABEL: f32_fcmp_ogt_f64_val:
448; 32R2:       # %bb.0: # %entry
449; 32R2-NEXT:    mov.d $f0, $f14
450; 32R2-NEXT:    lwc1 $f2, 20($sp)
451; 32R2-NEXT:    lwc1 $f3, 16($sp)
452; 32R2-NEXT:    c.ule.s $f3, $f2
453; 32R2-NEXT:    jr $ra
454; 32R2-NEXT:    movf.d $f0, $f12, $fcc0
455;
456; 32R6-LABEL: f32_fcmp_ogt_f64_val:
457; 32R6:       # %bb.0: # %entry
458; 32R6-NEXT:    lwc1 $f0, 16($sp)
459; 32R6-NEXT:    lwc1 $f1, 20($sp)
460; 32R6-NEXT:    cmp.lt.s $f0, $f1, $f0
461; 32R6-NEXT:    mfc1 $1, $f0
462; 32R6-NEXT:    mtc1 $1, $f0
463; 32R6-NEXT:    jr $ra
464; 32R6-NEXT:    sel.d $f0, $f14, $f12
465;
466; 64-LABEL: f32_fcmp_ogt_f64_val:
467; 64:       # %bb.0: # %entry
468; 64-NEXT:    mov.d $f0, $f13
469; 64-NEXT:    c.ule.s $f14, $f15
470; 64-NEXT:    jr $ra
471; 64-NEXT:    movf.d $f0, $f12, $fcc0
472;
473; 64R2-LABEL: f32_fcmp_ogt_f64_val:
474; 64R2:       # %bb.0: # %entry
475; 64R2-NEXT:    mov.d $f0, $f13
476; 64R2-NEXT:    c.ule.s $f14, $f15
477; 64R2-NEXT:    jr $ra
478; 64R2-NEXT:    movf.d $f0, $f12, $fcc0
479;
480; 64R6-LABEL: f32_fcmp_ogt_f64_val:
481; 64R6:       # %bb.0: # %entry
482; 64R6-NEXT:    cmp.lt.s $f0, $f15, $f14
483; 64R6-NEXT:    mfc1 $1, $f0
484; 64R6-NEXT:    mtc1 $1, $f0
485; 64R6-NEXT:    jr $ra
486; 64R6-NEXT:    sel.d $f0, $f13, $f12
487entry:
488  %cmp = fcmp ogt float %f2, %f3
489  %cond = select i1 %cmp, double %f0, double %f1
490  ret double %cond
491}
492
493define double @f64_fcmp_oeq_f64_val(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
494; 32-LABEL: f64_fcmp_oeq_f64_val:
495; 32:       # %bb.0: # %entry
496; 32-NEXT:    mov.d $f0, $f14
497; 32-NEXT:    ldc1 $f2, 24($sp)
498; 32-NEXT:    ldc1 $f4, 16($sp)
499; 32-NEXT:    c.eq.d $f4, $f2
500; 32-NEXT:    jr $ra
501; 32-NEXT:    movt.d $f0, $f12, $fcc0
502;
503; 32R2-LABEL: f64_fcmp_oeq_f64_val:
504; 32R2:       # %bb.0: # %entry
505; 32R2-NEXT:    mov.d $f0, $f14
506; 32R2-NEXT:    ldc1 $f2, 24($sp)
507; 32R2-NEXT:    ldc1 $f4, 16($sp)
508; 32R2-NEXT:    c.eq.d $f4, $f2
509; 32R2-NEXT:    jr $ra
510; 32R2-NEXT:    movt.d $f0, $f12, $fcc0
511;
512; 32R6-LABEL: f64_fcmp_oeq_f64_val:
513; 32R6:       # %bb.0: # %entry
514; 32R6-NEXT:    ldc1 $f0, 24($sp)
515; 32R6-NEXT:    ldc1 $f1, 16($sp)
516; 32R6-NEXT:    cmp.eq.d $f0, $f1, $f0
517; 32R6-NEXT:    mfc1 $1, $f0
518; 32R6-NEXT:    mtc1 $1, $f0
519; 32R6-NEXT:    jr $ra
520; 32R6-NEXT:    sel.d $f0, $f14, $f12
521;
522; 64-LABEL: f64_fcmp_oeq_f64_val:
523; 64:       # %bb.0: # %entry
524; 64-NEXT:    mov.d $f0, $f13
525; 64-NEXT:    c.eq.d $f14, $f15
526; 64-NEXT:    jr $ra
527; 64-NEXT:    movt.d $f0, $f12, $fcc0
528;
529; 64R2-LABEL: f64_fcmp_oeq_f64_val:
530; 64R2:       # %bb.0: # %entry
531; 64R2-NEXT:    mov.d $f0, $f13
532; 64R2-NEXT:    c.eq.d $f14, $f15
533; 64R2-NEXT:    jr $ra
534; 64R2-NEXT:    movt.d $f0, $f12, $fcc0
535;
536; 64R6-LABEL: f64_fcmp_oeq_f64_val:
537; 64R6:       # %bb.0: # %entry
538; 64R6-NEXT:    cmp.eq.d $f0, $f14, $f15
539; 64R6-NEXT:    mfc1 $1, $f0
540; 64R6-NEXT:    mtc1 $1, $f0
541; 64R6-NEXT:    jr $ra
542; 64R6-NEXT:    sel.d $f0, $f13, $f12
543entry:
544  %cmp = fcmp oeq double %f2, %f3
545  %cond = select i1 %cmp, double %f0, double %f1
546  ret double %cond
547}
548
549define double @f64_fcmp_olt_f64_val(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
550; 32-LABEL: f64_fcmp_olt_f64_val:
551; 32:       # %bb.0: # %entry
552; 32-NEXT:    mov.d $f0, $f14
553; 32-NEXT:    ldc1 $f2, 24($sp)
554; 32-NEXT:    ldc1 $f4, 16($sp)
555; 32-NEXT:    c.olt.d $f4, $f2
556; 32-NEXT:    jr $ra
557; 32-NEXT:    movt.d $f0, $f12, $fcc0
558;
559; 32R2-LABEL: f64_fcmp_olt_f64_val:
560; 32R2:       # %bb.0: # %entry
561; 32R2-NEXT:    mov.d $f0, $f14
562; 32R2-NEXT:    ldc1 $f2, 24($sp)
563; 32R2-NEXT:    ldc1 $f4, 16($sp)
564; 32R2-NEXT:    c.olt.d $f4, $f2
565; 32R2-NEXT:    jr $ra
566; 32R2-NEXT:    movt.d $f0, $f12, $fcc0
567;
568; 32R6-LABEL: f64_fcmp_olt_f64_val:
569; 32R6:       # %bb.0: # %entry
570; 32R6-NEXT:    ldc1 $f0, 24($sp)
571; 32R6-NEXT:    ldc1 $f1, 16($sp)
572; 32R6-NEXT:    cmp.lt.d $f0, $f1, $f0
573; 32R6-NEXT:    mfc1 $1, $f0
574; 32R6-NEXT:    mtc1 $1, $f0
575; 32R6-NEXT:    jr $ra
576; 32R6-NEXT:    sel.d $f0, $f14, $f12
577;
578; 64-LABEL: f64_fcmp_olt_f64_val:
579; 64:       # %bb.0: # %entry
580; 64-NEXT:    mov.d $f0, $f13
581; 64-NEXT:    c.olt.d $f14, $f15
582; 64-NEXT:    jr $ra
583; 64-NEXT:    movt.d $f0, $f12, $fcc0
584;
585; 64R2-LABEL: f64_fcmp_olt_f64_val:
586; 64R2:       # %bb.0: # %entry
587; 64R2-NEXT:    mov.d $f0, $f13
588; 64R2-NEXT:    c.olt.d $f14, $f15
589; 64R2-NEXT:    jr $ra
590; 64R2-NEXT:    movt.d $f0, $f12, $fcc0
591;
592; 64R6-LABEL: f64_fcmp_olt_f64_val:
593; 64R6:       # %bb.0: # %entry
594; 64R6-NEXT:    cmp.lt.d $f0, $f14, $f15
595; 64R6-NEXT:    mfc1 $1, $f0
596; 64R6-NEXT:    mtc1 $1, $f0
597; 64R6-NEXT:    jr $ra
598; 64R6-NEXT:    sel.d $f0, $f13, $f12
599entry:
600  %cmp = fcmp olt double %f2, %f3
601  %cond = select i1 %cmp, double %f0, double %f1
602  ret double %cond
603}
604
605define double @f64_fcmp_ogt_f64_val(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
606; 32-LABEL: f64_fcmp_ogt_f64_val:
607; 32:       # %bb.0: # %entry
608; 32-NEXT:    mov.d $f0, $f14
609; 32-NEXT:    ldc1 $f2, 24($sp)
610; 32-NEXT:    ldc1 $f4, 16($sp)
611; 32-NEXT:    c.ule.d $f4, $f2
612; 32-NEXT:    jr $ra
613; 32-NEXT:    movf.d $f0, $f12, $fcc0
614;
615; 32R2-LABEL: f64_fcmp_ogt_f64_val:
616; 32R2:       # %bb.0: # %entry
617; 32R2-NEXT:    mov.d $f0, $f14
618; 32R2-NEXT:    ldc1 $f2, 24($sp)
619; 32R2-NEXT:    ldc1 $f4, 16($sp)
620; 32R2-NEXT:    c.ule.d $f4, $f2
621; 32R2-NEXT:    jr $ra
622; 32R2-NEXT:    movf.d $f0, $f12, $fcc0
623;
624; 32R6-LABEL: f64_fcmp_ogt_f64_val:
625; 32R6:       # %bb.0: # %entry
626; 32R6-NEXT:    ldc1 $f0, 16($sp)
627; 32R6-NEXT:    ldc1 $f1, 24($sp)
628; 32R6-NEXT:    cmp.lt.d $f0, $f1, $f0
629; 32R6-NEXT:    mfc1 $1, $f0
630; 32R6-NEXT:    mtc1 $1, $f0
631; 32R6-NEXT:    jr $ra
632; 32R6-NEXT:    sel.d $f0, $f14, $f12
633;
634; 64-LABEL: f64_fcmp_ogt_f64_val:
635; 64:       # %bb.0: # %entry
636; 64-NEXT:    mov.d $f0, $f13
637; 64-NEXT:    c.ule.d $f14, $f15
638; 64-NEXT:    jr $ra
639; 64-NEXT:    movf.d $f0, $f12, $fcc0
640;
641; 64R2-LABEL: f64_fcmp_ogt_f64_val:
642; 64R2:       # %bb.0: # %entry
643; 64R2-NEXT:    mov.d $f0, $f13
644; 64R2-NEXT:    c.ule.d $f14, $f15
645; 64R2-NEXT:    jr $ra
646; 64R2-NEXT:    movf.d $f0, $f12, $fcc0
647;
648; 64R6-LABEL: f64_fcmp_ogt_f64_val:
649; 64R6:       # %bb.0: # %entry
650; 64R6-NEXT:    cmp.lt.d $f0, $f15, $f14
651; 64R6-NEXT:    mfc1 $1, $f0
652; 64R6-NEXT:    mtc1 $1, $f0
653; 64R6-NEXT:    jr $ra
654; 64R6-NEXT:    sel.d $f0, $f13, $f12
655entry:
656  %cmp = fcmp ogt double %f2, %f3
657  %cond = select i1 %cmp, double %f0, double %f1
658  ret double %cond
659}
660
661define float @f64_fcmp_ogt_f32_val(float %f0, float %f1, double %f2, double %f3) nounwind readnone {
662; 32-LABEL: f64_fcmp_ogt_f32_val:
663; 32:       # %bb.0: # %entry
664; 32-NEXT:    mov.s $f0, $f14
665; 32-NEXT:    mtc1 $6, $f2
666; 32-NEXT:    mtc1 $7, $f3
667; 32-NEXT:    ldc1 $f4, 16($sp)
668; 32-NEXT:    c.ule.d $f2, $f4
669; 32-NEXT:    jr $ra
670; 32-NEXT:    movf.s $f0, $f12, $fcc0
671;
672; 32R2-LABEL: f64_fcmp_ogt_f32_val:
673; 32R2:       # %bb.0: # %entry
674; 32R2-NEXT:    mov.s $f0, $f14
675; 32R2-NEXT:    mtc1 $6, $f2
676; 32R2-NEXT:    mthc1 $7, $f2
677; 32R2-NEXT:    ldc1 $f4, 16($sp)
678; 32R2-NEXT:    c.ule.d $f2, $f4
679; 32R2-NEXT:    jr $ra
680; 32R2-NEXT:    movf.s $f0, $f12, $fcc0
681;
682; 32R6-LABEL: f64_fcmp_ogt_f32_val:
683; 32R6:       # %bb.0: # %entry
684; 32R6-NEXT:    mtc1 $6, $f0
685; 32R6-NEXT:    mthc1 $7, $f0
686; 32R6-NEXT:    ldc1 $f1, 16($sp)
687; 32R6-NEXT:    cmp.lt.d $f0, $f1, $f0
688; 32R6-NEXT:    jr $ra
689; 32R6-NEXT:    sel.s $f0, $f14, $f12
690;
691; 64-LABEL: f64_fcmp_ogt_f32_val:
692; 64:       # %bb.0: # %entry
693; 64-NEXT:    mov.s $f0, $f13
694; 64-NEXT:    c.ule.d $f14, $f15
695; 64-NEXT:    jr $ra
696; 64-NEXT:    movf.s $f0, $f12, $fcc0
697;
698; 64R2-LABEL: f64_fcmp_ogt_f32_val:
699; 64R2:       # %bb.0: # %entry
700; 64R2-NEXT:    mov.s $f0, $f13
701; 64R2-NEXT:    c.ule.d $f14, $f15
702; 64R2-NEXT:    jr $ra
703; 64R2-NEXT:    movf.s $f0, $f12, $fcc0
704;
705; 64R6-LABEL: f64_fcmp_ogt_f32_val:
706; 64R6:       # %bb.0: # %entry
707; 64R6-NEXT:    cmp.lt.d $f0, $f15, $f14
708; 64R6-NEXT:    jr $ra
709; 64R6-NEXT:    sel.s $f0, $f13, $f12
710entry:
711  %cmp = fcmp ogt double %f2, %f3
712  %cond = select i1 %cmp, float %f0, float %f1
713  ret float %cond
714}
715
716define i32 @f32_fcmp_oeq_i32_val(i32 signext %f0, i32 signext %f1, float %f2, float %f3) nounwind readnone {
717; 32-LABEL: f32_fcmp_oeq_i32_val:
718; 32:       # %bb.0: # %entry
719; 32-NEXT:    mtc1 $7, $f0
720; 32-NEXT:    mtc1 $6, $f1
721; 32-NEXT:    c.eq.s $f1, $f0
722; 32-NEXT:    movt $5, $4, $fcc0
723; 32-NEXT:    jr $ra
724; 32-NEXT:    move $2, $5
725;
726; 32R2-LABEL: f32_fcmp_oeq_i32_val:
727; 32R2:       # %bb.0: # %entry
728; 32R2-NEXT:    mtc1 $7, $f0
729; 32R2-NEXT:    mtc1 $6, $f1
730; 32R2-NEXT:    c.eq.s $f1, $f0
731; 32R2-NEXT:    movt $5, $4, $fcc0
732; 32R2-NEXT:    jr $ra
733; 32R2-NEXT:    move $2, $5
734;
735; 32R6-LABEL: f32_fcmp_oeq_i32_val:
736; 32R6:       # %bb.0: # %entry
737; 32R6-NEXT:    mtc1 $7, $f0
738; 32R6-NEXT:    mtc1 $6, $f1
739; 32R6-NEXT:    cmp.eq.s $f0, $f1, $f0
740; 32R6-NEXT:    mfc1 $1, $f0
741; 32R6-NEXT:    andi $1, $1, 1
742; 32R6-NEXT:    seleqz $2, $5, $1
743; 32R6-NEXT:    selnez $1, $4, $1
744; 32R6-NEXT:    jr $ra
745; 32R6-NEXT:    or $2, $1, $2
746;
747; 64-LABEL: f32_fcmp_oeq_i32_val:
748; 64:       # %bb.0: # %entry
749; 64-NEXT:    c.eq.s $f14, $f15
750; 64-NEXT:    movt $5, $4, $fcc0
751; 64-NEXT:    jr $ra
752; 64-NEXT:    move $2, $5
753;
754; 64R2-LABEL: f32_fcmp_oeq_i32_val:
755; 64R2:       # %bb.0: # %entry
756; 64R2-NEXT:    c.eq.s $f14, $f15
757; 64R2-NEXT:    movt $5, $4, $fcc0
758; 64R2-NEXT:    jr $ra
759; 64R2-NEXT:    move $2, $5
760;
761; 64R6-LABEL: f32_fcmp_oeq_i32_val:
762; 64R6:       # %bb.0: # %entry
763; 64R6-NEXT:    cmp.eq.s $f0, $f14, $f15
764; 64R6-NEXT:    mfc1 $1, $f0
765; 64R6-NEXT:    andi $1, $1, 1
766; 64R6-NEXT:    seleqz $2, $5, $1
767; 64R6-NEXT:    selnez $1, $4, $1
768; 64R6-NEXT:    jr $ra
769; 64R6-NEXT:    or $2, $1, $2
770entry:
771  %cmp = fcmp oeq float %f2, %f3
772  %cond = select i1 %cmp, i32 %f0, i32 %f1
773  ret i32 %cond
774}
775
776define i32 @f32_fcmp_olt_i32_val(i32 signext %f0, i32 signext %f1, float %f2, float %f3) nounwind readnone {
777; 32-LABEL: f32_fcmp_olt_i32_val:
778; 32:       # %bb.0: # %entry
779; 32-NEXT:    mtc1 $7, $f0
780; 32-NEXT:    mtc1 $6, $f1
781; 32-NEXT:    c.olt.s $f1, $f0
782; 32-NEXT:    movt $5, $4, $fcc0
783; 32-NEXT:    jr $ra
784; 32-NEXT:    move $2, $5
785;
786; 32R2-LABEL: f32_fcmp_olt_i32_val:
787; 32R2:       # %bb.0: # %entry
788; 32R2-NEXT:    mtc1 $7, $f0
789; 32R2-NEXT:    mtc1 $6, $f1
790; 32R2-NEXT:    c.olt.s $f1, $f0
791; 32R2-NEXT:    movt $5, $4, $fcc0
792; 32R2-NEXT:    jr $ra
793; 32R2-NEXT:    move $2, $5
794;
795; 32R6-LABEL: f32_fcmp_olt_i32_val:
796; 32R6:       # %bb.0: # %entry
797; 32R6-NEXT:    mtc1 $7, $f0
798; 32R6-NEXT:    mtc1 $6, $f1
799; 32R6-NEXT:    cmp.lt.s $f0, $f1, $f0
800; 32R6-NEXT:    mfc1 $1, $f0
801; 32R6-NEXT:    andi $1, $1, 1
802; 32R6-NEXT:    seleqz $2, $5, $1
803; 32R6-NEXT:    selnez $1, $4, $1
804; 32R6-NEXT:    jr $ra
805; 32R6-NEXT:    or $2, $1, $2
806;
807; 64-LABEL: f32_fcmp_olt_i32_val:
808; 64:       # %bb.0: # %entry
809; 64-NEXT:    c.olt.s $f14, $f15
810; 64-NEXT:    movt $5, $4, $fcc0
811; 64-NEXT:    jr $ra
812; 64-NEXT:    move $2, $5
813;
814; 64R2-LABEL: f32_fcmp_olt_i32_val:
815; 64R2:       # %bb.0: # %entry
816; 64R2-NEXT:    c.olt.s $f14, $f15
817; 64R2-NEXT:    movt $5, $4, $fcc0
818; 64R2-NEXT:    jr $ra
819; 64R2-NEXT:    move $2, $5
820;
821; 64R6-LABEL: f32_fcmp_olt_i32_val:
822; 64R6:       # %bb.0: # %entry
823; 64R6-NEXT:    cmp.lt.s $f0, $f14, $f15
824; 64R6-NEXT:    mfc1 $1, $f0
825; 64R6-NEXT:    andi $1, $1, 1
826; 64R6-NEXT:    seleqz $2, $5, $1
827; 64R6-NEXT:    selnez $1, $4, $1
828; 64R6-NEXT:    jr $ra
829; 64R6-NEXT:    or $2, $1, $2
830entry:
831  %cmp = fcmp olt float %f2, %f3
832  %cond = select i1 %cmp, i32 %f0, i32 %f1
833  ret i32 %cond
834}
835
836define i32 @f32_fcmp_ogt_i32_val(i32 signext %f0, i32 signext %f1, float %f2, float %f3) nounwind readnone {
837; 32-LABEL: f32_fcmp_ogt_i32_val:
838; 32:       # %bb.0: # %entry
839; 32-NEXT:    mtc1 $7, $f0
840; 32-NEXT:    mtc1 $6, $f1
841; 32-NEXT:    c.ule.s $f1, $f0
842; 32-NEXT:    movf $5, $4, $fcc0
843; 32-NEXT:    jr $ra
844; 32-NEXT:    move $2, $5
845;
846; 32R2-LABEL: f32_fcmp_ogt_i32_val:
847; 32R2:       # %bb.0: # %entry
848; 32R2-NEXT:    mtc1 $7, $f0
849; 32R2-NEXT:    mtc1 $6, $f1
850; 32R2-NEXT:    c.ule.s $f1, $f0
851; 32R2-NEXT:    movf $5, $4, $fcc0
852; 32R2-NEXT:    jr $ra
853; 32R2-NEXT:    move $2, $5
854;
855; 32R6-LABEL: f32_fcmp_ogt_i32_val:
856; 32R6:       # %bb.0: # %entry
857; 32R6-NEXT:    mtc1 $6, $f0
858; 32R6-NEXT:    mtc1 $7, $f1
859; 32R6-NEXT:    cmp.lt.s $f0, $f1, $f0
860; 32R6-NEXT:    mfc1 $1, $f0
861; 32R6-NEXT:    andi $1, $1, 1
862; 32R6-NEXT:    seleqz $2, $5, $1
863; 32R6-NEXT:    selnez $1, $4, $1
864; 32R6-NEXT:    jr $ra
865; 32R6-NEXT:    or $2, $1, $2
866;
867; 64-LABEL: f32_fcmp_ogt_i32_val:
868; 64:       # %bb.0: # %entry
869; 64-NEXT:    c.ule.s $f14, $f15
870; 64-NEXT:    movf $5, $4, $fcc0
871; 64-NEXT:    jr $ra
872; 64-NEXT:    move $2, $5
873;
874; 64R2-LABEL: f32_fcmp_ogt_i32_val:
875; 64R2:       # %bb.0: # %entry
876; 64R2-NEXT:    c.ule.s $f14, $f15
877; 64R2-NEXT:    movf $5, $4, $fcc0
878; 64R2-NEXT:    jr $ra
879; 64R2-NEXT:    move $2, $5
880;
881; 64R6-LABEL: f32_fcmp_ogt_i32_val:
882; 64R6:       # %bb.0: # %entry
883; 64R6-NEXT:    cmp.lt.s $f0, $f15, $f14
884; 64R6-NEXT:    mfc1 $1, $f0
885; 64R6-NEXT:    andi $1, $1, 1
886; 64R6-NEXT:    seleqz $2, $5, $1
887; 64R6-NEXT:    selnez $1, $4, $1
888; 64R6-NEXT:    jr $ra
889; 64R6-NEXT:    or $2, $1, $2
890entry:
891  %cmp = fcmp ogt float %f2, %f3
892  %cond = select i1 %cmp, i32 %f0, i32 %f1
893  ret i32 %cond
894}
895
896define i32 @f64_fcmp_oeq_i32_val(i32 signext %f0, i32 signext %f1) nounwind readonly {
897; 32-LABEL: f64_fcmp_oeq_i32_val:
898; 32:       # %bb.0: # %entry
899; 32-NEXT:    lui $2, %hi(_gp_disp)
900; 32-NEXT:    addiu $2, $2, %lo(_gp_disp)
901; 32-NEXT:    addu $1, $2, $25
902; 32-NEXT:    lw $2, %got(d3)($1)
903; 32-NEXT:    ldc1 $f0, 0($2)
904; 32-NEXT:    lw $1, %got(d2)($1)
905; 32-NEXT:    ldc1 $f2, 0($1)
906; 32-NEXT:    c.eq.d $f2, $f0
907; 32-NEXT:    movt $5, $4, $fcc0
908; 32-NEXT:    jr $ra
909; 32-NEXT:    move $2, $5
910;
911; 32R2-LABEL: f64_fcmp_oeq_i32_val:
912; 32R2:       # %bb.0: # %entry
913; 32R2-NEXT:    lui $2, %hi(_gp_disp)
914; 32R2-NEXT:    addiu $2, $2, %lo(_gp_disp)
915; 32R2-NEXT:    addu $1, $2, $25
916; 32R2-NEXT:    lw $2, %got(d3)($1)
917; 32R2-NEXT:    ldc1 $f0, 0($2)
918; 32R2-NEXT:    lw $1, %got(d2)($1)
919; 32R2-NEXT:    ldc1 $f2, 0($1)
920; 32R2-NEXT:    c.eq.d $f2, $f0
921; 32R2-NEXT:    movt $5, $4, $fcc0
922; 32R2-NEXT:    jr $ra
923; 32R2-NEXT:    move $2, $5
924;
925; 32R6-LABEL: f64_fcmp_oeq_i32_val:
926; 32R6:       # %bb.0: # %entry
927; 32R6-NEXT:    lui $2, %hi(_gp_disp)
928; 32R6-NEXT:    addiu $2, $2, %lo(_gp_disp)
929; 32R6-NEXT:    addu $1, $2, $25
930; 32R6-NEXT:    lw $2, %got(d3)($1)
931; 32R6-NEXT:    ldc1 $f0, 0($2)
932; 32R6-NEXT:    lw $1, %got(d2)($1)
933; 32R6-NEXT:    ldc1 $f1, 0($1)
934; 32R6-NEXT:    cmp.eq.d $f0, $f1, $f0
935; 32R6-NEXT:    mfc1 $1, $f0
936; 32R6-NEXT:    andi $1, $1, 1
937; 32R6-NEXT:    seleqz $2, $5, $1
938; 32R6-NEXT:    selnez $1, $4, $1
939; 32R6-NEXT:    jr $ra
940; 32R6-NEXT:    or $2, $1, $2
941;
942; 64-LABEL: f64_fcmp_oeq_i32_val:
943; 64:       # %bb.0: # %entry
944; 64-NEXT:    lui $1, %hi(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
945; 64-NEXT:    daddu $1, $1, $25
946; 64-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
947; 64-NEXT:    ld $2, %got_disp(d3)($1)
948; 64-NEXT:    ldc1 $f0, 0($2)
949; 64-NEXT:    ld $1, %got_disp(d2)($1)
950; 64-NEXT:    ldc1 $f1, 0($1)
951; 64-NEXT:    c.eq.d $f1, $f0
952; 64-NEXT:    movt $5, $4, $fcc0
953; 64-NEXT:    jr $ra
954; 64-NEXT:    move $2, $5
955;
956; 64R2-LABEL: f64_fcmp_oeq_i32_val:
957; 64R2:       # %bb.0: # %entry
958; 64R2-NEXT:    lui $1, %hi(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
959; 64R2-NEXT:    daddu $1, $1, $25
960; 64R2-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
961; 64R2-NEXT:    ld $2, %got_disp(d3)($1)
962; 64R2-NEXT:    ldc1 $f0, 0($2)
963; 64R2-NEXT:    ld $1, %got_disp(d2)($1)
964; 64R2-NEXT:    ldc1 $f1, 0($1)
965; 64R2-NEXT:    c.eq.d $f1, $f0
966; 64R2-NEXT:    movt $5, $4, $fcc0
967; 64R2-NEXT:    jr $ra
968; 64R2-NEXT:    move $2, $5
969;
970; 64R6-LABEL: f64_fcmp_oeq_i32_val:
971; 64R6:       # %bb.0: # %entry
972; 64R6-NEXT:    lui $1, %hi(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
973; 64R6-NEXT:    daddu $1, $1, $25
974; 64R6-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
975; 64R6-NEXT:    ld $2, %got_disp(d3)($1)
976; 64R6-NEXT:    ldc1 $f0, 0($2)
977; 64R6-NEXT:    ld $1, %got_disp(d2)($1)
978; 64R6-NEXT:    ldc1 $f1, 0($1)
979; 64R6-NEXT:    cmp.eq.d $f0, $f1, $f0
980; 64R6-NEXT:    mfc1 $1, $f0
981; 64R6-NEXT:    andi $1, $1, 1
982; 64R6-NEXT:    seleqz $2, $5, $1
983; 64R6-NEXT:    selnez $1, $4, $1
984; 64R6-NEXT:    jr $ra
985; 64R6-NEXT:    or $2, $1, $2
986entry:
987  %tmp = load double, double* @d2, align 8
988  %tmp1 = load double, double* @d3, align 8
989  %cmp = fcmp oeq double %tmp, %tmp1
990  %cond = select i1 %cmp, i32 %f0, i32 %f1
991  ret i32 %cond
992}
993
994define i32 @f64_fcmp_olt_i32_val(i32 signext %f0, i32 signext %f1) nounwind readonly {
995; 32-LABEL: f64_fcmp_olt_i32_val:
996; 32:       # %bb.0: # %entry
997; 32-NEXT:    lui $2, %hi(_gp_disp)
998; 32-NEXT:    addiu $2, $2, %lo(_gp_disp)
999; 32-NEXT:    addu $1, $2, $25
1000; 32-NEXT:    lw $2, %got(d3)($1)
1001; 32-NEXT:    ldc1 $f0, 0($2)
1002; 32-NEXT:    lw $1, %got(d2)($1)
1003; 32-NEXT:    ldc1 $f2, 0($1)
1004; 32-NEXT:    c.olt.d $f2, $f0
1005; 32-NEXT:    movt $5, $4, $fcc0
1006; 32-NEXT:    jr $ra
1007; 32-NEXT:    move $2, $5
1008;
1009; 32R2-LABEL: f64_fcmp_olt_i32_val:
1010; 32R2:       # %bb.0: # %entry
1011; 32R2-NEXT:    lui $2, %hi(_gp_disp)
1012; 32R2-NEXT:    addiu $2, $2, %lo(_gp_disp)
1013; 32R2-NEXT:    addu $1, $2, $25
1014; 32R2-NEXT:    lw $2, %got(d3)($1)
1015; 32R2-NEXT:    ldc1 $f0, 0($2)
1016; 32R2-NEXT:    lw $1, %got(d2)($1)
1017; 32R2-NEXT:    ldc1 $f2, 0($1)
1018; 32R2-NEXT:    c.olt.d $f2, $f0
1019; 32R2-NEXT:    movt $5, $4, $fcc0
1020; 32R2-NEXT:    jr $ra
1021; 32R2-NEXT:    move $2, $5
1022;
1023; 32R6-LABEL: f64_fcmp_olt_i32_val:
1024; 32R6:       # %bb.0: # %entry
1025; 32R6-NEXT:    lui $2, %hi(_gp_disp)
1026; 32R6-NEXT:    addiu $2, $2, %lo(_gp_disp)
1027; 32R6-NEXT:    addu $1, $2, $25
1028; 32R6-NEXT:    lw $2, %got(d3)($1)
1029; 32R6-NEXT:    ldc1 $f0, 0($2)
1030; 32R6-NEXT:    lw $1, %got(d2)($1)
1031; 32R6-NEXT:    ldc1 $f1, 0($1)
1032; 32R6-NEXT:    cmp.lt.d $f0, $f1, $f0
1033; 32R6-NEXT:    mfc1 $1, $f0
1034; 32R6-NEXT:    andi $1, $1, 1
1035; 32R6-NEXT:    seleqz $2, $5, $1
1036; 32R6-NEXT:    selnez $1, $4, $1
1037; 32R6-NEXT:    jr $ra
1038; 32R6-NEXT:    or $2, $1, $2
1039;
1040; 64-LABEL: f64_fcmp_olt_i32_val:
1041; 64:       # %bb.0: # %entry
1042; 64-NEXT:    lui $1, %hi(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
1043; 64-NEXT:    daddu $1, $1, $25
1044; 64-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
1045; 64-NEXT:    ld $2, %got_disp(d3)($1)
1046; 64-NEXT:    ldc1 $f0, 0($2)
1047; 64-NEXT:    ld $1, %got_disp(d2)($1)
1048; 64-NEXT:    ldc1 $f1, 0($1)
1049; 64-NEXT:    c.olt.d $f1, $f0
1050; 64-NEXT:    movt $5, $4, $fcc0
1051; 64-NEXT:    jr $ra
1052; 64-NEXT:    move $2, $5
1053;
1054; 64R2-LABEL: f64_fcmp_olt_i32_val:
1055; 64R2:       # %bb.0: # %entry
1056; 64R2-NEXT:    lui $1, %hi(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
1057; 64R2-NEXT:    daddu $1, $1, $25
1058; 64R2-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
1059; 64R2-NEXT:    ld $2, %got_disp(d3)($1)
1060; 64R2-NEXT:    ldc1 $f0, 0($2)
1061; 64R2-NEXT:    ld $1, %got_disp(d2)($1)
1062; 64R2-NEXT:    ldc1 $f1, 0($1)
1063; 64R2-NEXT:    c.olt.d $f1, $f0
1064; 64R2-NEXT:    movt $5, $4, $fcc0
1065; 64R2-NEXT:    jr $ra
1066; 64R2-NEXT:    move $2, $5
1067;
1068; 64R6-LABEL: f64_fcmp_olt_i32_val:
1069; 64R6:       # %bb.0: # %entry
1070; 64R6-NEXT:    lui $1, %hi(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
1071; 64R6-NEXT:    daddu $1, $1, $25
1072; 64R6-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
1073; 64R6-NEXT:    ld $2, %got_disp(d3)($1)
1074; 64R6-NEXT:    ldc1 $f0, 0($2)
1075; 64R6-NEXT:    ld $1, %got_disp(d2)($1)
1076; 64R6-NEXT:    ldc1 $f1, 0($1)
1077; 64R6-NEXT:    cmp.lt.d $f0, $f1, $f0
1078; 64R6-NEXT:    mfc1 $1, $f0
1079; 64R6-NEXT:    andi $1, $1, 1
1080; 64R6-NEXT:    seleqz $2, $5, $1
1081; 64R6-NEXT:    selnez $1, $4, $1
1082; 64R6-NEXT:    jr $ra
1083; 64R6-NEXT:    or $2, $1, $2
1084entry:
1085  %tmp = load double, double* @d2, align 8
1086  %tmp1 = load double, double* @d3, align 8
1087  %cmp = fcmp olt double %tmp, %tmp1
1088  %cond = select i1 %cmp, i32 %f0, i32 %f1
1089  ret i32 %cond
1090}
1091
1092define i32 @f64_fcmp_ogt_i32_val(i32 signext %f0, i32 signext %f1) nounwind readonly {
1093; 32-LABEL: f64_fcmp_ogt_i32_val:
1094; 32:       # %bb.0: # %entry
1095; 32-NEXT:    lui $2, %hi(_gp_disp)
1096; 32-NEXT:    addiu $2, $2, %lo(_gp_disp)
1097; 32-NEXT:    addu $1, $2, $25
1098; 32-NEXT:    lw $2, %got(d3)($1)
1099; 32-NEXT:    ldc1 $f0, 0($2)
1100; 32-NEXT:    lw $1, %got(d2)($1)
1101; 32-NEXT:    ldc1 $f2, 0($1)
1102; 32-NEXT:    c.ule.d $f2, $f0
1103; 32-NEXT:    movf $5, $4, $fcc0
1104; 32-NEXT:    jr $ra
1105; 32-NEXT:    move $2, $5
1106;
1107; 32R2-LABEL: f64_fcmp_ogt_i32_val:
1108; 32R2:       # %bb.0: # %entry
1109; 32R2-NEXT:    lui $2, %hi(_gp_disp)
1110; 32R2-NEXT:    addiu $2, $2, %lo(_gp_disp)
1111; 32R2-NEXT:    addu $1, $2, $25
1112; 32R2-NEXT:    lw $2, %got(d3)($1)
1113; 32R2-NEXT:    ldc1 $f0, 0($2)
1114; 32R2-NEXT:    lw $1, %got(d2)($1)
1115; 32R2-NEXT:    ldc1 $f2, 0($1)
1116; 32R2-NEXT:    c.ule.d $f2, $f0
1117; 32R2-NEXT:    movf $5, $4, $fcc0
1118; 32R2-NEXT:    jr $ra
1119; 32R2-NEXT:    move $2, $5
1120;
1121; 32R6-LABEL: f64_fcmp_ogt_i32_val:
1122; 32R6:       # %bb.0: # %entry
1123; 32R6-NEXT:    lui $2, %hi(_gp_disp)
1124; 32R6-NEXT:    addiu $2, $2, %lo(_gp_disp)
1125; 32R6-NEXT:    addu $1, $2, $25
1126; 32R6-NEXT:    lw $2, %got(d2)($1)
1127; 32R6-NEXT:    ldc1 $f0, 0($2)
1128; 32R6-NEXT:    lw $1, %got(d3)($1)
1129; 32R6-NEXT:    ldc1 $f1, 0($1)
1130; 32R6-NEXT:    cmp.lt.d $f0, $f1, $f0
1131; 32R6-NEXT:    mfc1 $1, $f0
1132; 32R6-NEXT:    andi $1, $1, 1
1133; 32R6-NEXT:    seleqz $2, $5, $1
1134; 32R6-NEXT:    selnez $1, $4, $1
1135; 32R6-NEXT:    jr $ra
1136; 32R6-NEXT:    or $2, $1, $2
1137;
1138; 64-LABEL: f64_fcmp_ogt_i32_val:
1139; 64:       # %bb.0: # %entry
1140; 64-NEXT:    lui $1, %hi(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
1141; 64-NEXT:    daddu $1, $1, $25
1142; 64-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
1143; 64-NEXT:    ld $2, %got_disp(d3)($1)
1144; 64-NEXT:    ldc1 $f0, 0($2)
1145; 64-NEXT:    ld $1, %got_disp(d2)($1)
1146; 64-NEXT:    ldc1 $f1, 0($1)
1147; 64-NEXT:    c.ule.d $f1, $f0
1148; 64-NEXT:    movf $5, $4, $fcc0
1149; 64-NEXT:    jr $ra
1150; 64-NEXT:    move $2, $5
1151;
1152; 64R2-LABEL: f64_fcmp_ogt_i32_val:
1153; 64R2:       # %bb.0: # %entry
1154; 64R2-NEXT:    lui $1, %hi(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
1155; 64R2-NEXT:    daddu $1, $1, $25
1156; 64R2-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
1157; 64R2-NEXT:    ld $2, %got_disp(d3)($1)
1158; 64R2-NEXT:    ldc1 $f0, 0($2)
1159; 64R2-NEXT:    ld $1, %got_disp(d2)($1)
1160; 64R2-NEXT:    ldc1 $f1, 0($1)
1161; 64R2-NEXT:    c.ule.d $f1, $f0
1162; 64R2-NEXT:    movf $5, $4, $fcc0
1163; 64R2-NEXT:    jr $ra
1164; 64R2-NEXT:    move $2, $5
1165;
1166; 64R6-LABEL: f64_fcmp_ogt_i32_val:
1167; 64R6:       # %bb.0: # %entry
1168; 64R6-NEXT:    lui $1, %hi(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
1169; 64R6-NEXT:    daddu $1, $1, $25
1170; 64R6-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
1171; 64R6-NEXT:    ld $2, %got_disp(d2)($1)
1172; 64R6-NEXT:    ldc1 $f0, 0($2)
1173; 64R6-NEXT:    ld $1, %got_disp(d3)($1)
1174; 64R6-NEXT:    ldc1 $f1, 0($1)
1175; 64R6-NEXT:    cmp.lt.d $f0, $f1, $f0
1176; 64R6-NEXT:    mfc1 $1, $f0
1177; 64R6-NEXT:    andi $1, $1, 1
1178; 64R6-NEXT:    seleqz $2, $5, $1
1179; 64R6-NEXT:    selnez $1, $4, $1
1180; 64R6-NEXT:    jr $ra
1181; 64R6-NEXT:    or $2, $1, $2
1182entry:
1183  %tmp = load double, double* @d2, align 8
1184  %tmp1 = load double, double* @d3, align 8
1185  %cmp = fcmp ogt double %tmp, %tmp1
1186  %cond = select i1 %cmp, i32 %f0, i32 %f1
1187  ret i32 %cond
1188}
1189