1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s
3
4define arm_aapcs_vfpcc <4 x i32> @vmulqr_v4i32(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
5; CHECK-LABEL: vmulqr_v4i32:
6; CHECK:       @ %bb.0: @ %entry
7; CHECK-NEXT:    vmul.i32 q0, q0, r0
8; CHECK-NEXT:    bx lr
9entry:
10  %i = insertelement <4 x i32> undef, i32 %src2, i32 0
11  %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
12  %c = mul <4 x i32> %src, %sp
13  ret <4 x i32> %c
14}
15
16define arm_aapcs_vfpcc <8 x i16> @vmulqr_v8i16(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
17; CHECK-LABEL: vmulqr_v8i16:
18; CHECK:       @ %bb.0: @ %entry
19; CHECK-NEXT:    vmul.i16 q0, q0, r0
20; CHECK-NEXT:    bx lr
21entry:
22  %i = insertelement <8 x i16> undef, i16 %src2, i32 0
23  %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
24  %c = mul <8 x i16> %src, %sp
25  ret <8 x i16> %c
26}
27
28define arm_aapcs_vfpcc <16 x i8> @vmulqr_v16i8(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
29; CHECK-LABEL: vmulqr_v16i8:
30; CHECK:       @ %bb.0: @ %entry
31; CHECK-NEXT:    vmul.i8 q0, q0, r0
32; CHECK-NEXT:    bx lr
33entry:
34  %i = insertelement <16 x i8> undef, i8 %src2, i32 0
35  %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
36  %c = mul <16 x i8> %src, %sp
37  ret <16 x i8> %c
38}
39
40define arm_aapcs_vfpcc <4 x i32> @vmulqr_v4i32_2(<4 x i32> %src, i32 %src2, <4 x i32> %a, <4 x i32> %b) {
41; CHECK-LABEL: vmulqr_v4i32_2:
42; CHECK:       @ %bb.0: @ %entry
43; CHECK-NEXT:    vmul.i32 q0, q0, r0
44; CHECK-NEXT:    bx lr
45entry:
46  %i = insertelement <4 x i32> undef, i32 %src2, i32 0
47  %sp = shufflevector <4 x i32> %i, <4 x i32> undef, <4 x i32> zeroinitializer
48  %c = mul <4 x i32> %sp, %src
49  ret <4 x i32> %c
50}
51
52define arm_aapcs_vfpcc <8 x i16> @vmulqr_v8i16_2(<8 x i16> %src, i16 %src2, <8 x i16> %a, <8 x i16> %b) {
53; CHECK-LABEL: vmulqr_v8i16_2:
54; CHECK:       @ %bb.0: @ %entry
55; CHECK-NEXT:    vmul.i16 q0, q0, r0
56; CHECK-NEXT:    bx lr
57entry:
58  %i = insertelement <8 x i16> undef, i16 %src2, i32 0
59  %sp = shufflevector <8 x i16> %i, <8 x i16> undef, <8 x i32> zeroinitializer
60  %c = mul <8 x i16> %sp, %src
61  ret <8 x i16> %c
62}
63
64define arm_aapcs_vfpcc <16 x i8> @vmulqr_v16i8_2(<16 x i8> %src, i8 %src2, <16 x i8> %a, <16 x i8> %b) {
65; CHECK-LABEL: vmulqr_v16i8_2:
66; CHECK:       @ %bb.0: @ %entry
67; CHECK-NEXT:    vmul.i8 q0, q0, r0
68; CHECK-NEXT:    bx lr
69entry:
70  %i = insertelement <16 x i8> undef, i8 %src2, i32 0
71  %sp = shufflevector <16 x i8> %i, <16 x i8> undef, <16 x i32> zeroinitializer
72  %c = mul <16 x i8> %sp, %src
73  ret <16 x i8> %c
74}
75