1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=thumbv7m-none-eabi -mcpu=cortex-m7 | FileCheck %s --check-prefix=CHECK
3; RUN: llc < %s -mtriple=thumbv7m-none-eabi -mcpu=cortex-m7 -arm-data-bank-mask=-1 | FileCheck %s --check-prefix=NOBANK
4
5; This tests the cortex-m7 bank conflict hazard recognizer.
6; Normally both loads would be scheduled early (both in the first cycle) due to
7; their latency. But will bank conflict to TCM so are scheduled in different
8; cycles.
9
10define i32 @test(i32* %x0, i32 %y, i32 %z) {
11; CHECK-LABEL: test:
12; CHECK:       @ %bb.0: @ %entry
13; CHECK-NEXT:    ldr r3, [r0]
14; CHECK-NEXT:    subs r1, r3, r1
15; CHECK-NEXT:    ldr r0, [r0, #8]
16; CHECK-NEXT:    subs r1, r1, r2
17; CHECK-NEXT:    adds r1, #1
18; CHECK-NEXT:    muls r0, r1, r0
19; CHECK-NEXT:    bx lr
20; NOBANK-LABEL: test:
21; NOBANK:       @ %bb.0: @ %entry
22; NOBANK-NEXT:    ldr r3, [r0]
23; NOBANK-NEXT:    ldr r0, [r0, #8]
24; NOBANK-NEXT:    subs r1, r3, r1
25; NOBANK-NEXT:    subs r1, r1, r2
26; NOBANK-NEXT:    adds r1, #1
27; NOBANK-NEXT:    muls r0, r1, r0
28; NOBANK-NEXT:    bx lr
29entry:
30  %0 = load i32, i32* %x0, align 4
31  %mul3 = add nsw i32 %0, 1
32  %mul = sub nsw i32 %mul3, %y
33  %sub = sub nsw i32 %mul, %z
34  %arrayidx1 = getelementptr inbounds i32, i32* %x0, i32 2
35  %1 = load i32, i32* %arrayidx1, align 4
36  %mul2 = mul nsw i32 %sub, %1
37  ret i32 %mul2
38}
39