1 //===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the X86 Disassembler Emitter. 10 // It contains the interface of a single recognizable instruction. 11 // Documentation for the disassembler emitter in general can be found in 12 // X86DisassemblerEmitter.h. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H 17 #define LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H 18 19 #include "CodeGenTarget.h" 20 #include "X86DisassemblerTables.h" 21 #include "llvm/Support/DataTypes.h" 22 #include "llvm/TableGen/Record.h" 23 24 namespace llvm { 25 26 #define X86_INSTR_MRM_MAPPING \ 27 MAP(C0, 64) \ 28 MAP(C1, 65) \ 29 MAP(C2, 66) \ 30 MAP(C3, 67) \ 31 MAP(C4, 68) \ 32 MAP(C5, 69) \ 33 MAP(C6, 70) \ 34 MAP(C7, 71) \ 35 MAP(C8, 72) \ 36 MAP(C9, 73) \ 37 MAP(CA, 74) \ 38 MAP(CB, 75) \ 39 MAP(CC, 76) \ 40 MAP(CD, 77) \ 41 MAP(CE, 78) \ 42 MAP(CF, 79) \ 43 MAP(D0, 80) \ 44 MAP(D1, 81) \ 45 MAP(D2, 82) \ 46 MAP(D3, 83) \ 47 MAP(D4, 84) \ 48 MAP(D5, 85) \ 49 MAP(D6, 86) \ 50 MAP(D7, 87) \ 51 MAP(D8, 88) \ 52 MAP(D9, 89) \ 53 MAP(DA, 90) \ 54 MAP(DB, 91) \ 55 MAP(DC, 92) \ 56 MAP(DD, 93) \ 57 MAP(DE, 94) \ 58 MAP(DF, 95) \ 59 MAP(E0, 96) \ 60 MAP(E1, 97) \ 61 MAP(E2, 98) \ 62 MAP(E3, 99) \ 63 MAP(E4, 100) \ 64 MAP(E5, 101) \ 65 MAP(E6, 102) \ 66 MAP(E7, 103) \ 67 MAP(E8, 104) \ 68 MAP(E9, 105) \ 69 MAP(EA, 106) \ 70 MAP(EB, 107) \ 71 MAP(EC, 108) \ 72 MAP(ED, 109) \ 73 MAP(EE, 110) \ 74 MAP(EF, 111) \ 75 MAP(F0, 112) \ 76 MAP(F1, 113) \ 77 MAP(F2, 114) \ 78 MAP(F3, 115) \ 79 MAP(F4, 116) \ 80 MAP(F5, 117) \ 81 MAP(F6, 118) \ 82 MAP(F7, 119) \ 83 MAP(F8, 120) \ 84 MAP(F9, 121) \ 85 MAP(FA, 122) \ 86 MAP(FB, 123) \ 87 MAP(FC, 124) \ 88 MAP(FD, 125) \ 89 MAP(FE, 126) \ 90 MAP(FF, 127) 91 92 // A clone of X86 since we can't depend on something that is generated. 93 namespace X86Local { 94 enum { 95 Pseudo = 0, 96 RawFrm = 1, 97 AddRegFrm = 2, 98 RawFrmMemOffs = 3, 99 RawFrmSrc = 4, 100 RawFrmDst = 5, 101 RawFrmDstSrc = 6, 102 RawFrmImm8 = 7, 103 RawFrmImm16 = 8, 104 AddCCFrm = 9, 105 PrefixByte = 10, 106 MRMr0 = 21, 107 MRMSrcMemFSIB = 22, 108 MRMDestMemFSIB = 23, 109 MRMDestMem = 24, 110 MRMSrcMem = 25, 111 MRMSrcMem4VOp3 = 26, 112 MRMSrcMemOp4 = 27, 113 MRMSrcMemCC = 28, 114 MRMXmCC = 30, MRMXm = 31, 115 MRM0m = 32, MRM1m = 33, MRM2m = 34, MRM3m = 35, 116 MRM4m = 36, MRM5m = 37, MRM6m = 38, MRM7m = 39, 117 MRMDestReg = 40, 118 MRMSrcReg = 41, 119 MRMSrcReg4VOp3 = 42, 120 MRMSrcRegOp4 = 43, 121 MRMSrcRegCC = 44, 122 MRMXrCC = 46, MRMXr = 47, 123 MRM0r = 48, MRM1r = 49, MRM2r = 50, MRM3r = 51, 124 MRM4r = 52, MRM5r = 53, MRM6r = 54, MRM7r = 55, 125 MRM0X = 56, MRM1X = 57, MRM2X = 58, MRM3X = 59, 126 MRM4X = 60, MRM5X = 61, MRM6X = 62, MRM7X = 63, 127 #define MAP(from, to) MRM_##from = to, 128 X86_INSTR_MRM_MAPPING 129 #undef MAP 130 }; 131 132 enum { 133 OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6, ThreeDNow = 7, 134 T_MAP5 = 8, T_MAP6 = 9 135 }; 136 137 enum { 138 PD = 1, XS = 2, XD = 3, PS = 4 139 }; 140 141 enum { 142 VEX = 1, XOP = 2, EVEX = 3 143 }; 144 145 enum { 146 OpSize16 = 1, OpSize32 = 2 147 }; 148 149 enum { 150 AdSize16 = 1, AdSize32 = 2, AdSize64 = 3 151 }; 152 } 153 154 namespace X86Disassembler { 155 156 /// RecognizableInstr - Encapsulates all information required to decode a single 157 /// instruction, as extracted from the LLVM instruction tables. Has methods 158 /// to interpret the information available in the LLVM tables, and to emit the 159 /// instruction into DisassemblerTables. 160 class RecognizableInstr { 161 private: 162 /// The opcode of the instruction, as used in an MCInst 163 InstrUID UID; 164 /// The record from the .td files corresponding to this instruction 165 const Record* Rec; 166 /// The OpPrefix field from the record 167 uint8_t OpPrefix; 168 /// The OpMap field from the record 169 uint8_t OpMap; 170 /// The opcode field from the record; this is the opcode used in the Intel 171 /// encoding and therefore distinct from the UID 172 uint8_t Opcode; 173 /// The form field from the record 174 uint8_t Form; 175 // The encoding field from the record 176 uint8_t Encoding; 177 /// The OpSize field from the record 178 uint8_t OpSize; 179 /// The AdSize field from the record 180 uint8_t AdSize; 181 /// The hasREX_WPrefix field from the record 182 bool HasREX_WPrefix; 183 /// The hasVEX_4V field from the record 184 bool HasVEX_4V; 185 /// The HasVEX_WPrefix field from the record 186 bool HasVEX_W; 187 /// The IgnoresVEX_W field from the record 188 bool IgnoresVEX_W; 189 /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set 190 bool HasVEX_LPrefix; 191 /// The ignoreVEX_L field from the record 192 bool IgnoresVEX_L; 193 /// The hasEVEX_L2Prefix field from the record 194 bool HasEVEX_L2Prefix; 195 /// The hasEVEX_K field from the record 196 bool HasEVEX_K; 197 /// The hasEVEX_KZ field from the record 198 bool HasEVEX_KZ; 199 /// The hasEVEX_B field from the record 200 bool HasEVEX_B; 201 /// Indicates that the instruction uses the L and L' fields for RC. 202 bool EncodeRC; 203 /// The isCodeGenOnly field from the record 204 bool IsCodeGenOnly; 205 /// The ForceDisassemble field from the record 206 bool ForceDisassemble; 207 // The CD8_Scale field from the record 208 uint8_t CD8_Scale; 209 // Whether the instruction has the predicate "In64BitMode" 210 bool Is64Bit; 211 // Whether the instruction has the predicate "In32BitMode" 212 bool Is32Bit; 213 214 /// The instruction name as listed in the tables 215 std::string Name; 216 217 /// Indicates whether the instruction should be emitted into the decode 218 /// tables; regardless, it will be emitted into the instruction info table 219 bool ShouldBeEmitted; 220 221 /// The operands of the instruction, as listed in the CodeGenInstruction. 222 /// They are not one-to-one with operands listed in the MCInst; for example, 223 /// memory operands expand to 5 operands in the MCInst 224 const std::vector<CGIOperandList::OperandInfo>* Operands; 225 226 /// The description of the instruction that is emitted into the instruction 227 /// info table 228 InstructionSpecifier* Spec; 229 230 /// insnContext - Returns the primary context in which the instruction is 231 /// valid. 232 /// 233 /// @return - The context in which the instruction is valid. 234 InstructionContext insnContext() const; 235 236 /// typeFromString - Translates an operand type from the string provided in 237 /// the LLVM tables to an OperandType for use in the operand specifier. 238 /// 239 /// @param s - The string, as extracted by calling Rec->getName() 240 /// on a CodeGenInstruction::OperandInfo. 241 /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W 242 /// prefix. If it does, 32-bit register operands stay 243 /// 32-bit regardless of the operand size. 244 /// @param OpSize Indicates the operand size of the instruction. 245 /// If register size does not match OpSize, then 246 /// register sizes keep their size. 247 /// @return - The operand's type. 248 static OperandType typeFromString(const std::string& s, 249 bool hasREX_WPrefix, uint8_t OpSize); 250 251 /// immediateEncodingFromString - Translates an immediate encoding from the 252 /// string provided in the LLVM tables to an OperandEncoding for use in 253 /// the operand specifier. 254 /// 255 /// @param s - See typeFromString(). 256 /// @param OpSize - Indicates whether this is an OpSize16 instruction. 257 /// If it is not, then 16-bit immediate operands stay 16-bit. 258 /// @return - The operand's encoding. 259 static OperandEncoding immediateEncodingFromString(const std::string &s, 260 uint8_t OpSize); 261 262 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but 263 /// handles operands that are in the REG field of the ModR/M byte. 264 static OperandEncoding rmRegisterEncodingFromString(const std::string &s, 265 uint8_t OpSize); 266 267 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but 268 /// handles operands that are in the REG field of the ModR/M byte. 269 static OperandEncoding roRegisterEncodingFromString(const std::string &s, 270 uint8_t OpSize); 271 static OperandEncoding memoryEncodingFromString(const std::string &s, 272 uint8_t OpSize); 273 static OperandEncoding relocationEncodingFromString(const std::string &s, 274 uint8_t OpSize); 275 static OperandEncoding opcodeModifierEncodingFromString(const std::string &s, 276 uint8_t OpSize); 277 static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s, 278 uint8_t OpSize); 279 static OperandEncoding writemaskRegisterEncodingFromString(const std::string &s, 280 uint8_t OpSize); 281 282 /// Adjust the encoding type for an operand based on the instruction. 283 void adjustOperandEncoding(OperandEncoding &encoding); 284 285 /// handleOperand - Converts a single operand from the LLVM table format to 286 /// the emitted table format, handling any duplicate operands it encounters 287 /// and then one non-duplicate. 288 /// 289 /// @param optional - Determines whether to assert that the 290 /// operand exists. 291 /// @param operandIndex - The index into the generated operand table. 292 /// Incremented by this function one or more 293 /// times to reflect possible duplicate 294 /// operands). 295 /// @param physicalOperandIndex - The index of the current operand into the 296 /// set of non-duplicate ('physical') operands. 297 /// Incremented by this function once. 298 /// @param numPhysicalOperands - The number of non-duplicate operands in the 299 /// instructions. 300 /// @param operandMapping - The operand mapping, which has an entry for 301 /// each operand that indicates whether it is a 302 /// duplicate, and of what. 303 void handleOperand(bool optional, 304 unsigned &operandIndex, 305 unsigned &physicalOperandIndex, 306 unsigned numPhysicalOperands, 307 const unsigned *operandMapping, 308 OperandEncoding (*encodingFromString) 309 (const std::string&, 310 uint8_t OpSize)); 311 312 /// shouldBeEmitted - Returns the shouldBeEmitted field. Although filter() 313 /// filters out many instructions, at various points in decoding we 314 /// determine that the instruction should not actually be decodable. In 315 /// particular, MMX MOV instructions aren't emitted, but they're only 316 /// identified during operand parsing. 317 /// 318 /// @return - true if at this point we believe the instruction should be 319 /// emitted; false if not. This will return false if filter() returns false 320 /// once emitInstructionSpecifier() has been called. shouldBeEmitted()321 bool shouldBeEmitted() const { 322 return ShouldBeEmitted; 323 } 324 325 /// emitInstructionSpecifier - Loads the instruction specifier for the current 326 /// instruction into a DisassemblerTables. 327 /// 328 void emitInstructionSpecifier(); 329 330 /// emitDecodePath - Populates the proper fields in the decode tables 331 /// corresponding to the decode paths for this instruction. 332 /// 333 /// \param tables The DisassemblerTables to populate with the decode 334 /// decode information for the current instruction. 335 void emitDecodePath(DisassemblerTables &tables) const; 336 337 /// Constructor - Initializes a RecognizableInstr with the appropriate fields 338 /// from a CodeGenInstruction. 339 /// 340 /// \param tables The DisassemblerTables that the specifier will be added to. 341 /// \param insn The CodeGenInstruction to extract information from. 342 /// \param uid The unique ID of the current instruction. 343 RecognizableInstr(DisassemblerTables &tables, 344 const CodeGenInstruction &insn, 345 InstrUID uid); 346 public: 347 /// processInstr - Accepts a CodeGenInstruction and loads decode information 348 /// for it into a DisassemblerTables if appropriate. 349 /// 350 /// \param tables The DiassemblerTables to be populated with decode 351 /// information. 352 /// \param insn The CodeGenInstruction to be used as a source for this 353 /// information. 354 /// \param uid The unique ID of the instruction. 355 static void processInstr(DisassemblerTables &tables, 356 const CodeGenInstruction &insn, 357 InstrUID uid); 358 }; 359 360 } // namespace X86Disassembler 361 362 } // namespace llvm 363 364 #endif 365