1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about Mips target spec.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "MipsTargetMachine.h"
14 #include "MCTargetDesc/MipsABIInfo.h"
15 #include "MCTargetDesc/MipsMCTargetDesc.h"
16 #include "Mips.h"
17 #include "Mips16ISelDAGToDAG.h"
18 #include "MipsSEISelDAGToDAG.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetObjectFile.h"
21 #include "TargetInfo/MipsTargetInfo.h"
22 #include "llvm/ADT/Optional.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/Analysis/TargetTransformInfo.h"
26 #include "llvm/CodeGen/BasicTTIImpl.h"
27 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
28 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
29 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
30 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/CodeGen/TargetPassConfig.h"
34 #include "llvm/IR/Attributes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/InitializePasses.h"
37 #include "llvm/Support/CodeGen.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/TargetRegistry.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
42 #include <string>
43
44 using namespace llvm;
45
46 #define DEBUG_TYPE "mips"
47
LLVMInitializeMipsTarget()48 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTarget() {
49 // Register the target.
50 RegisterTargetMachine<MipsebTargetMachine> X(getTheMipsTarget());
51 RegisterTargetMachine<MipselTargetMachine> Y(getTheMipselTarget());
52 RegisterTargetMachine<MipsebTargetMachine> A(getTheMips64Target());
53 RegisterTargetMachine<MipselTargetMachine> B(getTheMips64elTarget());
54
55 PassRegistry *PR = PassRegistry::getPassRegistry();
56 initializeGlobalISel(*PR);
57 initializeMipsDelaySlotFillerPass(*PR);
58 initializeMipsBranchExpansionPass(*PR);
59 initializeMicroMipsSizeReducePass(*PR);
60 initializeMipsPreLegalizerCombinerPass(*PR);
61 }
62
computeDataLayout(const Triple & TT,StringRef CPU,const TargetOptions & Options,bool isLittle)63 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
64 const TargetOptions &Options,
65 bool isLittle) {
66 std::string Ret;
67 MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions);
68
69 // There are both little and big endian mips.
70 if (isLittle)
71 Ret += "e";
72 else
73 Ret += "E";
74
75 if (ABI.IsO32())
76 Ret += "-m:m";
77 else
78 Ret += "-m:e";
79
80 // Pointers are 32 bit on some ABIs.
81 if (!ABI.IsN64())
82 Ret += "-p:32:32";
83
84 // 8 and 16 bit integers only need to have natural alignment, but try to
85 // align them to 32 bits. 64 bit integers have natural alignment.
86 Ret += "-i8:8:32-i16:16:32-i64:64";
87
88 // 32 bit registers are always available and the stack is at least 64 bit
89 // aligned. On N64 64 bit registers are also available and the stack is
90 // 128 bit aligned.
91 if (ABI.IsN64() || ABI.IsN32())
92 Ret += "-n32:64-S128";
93 else
94 Ret += "-n32-S64";
95
96 return Ret;
97 }
98
getEffectiveRelocModel(bool JIT,Optional<Reloc::Model> RM)99 static Reloc::Model getEffectiveRelocModel(bool JIT,
100 Optional<Reloc::Model> RM) {
101 if (!RM.hasValue() || JIT)
102 return Reloc::Static;
103 return *RM;
104 }
105
106 // On function prologue, the stack is created by decrementing
107 // its pointer. Once decremented, all references are done with positive
108 // offset from the stack/frame pointer, using StackGrowsUp enables
109 // an easier handling.
110 // Using CodeModel::Large enables different CALL behavior.
MipsTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,Optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT,bool isLittle)111 MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT,
112 StringRef CPU, StringRef FS,
113 const TargetOptions &Options,
114 Optional<Reloc::Model> RM,
115 Optional<CodeModel::Model> CM,
116 CodeGenOpt::Level OL, bool JIT,
117 bool isLittle)
118 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
119 CPU, FS, Options, getEffectiveRelocModel(JIT, RM),
120 getEffectiveCodeModel(CM, CodeModel::Small), OL),
121 isLittle(isLittle), TLOF(std::make_unique<MipsTargetObjectFile>()),
122 ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)),
123 Subtarget(nullptr),
124 DefaultSubtarget(TT, CPU, FS, isLittle, *this,
125 MaybeAlign(Options.StackAlignmentOverride)),
126 NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
127 isLittle, *this,
128 MaybeAlign(Options.StackAlignmentOverride)),
129 Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
130 isLittle, *this,
131 MaybeAlign(Options.StackAlignmentOverride)) {
132 Subtarget = &DefaultSubtarget;
133 initAsmInfo();
134 }
135
136 MipsTargetMachine::~MipsTargetMachine() = default;
137
anchor()138 void MipsebTargetMachine::anchor() {}
139
MipsebTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,Optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT)140 MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT,
141 StringRef CPU, StringRef FS,
142 const TargetOptions &Options,
143 Optional<Reloc::Model> RM,
144 Optional<CodeModel::Model> CM,
145 CodeGenOpt::Level OL, bool JIT)
146 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
147
anchor()148 void MipselTargetMachine::anchor() {}
149
MipselTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,Optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT)150 MipselTargetMachine::MipselTargetMachine(const Target &T, const Triple &TT,
151 StringRef CPU, StringRef FS,
152 const TargetOptions &Options,
153 Optional<Reloc::Model> RM,
154 Optional<CodeModel::Model> CM,
155 CodeGenOpt::Level OL, bool JIT)
156 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
157
158 const MipsSubtarget *
getSubtargetImpl(const Function & F) const159 MipsTargetMachine::getSubtargetImpl(const Function &F) const {
160 Attribute CPUAttr = F.getFnAttribute("target-cpu");
161 Attribute FSAttr = F.getFnAttribute("target-features");
162
163 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
164 ? CPUAttr.getValueAsString().str()
165 : TargetCPU;
166 std::string FS = !FSAttr.hasAttribute(Attribute::None)
167 ? FSAttr.getValueAsString().str()
168 : TargetFS;
169 bool hasMips16Attr =
170 !F.getFnAttribute("mips16").hasAttribute(Attribute::None);
171 bool hasNoMips16Attr =
172 !F.getFnAttribute("nomips16").hasAttribute(Attribute::None);
173
174 bool HasMicroMipsAttr =
175 !F.getFnAttribute("micromips").hasAttribute(Attribute::None);
176 bool HasNoMicroMipsAttr =
177 !F.getFnAttribute("nomicromips").hasAttribute(Attribute::None);
178
179 // FIXME: This is related to the code below to reset the target options,
180 // we need to know whether or not the soft float flag is set on the
181 // function, so we can enable it as a subtarget feature.
182 bool softFloat =
183 F.hasFnAttribute("use-soft-float") &&
184 F.getFnAttribute("use-soft-float").getValueAsString() == "true";
185
186 if (hasMips16Attr)
187 FS += FS.empty() ? "+mips16" : ",+mips16";
188 else if (hasNoMips16Attr)
189 FS += FS.empty() ? "-mips16" : ",-mips16";
190 if (HasMicroMipsAttr)
191 FS += FS.empty() ? "+micromips" : ",+micromips";
192 else if (HasNoMicroMipsAttr)
193 FS += FS.empty() ? "-micromips" : ",-micromips";
194 if (softFloat)
195 FS += FS.empty() ? "+soft-float" : ",+soft-float";
196
197 auto &I = SubtargetMap[CPU + FS];
198 if (!I) {
199 // This needs to be done before we create a new subtarget since any
200 // creation will depend on the TM and the code generation flags on the
201 // function that reside in TargetOptions.
202 resetTargetOptions(F);
203 I = std::make_unique<MipsSubtarget>(
204 TargetTriple, CPU, FS, isLittle, *this,
205 MaybeAlign(Options.StackAlignmentOverride));
206 }
207 return I.get();
208 }
209
resetSubtarget(MachineFunction * MF)210 void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
211 LLVM_DEBUG(dbgs() << "resetSubtarget\n");
212
213 Subtarget = &MF->getSubtarget<MipsSubtarget>();
214 }
215
216 namespace {
217
218 /// Mips Code Generator Pass Configuration Options.
219 class MipsPassConfig : public TargetPassConfig {
220 public:
MipsPassConfig(MipsTargetMachine & TM,PassManagerBase & PM)221 MipsPassConfig(MipsTargetMachine &TM, PassManagerBase &PM)
222 : TargetPassConfig(TM, PM) {
223 // The current implementation of long branch pass requires a scratch
224 // register ($at) to be available before branch instructions. Tail merging
225 // can break this requirement, so disable it when long branch pass is
226 // enabled.
227 EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
228 }
229
getMipsTargetMachine() const230 MipsTargetMachine &getMipsTargetMachine() const {
231 return getTM<MipsTargetMachine>();
232 }
233
getMipsSubtarget() const234 const MipsSubtarget &getMipsSubtarget() const {
235 return *getMipsTargetMachine().getSubtargetImpl();
236 }
237
238 void addIRPasses() override;
239 bool addInstSelector() override;
240 void addPreEmitPass() override;
241 void addPreRegAlloc() override;
242 bool addIRTranslator() override;
243 void addPreLegalizeMachineIR() override;
244 bool addLegalizeMachineIR() override;
245 bool addRegBankSelect() override;
246 bool addGlobalInstructionSelect() override;
247
248 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
249 };
250
251 } // end anonymous namespace
252
createPassConfig(PassManagerBase & PM)253 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
254 return new MipsPassConfig(*this, PM);
255 }
256
getCSEConfig() const257 std::unique_ptr<CSEConfigBase> MipsPassConfig::getCSEConfig() const {
258 return getStandardCSEConfigForOpt(TM->getOptLevel());
259 }
260
addIRPasses()261 void MipsPassConfig::addIRPasses() {
262 TargetPassConfig::addIRPasses();
263 addPass(createAtomicExpandPass());
264 if (getMipsSubtarget().os16())
265 addPass(createMipsOs16Pass());
266 if (getMipsSubtarget().inMips16HardFloat())
267 addPass(createMips16HardFloatPass());
268 }
269 // Install an instruction selector pass using
270 // the ISelDag to gen Mips code.
addInstSelector()271 bool MipsPassConfig::addInstSelector() {
272 addPass(createMipsModuleISelDagPass());
273 addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel()));
274 addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel()));
275 return false;
276 }
277
addPreRegAlloc()278 void MipsPassConfig::addPreRegAlloc() {
279 addPass(createMipsOptimizePICCallPass());
280 }
281
282 TargetTransformInfo
getTargetTransformInfo(const Function & F)283 MipsTargetMachine::getTargetTransformInfo(const Function &F) {
284 if (Subtarget->allowMixed16_32()) {
285 LLVM_DEBUG(errs() << "No Target Transform Info Pass Added\n");
286 // FIXME: This is no longer necessary as the TTI returned is per-function.
287 return TargetTransformInfo(F.getParent()->getDataLayout());
288 }
289
290 LLVM_DEBUG(errs() << "Target Transform Info Pass Added\n");
291 return TargetTransformInfo(BasicTTIImpl(this, F));
292 }
293
294 // Implemented by targets that want to run passes immediately before
295 // machine code is emitted. return true if -print-machineinstrs should
296 // print out the code after the passes.
addPreEmitPass()297 void MipsPassConfig::addPreEmitPass() {
298 // Expand pseudo instructions that are sensitive to register allocation.
299 addPass(createMipsExpandPseudoPass());
300
301 // The microMIPS size reduction pass performs instruction reselection for
302 // instructions which can be remapped to a 16 bit instruction.
303 addPass(createMicroMipsSizeReducePass());
304
305 // The delay slot filler pass can potientially create forbidden slot hazards
306 // for MIPSR6 and therefore it should go before MipsBranchExpansion pass.
307 addPass(createMipsDelaySlotFillerPass());
308
309 // This pass expands branches and takes care about the forbidden slot hazards.
310 // Expanding branches may potentially create forbidden slot hazards for
311 // MIPSR6, and fixing such hazard may potentially break a branch by extending
312 // its offset out of range. That's why this pass combine these two tasks, and
313 // runs them alternately until one of them finishes without any changes. Only
314 // then we can be sure that all branches are expanded properly and no hazards
315 // exists.
316 // Any new pass should go before this pass.
317 addPass(createMipsBranchExpansion());
318
319 addPass(createMipsConstantIslandPass());
320 }
321
addIRTranslator()322 bool MipsPassConfig::addIRTranslator() {
323 addPass(new IRTranslator());
324 return false;
325 }
326
addPreLegalizeMachineIR()327 void MipsPassConfig::addPreLegalizeMachineIR() {
328 addPass(createMipsPreLegalizeCombiner());
329 }
330
addLegalizeMachineIR()331 bool MipsPassConfig::addLegalizeMachineIR() {
332 addPass(new Legalizer());
333 return false;
334 }
335
addRegBankSelect()336 bool MipsPassConfig::addRegBankSelect() {
337 addPass(new RegBankSelect());
338 return false;
339 }
340
addGlobalInstructionSelect()341 bool MipsPassConfig::addGlobalInstructionSelect() {
342 addPass(new InstructionSelect());
343 return false;
344 }
345