1; RUN: llc < %s -march=amdgcn -mcpu=bonaire -verify-machineinstrs | FileCheck --check-prefix=GCN %s 2; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s 3 4; GCN-LABEL: {{^}}inline_reg_constraints: 5; GCN: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}] 6; GCN: flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] 7; GCN: flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] 8; GCN: flat_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] 9; GCN: flat_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] 10; GCN: s_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}] 11; GCN: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] 12; GCN: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] 13; GCN: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] 14; GCN: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] 15; GCN: s_load_dwordx8 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] 16 17define amdgpu_kernel void @inline_reg_constraints(i32 addrspace(1)* %ptr) { 18entry: 19 %v32 = tail call i32 asm sideeffect "flat_load_dword $0, $1", "=v,v"(i32 addrspace(1)* %ptr) 20 %v2_32 = tail call <2 x i32> asm sideeffect "flat_load_dwordx2 $0, $1", "=v,v"(i32 addrspace(1)* %ptr) 21 %v64 = tail call i64 asm sideeffect "flat_load_dwordx2 $0, $1", "=v,v"(i32 addrspace(1)* %ptr) 22 %v4_32 = tail call <4 x i32> asm sideeffect "flat_load_dwordx4 $0, $1", "=v,v"(i32 addrspace(1)* %ptr) 23 %v128 = tail call i128 asm sideeffect "flat_load_dwordx4 $0, $1", "=v,v"(i32 addrspace(1)* %ptr) 24 %s32 = tail call i32 asm sideeffect "s_load_dword $0, $1", "=s,s"(i32 addrspace(1)* %ptr) 25 %s32_2 = tail call <2 x i32> asm sideeffect "s_load_dwordx2 $0, $1", "=s,s"(i32 addrspace(1)* %ptr) 26 %s64 = tail call i64 asm sideeffect "s_load_dwordx2 $0, $1", "=s,s"(i32 addrspace(1)* %ptr) 27 %s4_32 = tail call <4 x i32> asm sideeffect "s_load_dwordx4 $0, $1", "=s,s"(i32 addrspace(1)* %ptr) 28 %s128 = tail call i128 asm sideeffect "s_load_dwordx4 $0, $1", "=s,s"(i32 addrspace(1)* %ptr) 29 %s256 = tail call <8 x i32> asm sideeffect "s_load_dwordx8 $0, $1", "=s,s"(i32 addrspace(1)* %ptr) 30 ret void 31} 32 33; GCN-LABEL: {{^}}inline_sreg_constraint_m0: 34; GCN: s_mov_b32 m0, -1 35; GCN-NOT: m0 36; GCN: ; use m0 37define amdgpu_kernel void @inline_sreg_constraint_m0() { 38 %m0 = tail call i32 asm sideeffect "s_mov_b32 m0, -1", "={m0}"() 39 tail call void asm sideeffect "; use $0", "s"(i32 %m0) 40 ret void 41} 42 43; GCN-LABEL: {{^}}inline_sreg_constraint_imm_i32: 44; GCN: s_mov_b32 [[REG:s[0-9]+]], 32 45; GCN: ; use [[REG]] 46define amdgpu_kernel void @inline_sreg_constraint_imm_i32() { 47 tail call void asm sideeffect "; use $0", "s"(i32 32) 48 ret void 49} 50 51; GCN-LABEL: {{^}}inline_sreg_constraint_imm_f32: 52; GCN: s_mov_b32 [[REG:s[0-9]+]], 1.0 53; GCN: ; use [[REG]] 54define amdgpu_kernel void @inline_sreg_constraint_imm_f32() { 55 tail call void asm sideeffect "; use $0", "s"(float 1.0) 56 ret void 57} 58 59; FIXME: Should be able to use s_mov_b64 60; GCN-LABEL: {{^}}inline_sreg_constraint_imm_i64: 61; GCN-DAG: s_mov_b32 s[[REG_LO:[0-9]+]], -4{{$}} 62; GCN-DAG: s_mov_b32 s[[REG_HI:[0-9]+]], -1{{$}} 63; GCN: ; use s{{\[}}[[REG_LO]]:[[REG_HI]]{{\]}} 64define amdgpu_kernel void @inline_sreg_constraint_imm_i64() { 65 tail call void asm sideeffect "; use $0", "s"(i64 -4) 66 ret void 67} 68 69; GCN-LABEL: {{^}}inline_sreg_constraint_imm_f64: 70; GCN-DAG: s_mov_b32 s[[REG_LO:[0-9]+]], 0{{$}} 71; GCN-DAG: s_mov_b32 s[[REG_HI:[0-9]+]], 0x3ff00000{{$}} 72; GCN: ; use s{{\[}}[[REG_LO]]:[[REG_HI]]{{\]}} 73define amdgpu_kernel void @inline_sreg_constraint_imm_f64() { 74 tail call void asm sideeffect "; use $0", "s"(double 1.0) 75 ret void 76} 77