1 //===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements a target parser to recognise X86 hardware features.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/Support/X86TargetParser.h"
14 #include "llvm/ADT/StringSwitch.h"
15 #include "llvm/ADT/Triple.h"
16 
17 using namespace llvm;
18 using namespace llvm::X86;
19 
20 namespace {
21 
22 /// Container class for CPU features.
23 /// This is a constexpr reimplementation of a subset of std::bitset. It would be
24 /// nice to use std::bitset directly, but it doesn't support constant
25 /// initialization.
26 class FeatureBitset {
27   static constexpr unsigned NUM_FEATURE_WORDS =
28       (X86::CPU_FEATURE_MAX + 31) / 32;
29 
30   // This cannot be a std::array, operator[] is not constexpr until C++17.
31   uint32_t Bits[NUM_FEATURE_WORDS] = {};
32 
33 public:
34   constexpr FeatureBitset() = default;
FeatureBitset(std::initializer_list<unsigned> Init)35   constexpr FeatureBitset(std::initializer_list<unsigned> Init) {
36     for (auto I : Init)
37       set(I);
38   }
39 
any() const40   bool any() const {
41     return llvm::any_of(Bits, [](uint64_t V) { return V != 0; });
42   }
43 
set(unsigned I)44   constexpr FeatureBitset &set(unsigned I) {
45     // GCC <6.2 crashes if this is written in a single statement.
46     uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32));
47     Bits[I / 32] = NewBits;
48     return *this;
49   }
50 
operator [](unsigned I) const51   constexpr bool operator[](unsigned I) const {
52     uint32_t Mask = uint32_t(1) << (I % 32);
53     return (Bits[I / 32] & Mask) != 0;
54   }
55 
operator &=(const FeatureBitset & RHS)56   constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) {
57     for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
58       // GCC <6.2 crashes if this is written in a single statement.
59       uint32_t NewBits = Bits[I] & RHS.Bits[I];
60       Bits[I] = NewBits;
61     }
62     return *this;
63   }
64 
operator |=(const FeatureBitset & RHS)65   constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) {
66     for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
67       // GCC <6.2 crashes if this is written in a single statement.
68       uint32_t NewBits = Bits[I] | RHS.Bits[I];
69       Bits[I] = NewBits;
70     }
71     return *this;
72   }
73 
74   // gcc 5.3 miscompiles this if we try to write this using operator&=.
operator &(const FeatureBitset & RHS) const75   constexpr FeatureBitset operator&(const FeatureBitset &RHS) const {
76     FeatureBitset Result;
77     for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
78       Result.Bits[I] = Bits[I] & RHS.Bits[I];
79     return Result;
80   }
81 
82   // gcc 5.3 miscompiles this if we try to write this using operator&=.
operator |(const FeatureBitset & RHS) const83   constexpr FeatureBitset operator|(const FeatureBitset &RHS) const {
84     FeatureBitset Result;
85     for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
86       Result.Bits[I] = Bits[I] | RHS.Bits[I];
87     return Result;
88   }
89 
operator ~() const90   constexpr FeatureBitset operator~() const {
91     FeatureBitset Result;
92     for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
93       Result.Bits[I] = ~Bits[I];
94     return Result;
95   }
96 
operator !=(const FeatureBitset & RHS) const97   constexpr bool operator!=(const FeatureBitset &RHS) const {
98     for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
99       if (Bits[I] != RHS.Bits[I])
100         return true;
101     return false;
102   }
103 };
104 
105 struct ProcInfo {
106   StringLiteral Name;
107   X86::CPUKind Kind;
108   unsigned KeyFeature;
109   FeatureBitset Features;
110 };
111 
112 struct FeatureInfo {
113   StringLiteral Name;
114   FeatureBitset ImpliedFeatures;
115 };
116 
117 } // end anonymous namespace
118 
119 #define X86_FEATURE(ENUM, STRING)                                              \
120   static constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM};
121 #include "llvm/Support/X86TargetParser.def"
122 
123 // Pentium with MMX.
124 static constexpr FeatureBitset FeaturesPentiumMMX =
125     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
126 
127 // Pentium 2 and 3.
128 static constexpr FeatureBitset FeaturesPentium2 =
129     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR;
130 static constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE;
131 
132 // Pentium 4 CPUs
133 static constexpr FeatureBitset FeaturesPentium4 =
134     FeaturesPentium3 | FeatureSSE2;
135 static constexpr FeatureBitset FeaturesPrescott =
136     FeaturesPentium4 | FeatureSSE3;
137 static constexpr FeatureBitset FeaturesNocona =
138     FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
139 
140 // Basic 64-bit capable CPU.
141 static constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT;
142 
143 // Intel Core CPUs
144 static constexpr FeatureBitset FeaturesCore2 =
145     FeaturesNocona | FeatureSAHF | FeatureSSSE3;
146 static constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
147 static constexpr FeatureBitset FeaturesNehalem =
148     FeaturesPenryn | FeaturePOPCNT | FeatureSSE4_2;
149 static constexpr FeatureBitset FeaturesWestmere =
150     FeaturesNehalem | FeaturePCLMUL;
151 static constexpr FeatureBitset FeaturesSandyBridge =
152     FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT;
153 static constexpr FeatureBitset FeaturesIvyBridge =
154     FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND;
155 static constexpr FeatureBitset FeaturesHaswell =
156     FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA |
157     FeatureINVPCID | FeatureLZCNT | FeatureMOVBE;
158 static constexpr FeatureBitset FeaturesBroadwell =
159     FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED;
160 
161 // Intel Knights Landing and Knights Mill
162 // Knights Landing has feature parity with Broadwell.
163 static constexpr FeatureBitset FeaturesKNL =
164     FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD |
165     FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1;
166 static constexpr FeatureBitset FeaturesKNM =
167     FeaturesKNL | FeatureAVX512VPOPCNTDQ;
168 
169 // Intel Skylake processors.
170 static constexpr FeatureBitset FeaturesSkylakeClient =
171     FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
172     FeatureXSAVES | FeatureSGX;
173 // SkylakeServer inherits all SkylakeClient features except SGX.
174 // FIXME: That doesn't match gcc.
175 static constexpr FeatureBitset FeaturesSkylakeServer =
176     (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD |
177     FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB |
178     FeaturePKU;
179 static constexpr FeatureBitset FeaturesCascadeLake =
180     FeaturesSkylakeServer | FeatureAVX512VNNI;
181 static constexpr FeatureBitset FeaturesCooperLake =
182     FeaturesCascadeLake | FeatureAVX512BF16;
183 
184 // Intel 10nm processors.
185 static constexpr FeatureBitset FeaturesCannonlake =
186     FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
187     FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
188     FeaturePKU | FeatureSHA;
189 static constexpr FeatureBitset FeaturesICLClient =
190     FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
191     FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureGFNI |
192     FeatureRDPID | FeatureVAES | FeatureVPCLMULQDQ;
193 static constexpr FeatureBitset FeaturesICLServer =
194     FeaturesICLClient | FeaturePCONFIG | FeatureWBNOINVD;
195 static constexpr FeatureBitset FeaturesTigerlake =
196     FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
197     FeatureMOVDIRI | FeatureSHSTK;
198 
199 // Intel Atom processors.
200 // Bonnell has feature parity with Core2 and adds MOVBE.
201 static constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
202 // Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
203 static constexpr FeatureBitset FeaturesSilvermont =
204     FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
205 static constexpr FeatureBitset FeaturesGoldmont =
206     FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
207     FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
208     FeatureXSAVEOPT | FeatureXSAVES;
209 static constexpr FeatureBitset FeaturesGoldmontPlus =
210     FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
211 static constexpr FeatureBitset FeaturesTremont =
212     FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
213 
214 // Geode Processor.
215 static constexpr FeatureBitset FeaturesGeode =
216     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
217 
218 // K6 processor.
219 static constexpr FeatureBitset FeaturesK6 =
220     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
221 
222 // K7 and K8 architecture processors.
223 static constexpr FeatureBitset FeaturesAthlon =
224     FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
225 static constexpr FeatureBitset FeaturesAthlonXP =
226     FeaturesAthlon | FeatureFXSR | FeatureSSE;
227 static constexpr FeatureBitset FeaturesK8 =
228     FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
229 static constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
230 static constexpr FeatureBitset FeaturesAMDFAM10 =
231     FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
232     FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
233 
234 // Bobcat architecture processors.
235 static constexpr FeatureBitset FeaturesBTVER1 =
236     FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
237     FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
238     FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
239     FeatureSAHF;
240 static constexpr FeatureBitset FeaturesBTVER2 =
241     FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureF16C |
242     FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
243 
244 // AMD Bulldozer architecture processors.
245 static constexpr FeatureBitset FeaturesBDVER1 =
246     FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
247     FeatureCMPXCHG16B | Feature64BIT | FeatureFMA4 | FeatureFXSR | FeatureLWP |
248     FeatureLZCNT | FeatureMMX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW |
249     FeatureSAHF | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 |
250     FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | FeatureXOP | FeatureXSAVE;
251 static constexpr FeatureBitset FeaturesBDVER2 =
252     FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM;
253 static constexpr FeatureBitset FeaturesBDVER3 =
254     FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT;
255 static constexpr FeatureBitset FeaturesBDVER4 =
256     FeaturesBDVER3 | FeatureAVX2 | FeatureBMI2 | FeatureMOVBE | FeatureMWAITX |
257     FeatureRDRND;
258 
259 // AMD Zen architecture processors.
260 static constexpr FeatureBitset FeaturesZNVER1 =
261     FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
262     FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
263     FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | FeatureF16C |
264     FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureMMX |
265     FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
266     FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
267     FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
268     FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
269     FeatureXSAVEOPT | FeatureXSAVES;
270 static constexpr FeatureBitset FeaturesZNVER2 =
271     FeaturesZNVER1 | FeatureCLWB | FeatureRDPID | FeatureWBNOINVD;
272 
273 static constexpr ProcInfo Processors[] = {
274   // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
275   { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B },
276   // i386-generation processors.
277   { {"i386"}, CK_i386, ~0U, FeatureX87 },
278   // i486-generation processors.
279   { {"i486"}, CK_i486, ~0U, FeatureX87 },
280   { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX },
281   { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW },
282   { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW },
283   // i586-generation processors, P5 microarchitecture based.
284   { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B },
285   { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B },
286   { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX },
287   // i686-generation processors, P6 / Pentium M microarchitecture based.
288   { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B },
289   { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B },
290   { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 },
291   { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 },
292   { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 },
293   { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 },
294   { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 },
295   { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott },
296   // Netburst microarchitecture based processors.
297   { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 },
298   { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 },
299   { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott },
300   { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona },
301   // Core microarchitecture based processors.
302   { {"core2"}, CK_Core2, ~0U, FeaturesCore2 },
303   { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn },
304   // Atom processors
305   { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
306   { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
307   { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
308   { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
309   { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont },
310   { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus },
311   { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont },
312   // Nehalem microarchitecture based processors.
313   { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
314   { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
315   // Westmere microarchitecture based processors.
316   { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere },
317   // Sandy Bridge microarchitecture based processors.
318   { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
319   { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
320   // Ivy Bridge microarchitecture based processors.
321   { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
322   { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
323   // Haswell microarchitecture based processors.
324   { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
325   { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
326   // Broadwell microarchitecture based processors.
327   { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell },
328   // Skylake client microarchitecture based processors.
329   { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient },
330   // Skylake server microarchitecture based processors.
331   { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
332   { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
333   // Cascadelake Server microarchitecture based processors.
334   { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake },
335   // Cooperlake Server microarchitecture based processors.
336   { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake },
337   // Cannonlake client microarchitecture based processors.
338   { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake },
339   // Icelake client microarchitecture based processors.
340   { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient },
341   // Icelake server microarchitecture based processors.
342   { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer },
343   // Tigerlake microarchitecture based processors.
344   { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake },
345   // Knights Landing processor.
346   { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL },
347   // Knights Mill processor.
348   { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM },
349   // Lakemont microarchitecture based processors.
350   { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B },
351   // K6 architecture processors.
352   { {"k6"}, CK_K6, ~0U, FeaturesK6 },
353   { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW },
354   { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW },
355   // K7 architecture processors.
356   { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon },
357   { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon },
358   { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
359   { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
360   { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
361   // K8 architecture processors.
362   { {"k8"}, CK_K8, ~0U, FeaturesK8 },
363   { {"athlon64"}, CK_K8, ~0U, FeaturesK8 },
364   { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 },
365   { {"opteron"}, CK_K8, ~0U, FeaturesK8 },
366   { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
367   { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
368   { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
369   { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
370   { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
371   // Bobcat architecture processors.
372   { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 },
373   { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 },
374   // Bulldozer architecture processors.
375   { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 },
376   { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 },
377   { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 },
378   { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 },
379   // Zen architecture processors.
380   { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 },
381   { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 },
382   // Generic 64-bit processor.
383   { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 },
384   // Geode processors.
385   { {"geode"}, CK_Geode, ~0U, FeaturesGeode },
386 };
387 
parseArchX86(StringRef CPU,bool Only64Bit)388 X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
389   for (const auto &P : Processors)
390     if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit))
391       return P.Kind;
392 
393   return CK_None;
394 }
395 
fillValidCPUArchList(SmallVectorImpl<StringRef> & Values,bool Only64Bit)396 void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values,
397                                      bool Only64Bit) {
398   for (const auto &P : Processors)
399     if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit))
400       Values.emplace_back(P.Name);
401 }
402 
getKeyFeature(X86::CPUKind Kind)403 ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) {
404   // FIXME: Can we avoid a linear search here? The table might be sorted by
405   // CPUKind so we could binary search?
406   for (const auto &P : Processors) {
407     if (P.Kind == Kind) {
408       assert(P.KeyFeature != ~0U && "Processor does not have a key feature.");
409       return static_cast<ProcessorFeatures>(P.KeyFeature);
410     }
411   }
412 
413   llvm_unreachable("Unable to find CPU kind!");
414 }
415 
416 // Features with no dependencies.
417 static constexpr FeatureBitset ImpliedFeatures64BIT = {};
418 static constexpr FeatureBitset ImpliedFeaturesADX = {};
419 static constexpr FeatureBitset ImpliedFeaturesBMI = {};
420 static constexpr FeatureBitset ImpliedFeaturesBMI2 = {};
421 static constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {};
422 static constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {};
423 static constexpr FeatureBitset ImpliedFeaturesCLWB = {};
424 static constexpr FeatureBitset ImpliedFeaturesCLZERO = {};
425 static constexpr FeatureBitset ImpliedFeaturesCMOV = {};
426 static constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {};
427 static constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {};
428 static constexpr FeatureBitset ImpliedFeaturesENQCMD = {};
429 static constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {};
430 static constexpr FeatureBitset ImpliedFeaturesFXSR = {};
431 static constexpr FeatureBitset ImpliedFeaturesINVPCID = {};
432 static constexpr FeatureBitset ImpliedFeaturesLWP = {};
433 static constexpr FeatureBitset ImpliedFeaturesLZCNT = {};
434 static constexpr FeatureBitset ImpliedFeaturesMWAITX = {};
435 static constexpr FeatureBitset ImpliedFeaturesMOVBE = {};
436 static constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {};
437 static constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {};
438 static constexpr FeatureBitset ImpliedFeaturesPCONFIG = {};
439 static constexpr FeatureBitset ImpliedFeaturesPOPCNT = {};
440 static constexpr FeatureBitset ImpliedFeaturesPKU = {};
441 static constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1 = {};
442 static constexpr FeatureBitset ImpliedFeaturesPRFCHW = {};
443 static constexpr FeatureBitset ImpliedFeaturesPTWRITE = {};
444 static constexpr FeatureBitset ImpliedFeaturesRDPID = {};
445 static constexpr FeatureBitset ImpliedFeaturesRDRND = {};
446 static constexpr FeatureBitset ImpliedFeaturesRDSEED = {};
447 static constexpr FeatureBitset ImpliedFeaturesRTM = {};
448 static constexpr FeatureBitset ImpliedFeaturesSAHF = {};
449 static constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {};
450 static constexpr FeatureBitset ImpliedFeaturesSGX = {};
451 static constexpr FeatureBitset ImpliedFeaturesSHSTK = {};
452 static constexpr FeatureBitset ImpliedFeaturesTBM = {};
453 static constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {};
454 static constexpr FeatureBitset ImpliedFeaturesWAITPKG = {};
455 static constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {};
456 static constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {};
457 static constexpr FeatureBitset ImpliedFeaturesX87 = {};
458 static constexpr FeatureBitset ImpliedFeaturesXSAVE = {};
459 
460 // Not really CPU features, but need to be in the table because clang uses
461 // target features to communicate them to the backend.
462 static constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {};
463 static constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {};
464 static constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {};
465 static constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {};
466 static constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {};
467 
468 // XSAVE features are dependent on basic XSAVE.
469 static constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE;
470 static constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE;
471 static constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE;
472 
473 // MMX->3DNOW->3DNOWA chain.
474 static constexpr FeatureBitset ImpliedFeaturesMMX = {};
475 static constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX;
476 static constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW;
477 
478 // SSE/AVX/AVX512F chain.
479 static constexpr FeatureBitset ImpliedFeaturesSSE = {};
480 static constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE;
481 static constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2;
482 static constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3;
483 static constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3;
484 static constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1;
485 static constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2;
486 static constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX;
487 static constexpr FeatureBitset ImpliedFeaturesAVX512F =
488     FeatureAVX2 | FeatureF16C | FeatureFMA;
489 
490 // Vector extensions that build on SSE or AVX.
491 static constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
492 static constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
493 static constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
494 static constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
495 static constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
496 static constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
497 static constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX;
498 static constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ =
499     FeatureAVX | FeaturePCLMUL;
500 
501 // AVX512 features.
502 static constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
503 static constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
504 static constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
505 static constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F;
506 static constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F;
507 static constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;
508 
509 static constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW;
510 static constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW;
511 static constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F;
512 static constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F;
513 static constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F;
514 static constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW;
515 static constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW;
516 static constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT =
517     FeatureAVX512F;
518 
519 // FIXME: These two aren't really implemented and just exist in the feature
520 // list for __builtin_cpu_supports. So omit their dependencies.
521 static constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {};
522 static constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {};
523 
524 // SSE4_A->FMA4->XOP chain.
525 static constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3;
526 static constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A;
527 static constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
528 
529 // AMX Features
530 static constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {};
531 static constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
532 static constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
533 
534 static constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = {
535 #define X86_FEATURE(ENUM, STR) {{STR}, ImpliedFeatures##ENUM},
536 #include "llvm/Support/X86TargetParser.def"
537 };
538 
539 // Convert the set bits in FeatureBitset to a list of strings.
getFeatureBitsAsStrings(const FeatureBitset & Bits,SmallVectorImpl<StringRef> & Features)540 static void getFeatureBitsAsStrings(const FeatureBitset &Bits,
541                                     SmallVectorImpl<StringRef> &Features) {
542   for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
543     if (Bits[i] && !FeatureInfos[i].Name.empty())
544       Features.push_back(FeatureInfos[i].Name);
545 }
546 
getFeaturesForCPU(StringRef CPU,SmallVectorImpl<StringRef> & EnabledFeatures)547 void llvm::X86::getFeaturesForCPU(StringRef CPU,
548                                   SmallVectorImpl<StringRef> &EnabledFeatures) {
549   auto I = llvm::find_if(Processors,
550                          [&](const ProcInfo &P) { return P.Name == CPU; });
551   assert(I != std::end(Processors) && "Processor not found!");
552 
553   FeatureBitset Bits = I->Features;
554 
555   // Remove the 64-bit feature which we only use to validate if a CPU can
556   // be used with 64-bit mode.
557   Bits &= ~Feature64BIT;
558 
559   // Add the string version of all set bits.
560   getFeatureBitsAsStrings(Bits, EnabledFeatures);
561 }
562 
563 // For each feature that is (transitively) implied by this feature, set it.
getImpliedEnabledFeatures(FeatureBitset & Bits,const FeatureBitset & Implies)564 static void getImpliedEnabledFeatures(FeatureBitset &Bits,
565                                       const FeatureBitset &Implies) {
566   // Fast path: Implies is often empty.
567   if (!Implies.any())
568     return;
569   FeatureBitset Prev;
570   Bits |= Implies;
571   do {
572     Prev = Bits;
573     for (unsigned i = CPU_FEATURE_MAX; i;)
574       if (Bits[--i])
575         Bits |= FeatureInfos[i].ImpliedFeatures;
576   } while (Prev != Bits);
577 }
578 
579 /// Create bit vector of features that are implied disabled if the feature
580 /// passed in Value is disabled.
getImpliedDisabledFeatures(FeatureBitset & Bits,unsigned Value)581 static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) {
582   // Check all features looking for any dependent on this feature. If we find
583   // one, mark it and recursively find any feature that depend on it.
584   FeatureBitset Prev;
585   Bits.set(Value);
586   do {
587     Prev = Bits;
588     for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
589       if ((FeatureInfos[i].ImpliedFeatures & Bits).any())
590         Bits.set(i);
591   } while (Prev != Bits);
592 }
593 
getImpliedFeatures(StringRef Feature,bool Enabled,SmallVectorImpl<StringRef> & ImpliedFeatures)594 void llvm::X86::getImpliedFeatures(
595     StringRef Feature, bool Enabled,
596     SmallVectorImpl<StringRef> &ImpliedFeatures) {
597   auto I = llvm::find_if(
598       FeatureInfos, [&](const FeatureInfo &FI) { return FI.Name == Feature; });
599   if (I == std::end(FeatureInfos)) {
600     // FIXME: This shouldn't happen, but may not have all features in the table
601     // yet.
602     return;
603   }
604 
605   FeatureBitset ImpliedBits;
606   if (Enabled)
607     getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures);
608   else
609     getImpliedDisabledFeatures(ImpliedBits,
610                                std::distance(std::begin(FeatureInfos), I));
611 
612   // Convert all the found bits into strings.
613   getFeatureBitsAsStrings(ImpliedBits, ImpliedFeatures);
614 }
615