1 //===-- NVPTX.h - Top-level interface for NVPTX representation --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the entry points for global functions defined in
10 // the LLVM NVPTX back-end.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTX_H
15 #define LLVM_LIB_TARGET_NVPTX_NVPTX_H
16 
17 #include "llvm/Pass.h"
18 #include "llvm/Support/CodeGen.h"
19 
20 namespace llvm {
21 class NVPTXTargetMachine;
22 class FunctionPass;
23 class MachineFunctionPass;
24 
25 namespace NVPTXCC {
26 enum CondCodes {
27   EQ,
28   NE,
29   LT,
30   LE,
31   GT,
32   GE
33 };
34 }
35 
36 FunctionPass *createNVPTXISelDag(NVPTXTargetMachine &TM,
37                                  llvm::CodeGenOpt::Level OptLevel);
38 ModulePass *createNVPTXAssignValidGlobalNamesPass();
39 ModulePass *createGenericToNVVMPass();
40 FunctionPass *createNVVMIntrRangePass(unsigned int SmVersion);
41 FunctionPass *createNVVMReflectPass(unsigned int SmVersion);
42 MachineFunctionPass *createNVPTXPrologEpilogPass();
43 MachineFunctionPass *createNVPTXReplaceImageHandlesPass();
44 FunctionPass *createNVPTXImageOptimizerPass();
45 FunctionPass *createNVPTXLowerArgsPass(const NVPTXTargetMachine *TM);
46 FunctionPass *createNVPTXLowerAllocaPass();
47 MachineFunctionPass *createNVPTXPeephole();
48 MachineFunctionPass *createNVPTXProxyRegErasurePass();
49 
50 namespace NVPTX {
51 enum DrvInterface {
52   NVCL,
53   CUDA
54 };
55 
56 // A field inside TSFlags needs a shift and a mask. The usage is
57 // always as follows :
58 // ((TSFlags & fieldMask) >> fieldShift)
59 // The enum keeps the mask, the shift, and all valid values of the
60 // field in one place.
61 enum VecInstType {
62   VecInstTypeShift = 0,
63   VecInstTypeMask = 0xF,
64 
65   VecNOP = 0,
66   VecLoad = 1,
67   VecStore = 2,
68   VecBuild = 3,
69   VecShuffle = 4,
70   VecExtract = 5,
71   VecInsert = 6,
72   VecDest = 7,
73   VecOther = 15
74 };
75 
76 enum SimpleMove {
77   SimpleMoveMask = 0x10,
78   SimpleMoveShift = 4
79 };
80 enum LoadStore {
81   isLoadMask = 0x20,
82   isLoadShift = 5,
83   isStoreMask = 0x40,
84   isStoreShift = 6
85 };
86 
87 namespace PTXLdStInstCode {
88 enum AddressSpace {
89   GENERIC = 0,
90   GLOBAL = 1,
91   CONSTANT = 2,
92   SHARED = 3,
93   PARAM = 4,
94   LOCAL = 5
95 };
96 enum FromType {
97   Unsigned = 0,
98   Signed,
99   Float,
100   Untyped
101 };
102 enum VecType {
103   Scalar = 1,
104   V2 = 2,
105   V4 = 4
106 };
107 }
108 
109 /// PTXCvtMode - Conversion code enumeration
110 namespace PTXCvtMode {
111 enum CvtMode {
112   NONE = 0,
113   RNI,
114   RZI,
115   RMI,
116   RPI,
117   RN,
118   RZ,
119   RM,
120   RP,
121 
122   BASE_MASK = 0x0F,
123   FTZ_FLAG = 0x10,
124   SAT_FLAG = 0x20
125 };
126 }
127 
128 /// PTXCmpMode - Comparison mode enumeration
129 namespace PTXCmpMode {
130 enum CmpMode {
131   EQ = 0,
132   NE,
133   LT,
134   LE,
135   GT,
136   GE,
137   LO,
138   LS,
139   HI,
140   HS,
141   EQU,
142   NEU,
143   LTU,
144   LEU,
145   GTU,
146   GEU,
147   NUM,
148   // NAN is a MACRO
149   NotANumber,
150 
151   BASE_MASK = 0xFF,
152   FTZ_FLAG = 0x100
153 };
154 }
155 }
156 } // end namespace llvm;
157 
158 // Defines symbolic names for NVPTX registers.  This defines a mapping from
159 // register name to register number.
160 #define GET_REGINFO_ENUM
161 #include "NVPTXGenRegisterInfo.inc"
162 
163 // Defines symbolic names for the NVPTX instructions.
164 #define GET_INSTRINFO_ENUM
165 #include "NVPTXGenInstrInfo.inc"
166 
167 #endif
168