1; RUN: llc < %s
2
3; This used to assert with "Overran sorted position" in AssignTopologicalOrder
4; due to a cycle created in performPostLD1Combine.
5
6target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
7target triple = "arm64-apple-ios7.0.0"
8
9; Function Attrs: nounwind ssp
10define void @f(double* %P1) #0 {
11entry:
12  %arrayidx4 = getelementptr inbounds double, double* %P1, i64 1
13  %0 = load double, double* %arrayidx4, align 8, !tbaa !1
14  %1 = load double, double* %P1, align 8, !tbaa !1
15  %2 = insertelement <2 x double> undef, double %0, i32 0
16  %3 = insertelement <2 x double> %2, double %1, i32 1
17  %4 = fsub <2 x double> zeroinitializer, %3
18  %5 = fmul <2 x double> undef, %4
19  %6 = extractelement <2 x double> %5, i32 0
20  %cmp168 = fcmp olt double %6, undef
21  br i1 %cmp168, label %if.then172, label %return
22
23if.then172:                                       ; preds = %cond.end90
24  %7 = tail call i64 @llvm.objectsize.i64.p0i8(i8* undef, i1 false)
25  br label %return
26
27return:                                           ; preds = %if.then172, %cond.end90, %entry
28  ret void
29}
30
31; Avoid an assert/bad codegen in LD1LANEPOST lowering by not forming
32; LD1LANEPOST ISD nodes with a non-constant lane index.
33define <4 x i32> @f2(i32 *%p, <4 x i1> %m, <4 x i32> %v1, <4 x i32> %v2, i32 %idx) {
34  %L0 = load i32, i32* %p
35  %p1 = getelementptr i32, i32* %p, i64 1
36  %L1 = load i32, i32* %p1
37  %v = select <4 x i1> %m, <4 x i32> %v1, <4 x i32> %v2
38  %vret = insertelement <4 x i32> %v, i32 %L0, i32 %idx
39  store i32 %L1, i32 *%p
40  ret <4 x i32> %vret
41}
42
43; Check that a cycle is avoided during isel between the LD1LANEPOST instruction and the load of %L1.
44define <4 x i32> @f3(i32 *%p, <4 x i1> %m, <4 x i32> %v1, <4 x i32> %v2) {
45  %L0 = load i32, i32* %p
46  %p1 = getelementptr i32, i32* %p, i64 1
47  %L1 = load i32, i32* %p1
48  %v = select <4 x i1> %m, <4 x i32> %v1, <4 x i32> %v2
49  %vret = insertelement <4 x i32> %v, i32 %L0, i32 %L1
50  ret <4 x i32> %vret
51}
52
53; Function Attrs: nounwind readnone
54declare i64 @llvm.objectsize.i64.p0i8(i8*, i1) #1
55
56attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
57attributes #1 = { nounwind readnone }
58
59!1 = !{!2, !2, i64 0}
60!2 = !{!"double", !3, i64 0}
61!3 = !{!"omnipotent char", !4, i64 0}
62!4 = !{!"Simple C/C++ TBAA"}
63