1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
3
4; These two forms are equivalent:
5;   sub %y, (xor %x, -1)
6;   add (add %x, 1), %y
7; Some targets may prefer one to the other.
8
9define i8 @scalar_i8(i8 %x, i8 %y) nounwind {
10; CHECK-LABEL: scalar_i8:
11; CHECK:       // %bb.0:
12; CHECK-NEXT:    add w8, w0, w1
13; CHECK-NEXT:    add w0, w8, #1 // =1
14; CHECK-NEXT:    ret
15  %t0 = add i8 %x, 1
16  %t1 = add i8 %y, %t0
17  ret i8 %t1
18}
19
20define i16 @scalar_i16(i16 %x, i16 %y) nounwind {
21; CHECK-LABEL: scalar_i16:
22; CHECK:       // %bb.0:
23; CHECK-NEXT:    add w8, w0, w1
24; CHECK-NEXT:    add w0, w8, #1 // =1
25; CHECK-NEXT:    ret
26  %t0 = add i16 %x, 1
27  %t1 = add i16 %y, %t0
28  ret i16 %t1
29}
30
31define i32 @scalar_i32(i32 %x, i32 %y) nounwind {
32; CHECK-LABEL: scalar_i32:
33; CHECK:       // %bb.0:
34; CHECK-NEXT:    add w8, w0, w1
35; CHECK-NEXT:    add w0, w8, #1 // =1
36; CHECK-NEXT:    ret
37  %t0 = add i32 %x, 1
38  %t1 = add i32 %y, %t0
39  ret i32 %t1
40}
41
42define i64 @scalar_i64(i64 %x, i64 %y) nounwind {
43; CHECK-LABEL: scalar_i64:
44; CHECK:       // %bb.0:
45; CHECK-NEXT:    add x8, x0, x1
46; CHECK-NEXT:    add x0, x8, #1 // =1
47; CHECK-NEXT:    ret
48  %t0 = add i64 %x, 1
49  %t1 = add i64 %y, %t0
50  ret i64 %t1
51}
52
53define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y) nounwind {
54; CHECK-LABEL: vector_i128_i8:
55; CHECK:       // %bb.0:
56; CHECK-NEXT:    mvn v0.16b, v0.16b
57; CHECK-NEXT:    sub v0.16b, v1.16b, v0.16b
58; CHECK-NEXT:    ret
59  %t0 = add <16 x i8> %x, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
60  %t1 = add <16 x i8> %y, %t0
61  ret <16 x i8> %t1
62}
63
64define <8 x i16> @vector_i128_i16(<8 x i16> %x, <8 x i16> %y) nounwind {
65; CHECK-LABEL: vector_i128_i16:
66; CHECK:       // %bb.0:
67; CHECK-NEXT:    mvn v0.16b, v0.16b
68; CHECK-NEXT:    sub v0.8h, v1.8h, v0.8h
69; CHECK-NEXT:    ret
70  %t0 = add <8 x i16> %x, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
71  %t1 = add <8 x i16> %y, %t0
72  ret <8 x i16> %t1
73}
74
75define <4 x i32> @vector_i128_i32(<4 x i32> %x, <4 x i32> %y) nounwind {
76; CHECK-LABEL: vector_i128_i32:
77; CHECK:       // %bb.0:
78; CHECK-NEXT:    mvn v0.16b, v0.16b
79; CHECK-NEXT:    sub v0.4s, v1.4s, v0.4s
80; CHECK-NEXT:    ret
81  %t0 = add <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
82  %t1 = add <4 x i32> %y, %t0
83  ret <4 x i32> %t1
84}
85
86define <2 x i64> @vector_i128_i64(<2 x i64> %x, <2 x i64> %y) nounwind {
87; CHECK-LABEL: vector_i128_i64:
88; CHECK:       // %bb.0:
89; CHECK-NEXT:    mvn v0.16b, v0.16b
90; CHECK-NEXT:    sub v0.2d, v1.2d, v0.2d
91; CHECK-NEXT:    ret
92  %t0 = add <2 x i64> %x, <i64 1, i64 1>
93  %t1 = add <2 x i64> %y, %t0
94  ret <2 x i64> %t1
95}
96