1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
3
4declare i4 @llvm.sadd.sat.i4(i4, i4)
5declare i8 @llvm.sadd.sat.i8(i8, i8)
6declare i16 @llvm.sadd.sat.i16(i16, i16)
7declare i32 @llvm.sadd.sat.i32(i32, i32)
8declare i64 @llvm.sadd.sat.i64(i64, i64)
9
10define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
11; CHECK-LABEL: func32:
12; CHECK:       // %bb.0:
13; CHECK-NEXT:    mul w8, w1, w2
14; CHECK-NEXT:    adds w10, w0, w8
15; CHECK-NEXT:    mov w9, #2147483647
16; CHECK-NEXT:    cmp w10, #0 // =0
17; CHECK-NEXT:    cinv w9, w9, ge
18; CHECK-NEXT:    adds w8, w0, w8
19; CHECK-NEXT:    csel w0, w9, w8, vs
20; CHECK-NEXT:    ret
21  %a = mul i32 %y, %z
22  %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %a)
23  ret i32 %tmp
24}
25
26define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
27; CHECK-LABEL: func64:
28; CHECK:       // %bb.0:
29; CHECK-NEXT:    adds x8, x0, x2
30; CHECK-NEXT:    mov x9, #9223372036854775807
31; CHECK-NEXT:    cmp x8, #0 // =0
32; CHECK-NEXT:    cinv x8, x9, ge
33; CHECK-NEXT:    adds x9, x0, x2
34; CHECK-NEXT:    csel x0, x8, x9, vs
35; CHECK-NEXT:    ret
36  %a = mul i64 %y, %z
37  %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %z)
38  ret i64 %tmp
39}
40
41define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
42; CHECK-LABEL: func16:
43; CHECK:       // %bb.0:
44; CHECK-NEXT:    sxth w8, w0
45; CHECK-NEXT:    mul w9, w1, w2
46; CHECK-NEXT:    mov w10, #32767
47; CHECK-NEXT:    add w8, w8, w9, sxth
48; CHECK-NEXT:    cmp w8, w10
49; CHECK-NEXT:    csel w8, w8, w10, lt
50; CHECK-NEXT:    cmn w8, #8, lsl #12 // =32768
51; CHECK-NEXT:    mov w9, #-32768
52; CHECK-NEXT:    csel w0, w8, w9, gt
53; CHECK-NEXT:    ret
54  %a = mul i16 %y, %z
55  %tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %a)
56  ret i16 %tmp
57}
58
59define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
60; CHECK-LABEL: func8:
61; CHECK:       // %bb.0:
62; CHECK-NEXT:    sxtb w8, w0
63; CHECK-NEXT:    mul w9, w1, w2
64; CHECK-NEXT:    add w8, w8, w9, sxtb
65; CHECK-NEXT:    mov w10, #127
66; CHECK-NEXT:    cmp w8, #127 // =127
67; CHECK-NEXT:    csel w8, w8, w10, lt
68; CHECK-NEXT:    cmn w8, #128 // =128
69; CHECK-NEXT:    mov w9, #-128
70; CHECK-NEXT:    csel w0, w8, w9, gt
71; CHECK-NEXT:    ret
72  %a = mul i8 %y, %z
73  %tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %a)
74  ret i8 %tmp
75}
76
77define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
78; CHECK-LABEL: func4:
79; CHECK:       // %bb.0:
80; CHECK-NEXT:    mul w9, w1, w2
81; CHECK-NEXT:    sbfx w8, w0, #0, #4
82; CHECK-NEXT:    lsl w9, w9, #28
83; CHECK-NEXT:    add w8, w8, w9, asr #28
84; CHECK-NEXT:    mov w10, #7
85; CHECK-NEXT:    cmp w8, #7 // =7
86; CHECK-NEXT:    csel w8, w8, w10, lt
87; CHECK-NEXT:    cmn w8, #8 // =8
88; CHECK-NEXT:    mov w9, #-8
89; CHECK-NEXT:    csel w0, w8, w9, gt
90; CHECK-NEXT:    ret
91  %a = mul i4 %y, %z
92  %tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %a)
93  ret i4 %tmp
94}
95