1; RUN: llc -aarch64-sve-vector-bits-min=128 < %s | FileCheck %s -D#VBYTES=16 -check-prefix=NO_SVE 2; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -D#VBYTES=32 -check-prefixes=CHECK,VBITS_LE_1024,VBITS_LE_512,VBITS_LE_256 3; RUN: llc -aarch64-sve-vector-bits-min=384 < %s | FileCheck %s -D#VBYTES=32 -check-prefixes=CHECK,VBITS_LE_1024,VBITS_LE_512,VBITS_LE_256 4; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -D#VBYTES=64 -check-prefixes=CHECK,VBITS_LE_1024,VBITS_LE_512 5; RUN: llc -aarch64-sve-vector-bits-min=640 < %s | FileCheck %s -D#VBYTES=64 -check-prefixes=CHECK,VBITS_LE_1024,VBITS_LE_512 6; RUN: llc -aarch64-sve-vector-bits-min=768 < %s | FileCheck %s -D#VBYTES=64 -check-prefixes=CHECK,VBITS_LE_1024,VBITS_LE_512 7; RUN: llc -aarch64-sve-vector-bits-min=896 < %s | FileCheck %s -D#VBYTES=64 -check-prefixes=CHECK,VBITS_LE_1024,VBITS_LE_512 8; RUN: llc -aarch64-sve-vector-bits-min=1024 < %s | FileCheck %s -D#VBYTES=128 -check-prefixes=CHECK,VBITS_LE_1024 9; RUN: llc -aarch64-sve-vector-bits-min=1152 < %s | FileCheck %s -D#VBYTES=128 -check-prefixes=CHECK,VBITS_LE_1024 10; RUN: llc -aarch64-sve-vector-bits-min=1280 < %s | FileCheck %s -D#VBYTES=128 -check-prefixes=CHECK,VBITS_LE_1024 11; RUN: llc -aarch64-sve-vector-bits-min=1408 < %s | FileCheck %s -D#VBYTES=128 -check-prefixes=CHECK,VBITS_LE_1024 12; RUN: llc -aarch64-sve-vector-bits-min=1536 < %s | FileCheck %s -D#VBYTES=128 -check-prefixes=CHECK,VBITS_LE_1024 13; RUN: llc -aarch64-sve-vector-bits-min=1664 < %s | FileCheck %s -D#VBYTES=128 -check-prefixes=CHECK,VBITS_LE_1024 14; RUN: llc -aarch64-sve-vector-bits-min=1792 < %s | FileCheck %s -D#VBYTES=128 -check-prefixes=CHECK,VBITS_LE_1024 15; RUN: llc -aarch64-sve-vector-bits-min=1920 < %s | FileCheck %s -D#VBYTES=128 -check-prefixes=CHECK,VBITS_LE_1024 16; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -D#VBYTES=256 -check-prefixes=CHECK 17 18; VBYTES represents the useful byte size of a vector register from the code 19; generator's point of view. It is clamped to power-of-2 values because 20; only power-of-2 vector lengths are considered legal, regardless of the 21; user specified vector length. 22 23target triple = "aarch64-unknown-linux-gnu" 24 25; Don't use SVE when its registers are no bigger than NEON. 26; NO_SVE-NOT: ptrue 27 28; Don't use SVE for 64-bit vectors. 29define <2 x float> @load_v2f32(<2 x float>* %a) #0 { 30; CHECK-LABEL: load_v2f32: 31; CHECK: ldr d0, [x0] 32; CHECK: ret 33 %load = load <2 x float>, <2 x float>* %a 34 ret <2 x float> %load 35} 36 37; Don't use SVE for 128-bit vectors. 38define <4 x float> @load_v4f32(<4 x float>* %a) #0 { 39; CHECK-LABEL: load_v4f32: 40; CHECK: ldr q0, [x0] 41; CHECK: ret 42 %load = load <4 x float>, <4 x float>* %a 43 ret <4 x float> %load 44} 45 46define <8 x float> @load_v8f32(<8 x float>* %a) #0 { 47; CHECK-LABEL: load_v8f32: 48; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),8)]] 49; CHECK: ld1w { z{{[0-9]+}}.s }, [[PG]]/z, [x0] 50; CHECK: ret 51 %load = load <8 x float>, <8 x float>* %a 52 ret <8 x float> %load 53} 54 55define <16 x float> @load_v16f32(<16 x float>* %a) #0 { 56; CHECK-LABEL: load_v16f32: 57; CHECK-DAG: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),16)]] 58; CHECK-DAG: ld1w { z{{[0-9]+}}.s }, [[PG]]/z, [x0] 59; VBITS_LE_256-DAG: add x[[A1:[0-9]+]], x0, #[[#VBYTES]] 60; VBITS_LE_256-DAG: ld1w { z{{[0-9]+}}.s }, [[PG]]/z, [x[[A1]]] 61; CHECK: ret 62 %load = load <16 x float>, <16 x float>* %a 63 ret <16 x float> %load 64} 65 66define <32 x float> @load_v32f32(<32 x float>* %a) #0 { 67; CHECK-LABEL: load_v32f32: 68; CHECK-DAG: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),32)]] 69; CHECK-DAG: ld1w { z{{[0-9]+}}.s }, [[PG]]/z, [x0] 70; VBITS_LE_512-DAG: add x[[A1:[0-9]+]], x0, #[[#VBYTES]] 71; VBITS_LE_512-DAG: ld1w { z{{[0-9]+}}.s }, [[PG]]/z, [x[[A1]]] 72; VBITS_LE_256-DAG: add x[[A2:[0-9]+]], x0, #[[#mul(VBYTES,2)]] 73; VBITS_LE_256-DAG: ld1w { z{{[0-9]+}}.s }, [[PG]]/z, [x[[A2]]] 74; VBITS_LE_256-DAG: add x[[A3:[0-9]+]], x0, #[[#mul(VBYTES,3)]] 75; VBITS_LE_256-DAG: ld1w { z{{[0-9]+}}.s }, [[PG]]/z, [x[[A3]]] 76; CHECK: ret 77 %load = load <32 x float>, <32 x float>* %a 78 ret <32 x float> %load 79} 80 81define <64 x float> @load_v64f32(<64 x float>* %a) #0 { 82; CHECK-LABEL: load_v64f32: 83; CHECK-DAG: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),64)]] 84; CHECK-DAG: ld1w { z{{[0-9]+}}.s }, [[PG]]/z, [x0] 85; VBITS_LE_1024-DAG: add x[[A1:[0-9]+]], x0, #[[#VBYTES]] 86; VBITS_LE_1024-DAG: ld1w { z{{[0-9]+}}.s }, [[PG]]/z, [x[[A1]]] 87; VBITS_LE_512-DAG: add x[[A2:[0-9]+]], x0, #[[#mul(VBYTES,2)]] 88; VBITS_LE_512-DAG: ld1w { z{{[0-9]+}}.s }, [[PG]]/z, [x[[A2]]] 89; VBITS_LE_512-DAG: add x[[A3:[0-9]+]], x0, #[[#mul(VBYTES,3)]] 90; VBITS_LE_512-DAG: ld1w { z{{[0-9]+}}.s }, [[PG]]/z, [x[[A3]]] 91; VBITS_LE_256-DAG: add x[[A4:[0-9]+]], x0, #[[#mul(VBYTES,4)]] 92; VBITS_LE_256-DAG: ld1w { z{{[0-9]+}}.s }, [[PG]]/z, [x[[A4]]] 93; VBITS_LE_256-DAG: add x[[A5:[0-9]+]], x0, #[[#mul(VBYTES,5)]] 94; VBITS_LE_256-DAG: ld1w { z{{[0-9]+}}.s }, [[PG]]/z, [x[[A5]]] 95; VBITS_LE_256-DAG: add x[[A6:[0-9]+]], x0, #[[#mul(VBYTES,6)]] 96; VBITS_LE_256-DAG: ld1w { z{{[0-9]+}}.s }, [[PG]]/z, [x[[A6]]] 97; VBITS_LE_256-DAG: add x[[A7:[0-9]+]], x0, #[[#mul(VBYTES,7)]] 98; VBITS_LE_256-DAG: ld1w { z{{[0-9]+}}.s }, [[PG]]/z, [x[[A7]]] 99; CHECK: ret 100 %load = load <64 x float>, <64 x float>* %a 101 ret <64 x float> %load 102} 103 104attributes #0 = { "target-features"="+sve" } 105