1; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve -asm-verbose=0 < %s 2>%t | FileCheck %s 2; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t 3 4; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it. 5; WARN-NOT: warning 6 7; 8; FADDA 9; 10 11define half @fadda_f16(<vscale x 8 x i1> %pg, half %init, <vscale x 8 x half> %a) { 12; CHECK-LABEL: fadda_f16: 13; CHECK: fadda h0, p0, h0, z1.h 14; CHECK-NEXT: ret 15 %res = call half @llvm.aarch64.sve.fadda.nxv8f16(<vscale x 8 x i1> %pg, 16 half %init, 17 <vscale x 8 x half> %a) 18 ret half %res 19} 20 21define float @fadda_f32(<vscale x 4 x i1> %pg, float %init, <vscale x 4 x float> %a) { 22; CHECK-LABEL: fadda_f32: 23; CHECK: fadda s0, p0, s0, z1.s 24; CHECK-NEXT: ret 25 %res = call float @llvm.aarch64.sve.fadda.nxv4f32(<vscale x 4 x i1> %pg, 26 float %init, 27 <vscale x 4 x float> %a) 28 ret float %res 29} 30 31define double @fadda_f64(<vscale x 2 x i1> %pg, double %init, <vscale x 2 x double> %a) { 32; CHECK-LABEL: fadda_f64: 33; CHECK: fadda d0, p0, d0, z1.d 34; CHECK-NEXT: ret 35 %res = call double @llvm.aarch64.sve.fadda.nxv2f64(<vscale x 2 x i1> %pg, 36 double %init, 37 <vscale x 2 x double> %a) 38 ret double %res 39} 40 41; 42; FADDV 43; 44 45define half @faddv_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) { 46; CHECK-LABEL: faddv_f16: 47; CHECK: faddv h0, p0, z0.h 48; CHECK-NEXT: ret 49 %res = call half @llvm.aarch64.sve.faddv.nxv8f16(<vscale x 8 x i1> %pg, 50 <vscale x 8 x half> %a) 51 ret half %res 52} 53 54define float @faddv_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) { 55; CHECK-LABEL: faddv_f32: 56; CHECK: faddv s0, p0, z0.s 57; CHECK-NEXT: ret 58 %res = call float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1> %pg, 59 <vscale x 4 x float> %a) 60 ret float %res 61} 62 63define double @faddv_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) { 64; CHECK-LABEL: faddv_f64: 65; CHECK: faddv d0, p0, z0.d 66; CHECK-NEXT: ret 67 %res = call double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1> %pg, 68 <vscale x 2 x double> %a) 69 ret double %res 70} 71 72; 73; FMAXNMV 74; 75 76define half @fmaxnmv_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) { 77; CHECK-LABEL: fmaxnmv_f16: 78; CHECK: fmaxnmv h0, p0, z0.h 79; CHECK-NEXT: ret 80 %res = call half @llvm.aarch64.sve.fmaxnmv.nxv8f16(<vscale x 8 x i1> %pg, 81 <vscale x 8 x half> %a) 82 ret half %res 83} 84 85define float @fmaxnmv_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) { 86; CHECK-LABEL: fmaxnmv_f32: 87; CHECK: fmaxnmv s0, p0, z0.s 88; CHECK-NEXT: ret 89 %res = call float @llvm.aarch64.sve.fmaxnmv.nxv4f32(<vscale x 4 x i1> %pg, 90 <vscale x 4 x float> %a) 91 ret float %res 92} 93 94define double @fmaxnmv_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) { 95; CHECK-LABEL: fmaxnmv_f64: 96; CHECK: fmaxnmv d0, p0, z0.d 97; CHECK-NEXT: ret 98 %res = call double @llvm.aarch64.sve.fmaxnmv.nxv2f64(<vscale x 2 x i1> %pg, 99 <vscale x 2 x double> %a) 100 ret double %res 101} 102 103; 104; FMAXV 105; 106 107define half @fmaxv_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) { 108; CHECK-LABEL: fmaxv_f16: 109; CHECK: fmaxv h0, p0, z0.h 110; CHECK-NEXT: ret 111 %res = call half @llvm.aarch64.sve.fmaxv.nxv8f16(<vscale x 8 x i1> %pg, 112 <vscale x 8 x half> %a) 113 ret half %res 114} 115 116define float @fmaxv_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) { 117; CHECK-LABEL: fmaxv_f32: 118; CHECK: fmaxv s0, p0, z0.s 119; CHECK-NEXT: ret 120 %res = call float @llvm.aarch64.sve.fmaxv.nxv4f32(<vscale x 4 x i1> %pg, 121 <vscale x 4 x float> %a) 122 ret float %res 123} 124 125define double @fmaxv_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) { 126; CHECK-LABEL: fmaxv_f64: 127; CHECK: fmaxv d0, p0, z0.d 128; CHECK-NEXT: ret 129 %res = call double @llvm.aarch64.sve.fmaxv.nxv2f64(<vscale x 2 x i1> %pg, 130 <vscale x 2 x double> %a) 131 ret double %res 132} 133 134; 135; FMINNMV 136; 137 138define half @fminnmv_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) { 139; CHECK-LABEL: fminnmv_f16: 140; CHECK: fminnmv h0, p0, z0.h 141; CHECK-NEXT: ret 142 %res = call half @llvm.aarch64.sve.fminnmv.nxv8f16(<vscale x 8 x i1> %pg, 143 <vscale x 8 x half> %a) 144 ret half %res 145} 146 147define float @fminnmv_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) { 148; CHECK-LABEL: fminnmv_f32: 149; CHECK: fminnmv s0, p0, z0.s 150; CHECK-NEXT: ret 151 %res = call float @llvm.aarch64.sve.fminnmv.nxv4f32(<vscale x 4 x i1> %pg, 152 <vscale x 4 x float> %a) 153 ret float %res 154} 155 156define double @fminnmv_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) { 157; CHECK-LABEL: fminnmv_f64: 158; CHECK: fminnmv d0, p0, z0.d 159; CHECK-NEXT: ret 160 %res = call double @llvm.aarch64.sve.fminnmv.nxv2f64(<vscale x 2 x i1> %pg, 161 <vscale x 2 x double> %a) 162 ret double %res 163} 164 165; 166; FMINV 167; 168 169define half @fminv_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) { 170; CHECK-LABEL: fminv_f16: 171; CHECK: fminv h0, p0, z0.h 172; CHECK-NEXT: ret 173 %res = call half @llvm.aarch64.sve.fminv.nxv8f16(<vscale x 8 x i1> %pg, 174 <vscale x 8 x half> %a) 175 ret half %res 176} 177 178define float @fminv_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) { 179; CHECK-LABEL: fminv_f32: 180; CHECK: fminv s0, p0, z0.s 181; CHECK-NEXT: ret 182 %res = call float @llvm.aarch64.sve.fminv.nxv4f32(<vscale x 4 x i1> %pg, 183 <vscale x 4 x float> %a) 184 ret float %res 185} 186 187define double @fminv_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) { 188; CHECK-LABEL: fminv_f64: 189; CHECK: fminv d0, p0, z0.d 190; CHECK-NEXT: ret 191 %res = call double @llvm.aarch64.sve.fminv.nxv2f64(<vscale x 2 x i1> %pg, 192 <vscale x 2 x double> %a) 193 ret double %res 194} 195 196declare half @llvm.aarch64.sve.fadda.nxv8f16(<vscale x 8 x i1>, half, <vscale x 8 x half>) 197declare float @llvm.aarch64.sve.fadda.nxv4f32(<vscale x 4 x i1>, float, <vscale x 4 x float>) 198declare double @llvm.aarch64.sve.fadda.nxv2f64(<vscale x 2 x i1>, double, <vscale x 2 x double>) 199 200declare half @llvm.aarch64.sve.faddv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) 201declare float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) 202declare double @llvm.aarch64.sve.faddv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) 203 204declare half @llvm.aarch64.sve.fmaxnmv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) 205declare float @llvm.aarch64.sve.fmaxnmv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) 206declare double @llvm.aarch64.sve.fmaxnmv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) 207 208declare half @llvm.aarch64.sve.fmaxv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) 209declare float @llvm.aarch64.sve.fmaxv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) 210declare double @llvm.aarch64.sve.fmaxv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) 211 212declare half @llvm.aarch64.sve.fminnmv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) 213declare float @llvm.aarch64.sve.fminnmv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) 214declare double @llvm.aarch64.sve.fminnmv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) 215 216declare half @llvm.aarch64.sve.fminv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) 217declare float @llvm.aarch64.sve.fminv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) 218declare double @llvm.aarch64.sve.fminv.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) 219