1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 -asm-verbose=0 -mattr=+use-experimental-zeroing-pseudos < %s | FileCheck %s 2 3; 4; SQSHLU 5; 6 7define <vscale x 16 x i8> @sqshlu_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) { 8; CHECK-LABEL: sqshlu_i8: 9; CHECK: movprfx z0.b, p0/z, z0.b 10; CHECK-NEXT: sqshlu z0.b, p0/m, z0.b, #2 11; CHECK-NEXT: ret 12 %a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer 13 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqshlu.nxv16i8(<vscale x 16 x i1> %pg, 14 <vscale x 16 x i8> %a_z, 15 i32 2) 16 ret <vscale x 16 x i8> %out 17} 18 19define <vscale x 8 x i16> @sqshlu_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) { 20; CHECK-LABEL: sqshlu_i16: 21; CHECK: movprfx z0.h, p0/z, z0.h 22; CHECK-NEXT: sqshlu z0.h, p0/m, z0.h, #3 23; CHECK-NEXT: ret 24 %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer 25 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqshlu.nxv8i16(<vscale x 8 x i1> %pg, 26 <vscale x 8 x i16> %a_z, 27 i32 3) 28 ret <vscale x 8 x i16> %out 29} 30 31define <vscale x 4 x i32> @sqshlu_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) { 32; CHECK-LABEL: sqshlu_i32: 33; CHECK: movprfx z0.s, p0/z, z0.s 34; CHECK-NEXT: sqshlu z0.s, p0/m, z0.s, #29 35; CHECK-NEXT: ret 36 %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer 37 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqshlu.nxv4i32(<vscale x 4 x i1> %pg, 38 <vscale x 4 x i32> %a_z, 39 i32 29) 40 ret <vscale x 4 x i32> %out 41} 42 43define <vscale x 2 x i64> @sqshlu_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) { 44; CHECK-LABEL: sqshlu_i64: 45; CHECK: movprfx z0.d, p0/z, z0.d 46; CHECK-NEXT: sqshlu z0.d, p0/m, z0.d, #62 47; CHECK-NEXT: ret 48 %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer 49 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqshlu.nxv2i64(<vscale x 2 x i1> %pg, 50 <vscale x 2 x i64> %a_z, 51 i32 62) 52 ret <vscale x 2 x i64> %out 53} 54 55declare <vscale x 16 x i8> @llvm.aarch64.sve.sqshlu.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, i32) 56declare <vscale x 8 x i16> @llvm.aarch64.sve.sqshlu.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, i32) 57declare <vscale x 4 x i32> @llvm.aarch64.sve.sqshlu.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i32) 58declare <vscale x 2 x i64> @llvm.aarch64.sve.sqshlu.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i32) 59