1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK 3 4declare {<1 x i32>, <1 x i1>} @llvm.uadd.with.overflow.v1i32(<1 x i32>, <1 x i32>) 5declare {<2 x i32>, <2 x i1>} @llvm.uadd.with.overflow.v2i32(<2 x i32>, <2 x i32>) 6declare {<3 x i32>, <3 x i1>} @llvm.uadd.with.overflow.v3i32(<3 x i32>, <3 x i32>) 7declare {<4 x i32>, <4 x i1>} @llvm.uadd.with.overflow.v4i32(<4 x i32>, <4 x i32>) 8declare {<6 x i32>, <6 x i1>} @llvm.uadd.with.overflow.v6i32(<6 x i32>, <6 x i32>) 9declare {<8 x i32>, <8 x i1>} @llvm.uadd.with.overflow.v8i32(<8 x i32>, <8 x i32>) 10 11declare {<16 x i8>, <16 x i1>} @llvm.uadd.with.overflow.v16i8(<16 x i8>, <16 x i8>) 12declare {<8 x i16>, <8 x i1>} @llvm.uadd.with.overflow.v8i16(<8 x i16>, <8 x i16>) 13declare {<2 x i64>, <2 x i1>} @llvm.uadd.with.overflow.v2i64(<2 x i64>, <2 x i64>) 14 15declare {<4 x i24>, <4 x i1>} @llvm.uadd.with.overflow.v4i24(<4 x i24>, <4 x i24>) 16declare {<4 x i1>, <4 x i1>} @llvm.uadd.with.overflow.v4i1(<4 x i1>, <4 x i1>) 17declare {<2 x i128>, <2 x i1>} @llvm.uadd.with.overflow.v2i128(<2 x i128>, <2 x i128>) 18 19define <1 x i32> @uaddo_v1i32(<1 x i32> %a0, <1 x i32> %a1, <1 x i32>* %p2) nounwind { 20; CHECK-LABEL: uaddo_v1i32: 21; CHECK: // %bb.0: 22; CHECK-NEXT: add v1.2s, v0.2s, v1.2s 23; CHECK-NEXT: cmhi v0.2s, v0.2s, v1.2s 24; CHECK-NEXT: str s1, [x0] 25; CHECK-NEXT: ret 26 %t = call {<1 x i32>, <1 x i1>} @llvm.uadd.with.overflow.v1i32(<1 x i32> %a0, <1 x i32> %a1) 27 %val = extractvalue {<1 x i32>, <1 x i1>} %t, 0 28 %obit = extractvalue {<1 x i32>, <1 x i1>} %t, 1 29 %res = sext <1 x i1> %obit to <1 x i32> 30 store <1 x i32> %val, <1 x i32>* %p2 31 ret <1 x i32> %res 32} 33 34define <2 x i32> @uaddo_v2i32(<2 x i32> %a0, <2 x i32> %a1, <2 x i32>* %p2) nounwind { 35; CHECK-LABEL: uaddo_v2i32: 36; CHECK: // %bb.0: 37; CHECK-NEXT: add v1.2s, v0.2s, v1.2s 38; CHECK-NEXT: cmhi v0.2s, v0.2s, v1.2s 39; CHECK-NEXT: str d1, [x0] 40; CHECK-NEXT: ret 41 %t = call {<2 x i32>, <2 x i1>} @llvm.uadd.with.overflow.v2i32(<2 x i32> %a0, <2 x i32> %a1) 42 %val = extractvalue {<2 x i32>, <2 x i1>} %t, 0 43 %obit = extractvalue {<2 x i32>, <2 x i1>} %t, 1 44 %res = sext <2 x i1> %obit to <2 x i32> 45 store <2 x i32> %val, <2 x i32>* %p2 46 ret <2 x i32> %res 47} 48 49define <3 x i32> @uaddo_v3i32(<3 x i32> %a0, <3 x i32> %a1, <3 x i32>* %p2) nounwind { 50; CHECK-LABEL: uaddo_v3i32: 51; CHECK: // %bb.0: 52; CHECK-NEXT: add v1.4s, v0.4s, v1.4s 53; CHECK-NEXT: add x8, x0, #8 // =8 54; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s 55; CHECK-NEXT: st1 { v1.s }[2], [x8] 56; CHECK-NEXT: str d1, [x0] 57; CHECK-NEXT: ret 58 %t = call {<3 x i32>, <3 x i1>} @llvm.uadd.with.overflow.v3i32(<3 x i32> %a0, <3 x i32> %a1) 59 %val = extractvalue {<3 x i32>, <3 x i1>} %t, 0 60 %obit = extractvalue {<3 x i32>, <3 x i1>} %t, 1 61 %res = sext <3 x i1> %obit to <3 x i32> 62 store <3 x i32> %val, <3 x i32>* %p2 63 ret <3 x i32> %res 64} 65 66define <4 x i32> @uaddo_v4i32(<4 x i32> %a0, <4 x i32> %a1, <4 x i32>* %p2) nounwind { 67; CHECK-LABEL: uaddo_v4i32: 68; CHECK: // %bb.0: 69; CHECK-NEXT: add v1.4s, v0.4s, v1.4s 70; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s 71; CHECK-NEXT: str q1, [x0] 72; CHECK-NEXT: ret 73 %t = call {<4 x i32>, <4 x i1>} @llvm.uadd.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> %a1) 74 %val = extractvalue {<4 x i32>, <4 x i1>} %t, 0 75 %obit = extractvalue {<4 x i32>, <4 x i1>} %t, 1 76 %res = sext <4 x i1> %obit to <4 x i32> 77 store <4 x i32> %val, <4 x i32>* %p2 78 ret <4 x i32> %res 79} 80 81define <6 x i32> @uaddo_v6i32(<6 x i32> %a0, <6 x i32> %a1, <6 x i32>* %p2) nounwind { 82; CHECK-LABEL: uaddo_v6i32: 83; CHECK: // %bb.0: 84; CHECK-NEXT: fmov s2, w6 85; CHECK-NEXT: ldr s0, [sp, #16] 86; CHECK-NEXT: mov x9, sp 87; CHECK-NEXT: mov v2.s[1], w7 88; CHECK-NEXT: ld1 { v2.s }[2], [x9] 89; CHECK-NEXT: add x8, sp, #24 // =24 90; CHECK-NEXT: add x10, sp, #8 // =8 91; CHECK-NEXT: ld1 { v0.s }[1], [x8] 92; CHECK-NEXT: fmov s3, w0 93; CHECK-NEXT: ldr x11, [sp, #32] 94; CHECK-NEXT: ld1 { v2.s }[3], [x10] 95; CHECK-NEXT: fmov s1, w4 96; CHECK-NEXT: mov v3.s[1], w1 97; CHECK-NEXT: mov v1.s[1], w5 98; CHECK-NEXT: mov v3.s[2], w2 99; CHECK-NEXT: mov v3.s[3], w3 100; CHECK-NEXT: add v0.4s, v1.4s, v0.4s 101; CHECK-NEXT: cmhi v1.4s, v1.4s, v0.4s 102; CHECK-NEXT: str d0, [x11, #16] 103; CHECK-NEXT: add v0.4s, v3.4s, v2.4s 104; CHECK-NEXT: cmhi v2.4s, v3.4s, v0.4s 105; CHECK-NEXT: mov w5, v1.s[1] 106; CHECK-NEXT: mov w1, v2.s[1] 107; CHECK-NEXT: mov w2, v2.s[2] 108; CHECK-NEXT: mov w3, v2.s[3] 109; CHECK-NEXT: fmov w4, s1 110; CHECK-NEXT: fmov w0, s2 111; CHECK-NEXT: str q0, [x11] 112; CHECK-NEXT: ret 113 %t = call {<6 x i32>, <6 x i1>} @llvm.uadd.with.overflow.v6i32(<6 x i32> %a0, <6 x i32> %a1) 114 %val = extractvalue {<6 x i32>, <6 x i1>} %t, 0 115 %obit = extractvalue {<6 x i32>, <6 x i1>} %t, 1 116 %res = sext <6 x i1> %obit to <6 x i32> 117 store <6 x i32> %val, <6 x i32>* %p2 118 ret <6 x i32> %res 119} 120 121define <8 x i32> @uaddo_v8i32(<8 x i32> %a0, <8 x i32> %a1, <8 x i32>* %p2) nounwind { 122; CHECK-LABEL: uaddo_v8i32: 123; CHECK: // %bb.0: 124; CHECK-NEXT: add v2.4s, v0.4s, v2.4s 125; CHECK-NEXT: add v3.4s, v1.4s, v3.4s 126; CHECK-NEXT: cmhi v0.4s, v0.4s, v2.4s 127; CHECK-NEXT: cmhi v1.4s, v1.4s, v3.4s 128; CHECK-NEXT: stp q2, q3, [x0] 129; CHECK-NEXT: ret 130 %t = call {<8 x i32>, <8 x i1>} @llvm.uadd.with.overflow.v8i32(<8 x i32> %a0, <8 x i32> %a1) 131 %val = extractvalue {<8 x i32>, <8 x i1>} %t, 0 132 %obit = extractvalue {<8 x i32>, <8 x i1>} %t, 1 133 %res = sext <8 x i1> %obit to <8 x i32> 134 store <8 x i32> %val, <8 x i32>* %p2 135 ret <8 x i32> %res 136} 137 138define <16 x i32> @uaddo_v16i8(<16 x i8> %a0, <16 x i8> %a1, <16 x i8>* %p2) nounwind { 139; CHECK-LABEL: uaddo_v16i8: 140; CHECK: // %bb.0: 141; CHECK-NEXT: add v4.16b, v0.16b, v1.16b 142; CHECK-NEXT: cmhi v0.16b, v0.16b, v4.16b 143; CHECK-NEXT: zip1 v1.8b, v0.8b, v0.8b 144; CHECK-NEXT: zip2 v2.8b, v0.8b, v0.8b 145; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 146; CHECK-NEXT: ushll v1.4s, v1.4h, #0 147; CHECK-NEXT: ushll v2.4s, v2.4h, #0 148; CHECK-NEXT: zip1 v3.8b, v0.8b, v0.8b 149; CHECK-NEXT: zip2 v0.8b, v0.8b, v0.8b 150; CHECK-NEXT: shl v1.4s, v1.4s, #31 151; CHECK-NEXT: shl v2.4s, v2.4s, #31 152; CHECK-NEXT: ushll v3.4s, v3.4h, #0 153; CHECK-NEXT: ushll v5.4s, v0.4h, #0 154; CHECK-NEXT: sshr v0.4s, v1.4s, #31 155; CHECK-NEXT: sshr v1.4s, v2.4s, #31 156; CHECK-NEXT: shl v2.4s, v3.4s, #31 157; CHECK-NEXT: shl v3.4s, v5.4s, #31 158; CHECK-NEXT: sshr v2.4s, v2.4s, #31 159; CHECK-NEXT: sshr v3.4s, v3.4s, #31 160; CHECK-NEXT: str q4, [x0] 161; CHECK-NEXT: ret 162 %t = call {<16 x i8>, <16 x i1>} @llvm.uadd.with.overflow.v16i8(<16 x i8> %a0, <16 x i8> %a1) 163 %val = extractvalue {<16 x i8>, <16 x i1>} %t, 0 164 %obit = extractvalue {<16 x i8>, <16 x i1>} %t, 1 165 %res = sext <16 x i1> %obit to <16 x i32> 166 store <16 x i8> %val, <16 x i8>* %p2 167 ret <16 x i32> %res 168} 169 170define <8 x i32> @uaddo_v8i16(<8 x i16> %a0, <8 x i16> %a1, <8 x i16>* %p2) nounwind { 171; CHECK-LABEL: uaddo_v8i16: 172; CHECK: // %bb.0: 173; CHECK-NEXT: add v2.8h, v0.8h, v1.8h 174; CHECK-NEXT: cmhi v0.8h, v0.8h, v2.8h 175; CHECK-NEXT: xtn v0.8b, v0.8h 176; CHECK-NEXT: zip1 v1.8b, v0.8b, v0.8b 177; CHECK-NEXT: zip2 v0.8b, v0.8b, v0.8b 178; CHECK-NEXT: ushll v1.4s, v1.4h, #0 179; CHECK-NEXT: ushll v0.4s, v0.4h, #0 180; CHECK-NEXT: shl v1.4s, v1.4s, #31 181; CHECK-NEXT: shl v3.4s, v0.4s, #31 182; CHECK-NEXT: sshr v0.4s, v1.4s, #31 183; CHECK-NEXT: sshr v1.4s, v3.4s, #31 184; CHECK-NEXT: str q2, [x0] 185; CHECK-NEXT: ret 186 %t = call {<8 x i16>, <8 x i1>} @llvm.uadd.with.overflow.v8i16(<8 x i16> %a0, <8 x i16> %a1) 187 %val = extractvalue {<8 x i16>, <8 x i1>} %t, 0 188 %obit = extractvalue {<8 x i16>, <8 x i1>} %t, 1 189 %res = sext <8 x i1> %obit to <8 x i32> 190 store <8 x i16> %val, <8 x i16>* %p2 191 ret <8 x i32> %res 192} 193 194define <2 x i32> @uaddo_v2i64(<2 x i64> %a0, <2 x i64> %a1, <2 x i64>* %p2) nounwind { 195; CHECK-LABEL: uaddo_v2i64: 196; CHECK: // %bb.0: 197; CHECK-NEXT: add v1.2d, v0.2d, v1.2d 198; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d 199; CHECK-NEXT: xtn v0.2s, v0.2d 200; CHECK-NEXT: str q1, [x0] 201; CHECK-NEXT: ret 202 %t = call {<2 x i64>, <2 x i1>} @llvm.uadd.with.overflow.v2i64(<2 x i64> %a0, <2 x i64> %a1) 203 %val = extractvalue {<2 x i64>, <2 x i1>} %t, 0 204 %obit = extractvalue {<2 x i64>, <2 x i1>} %t, 1 205 %res = sext <2 x i1> %obit to <2 x i32> 206 store <2 x i64> %val, <2 x i64>* %p2 207 ret <2 x i32> %res 208} 209 210define <4 x i32> @uaddo_v4i24(<4 x i24> %a0, <4 x i24> %a1, <4 x i24>* %p2) nounwind { 211; CHECK-LABEL: uaddo_v4i24: 212; CHECK: // %bb.0: 213; CHECK-NEXT: bic v1.4s, #255, lsl #24 214; CHECK-NEXT: bic v0.4s, #255, lsl #24 215; CHECK-NEXT: add v0.4s, v0.4s, v1.4s 216; CHECK-NEXT: mov v1.16b, v0.16b 217; CHECK-NEXT: mov w8, v0.s[3] 218; CHECK-NEXT: bic v1.4s, #255, lsl #24 219; CHECK-NEXT: mov w9, v0.s[2] 220; CHECK-NEXT: mov w10, v0.s[1] 221; CHECK-NEXT: sturh w8, [x0, #9] 222; CHECK-NEXT: lsr w8, w8, #16 223; CHECK-NEXT: cmeq v1.4s, v1.4s, v0.4s 224; CHECK-NEXT: fmov w11, s0 225; CHECK-NEXT: strh w9, [x0, #6] 226; CHECK-NEXT: sturh w10, [x0, #3] 227; CHECK-NEXT: lsr w9, w9, #16 228; CHECK-NEXT: lsr w10, w10, #16 229; CHECK-NEXT: strb w8, [x0, #11] 230; CHECK-NEXT: mvn v0.16b, v1.16b 231; CHECK-NEXT: lsr w8, w11, #16 232; CHECK-NEXT: strh w11, [x0] 233; CHECK-NEXT: strb w9, [x0, #8] 234; CHECK-NEXT: strb w10, [x0, #5] 235; CHECK-NEXT: strb w8, [x0, #2] 236; CHECK-NEXT: ret 237 %t = call {<4 x i24>, <4 x i1>} @llvm.uadd.with.overflow.v4i24(<4 x i24> %a0, <4 x i24> %a1) 238 %val = extractvalue {<4 x i24>, <4 x i1>} %t, 0 239 %obit = extractvalue {<4 x i24>, <4 x i1>} %t, 1 240 %res = sext <4 x i1> %obit to <4 x i32> 241 store <4 x i24> %val, <4 x i24>* %p2 242 ret <4 x i32> %res 243} 244 245define <4 x i32> @uaddo_v4i1(<4 x i1> %a0, <4 x i1> %a1, <4 x i1>* %p2) nounwind { 246; CHECK-LABEL: uaddo_v4i1: 247; CHECK: // %bb.0: 248; CHECK-NEXT: movi v2.4h, #1 249; CHECK-NEXT: and v1.8b, v1.8b, v2.8b 250; CHECK-NEXT: and v0.8b, v0.8b, v2.8b 251; CHECK-NEXT: add v1.4h, v0.4h, v1.4h 252; CHECK-NEXT: umov w9, v1.h[1] 253; CHECK-NEXT: umov w8, v1.h[0] 254; CHECK-NEXT: and w9, w9, #0x1 255; CHECK-NEXT: bfi w8, w9, #1, #1 256; CHECK-NEXT: umov w9, v1.h[2] 257; CHECK-NEXT: and v0.8b, v1.8b, v2.8b 258; CHECK-NEXT: and w9, w9, #0x1 259; CHECK-NEXT: cmeq v0.4h, v0.4h, v1.4h 260; CHECK-NEXT: bfi w8, w9, #2, #1 261; CHECK-NEXT: umov w9, v1.h[3] 262; CHECK-NEXT: mvn v0.8b, v0.8b 263; CHECK-NEXT: bfi w8, w9, #3, #29 264; CHECK-NEXT: sshll v0.4s, v0.4h, #0 265; CHECK-NEXT: and w8, w8, #0xf 266; CHECK-NEXT: strb w8, [x0] 267; CHECK-NEXT: ret 268 %t = call {<4 x i1>, <4 x i1>} @llvm.uadd.with.overflow.v4i1(<4 x i1> %a0, <4 x i1> %a1) 269 %val = extractvalue {<4 x i1>, <4 x i1>} %t, 0 270 %obit = extractvalue {<4 x i1>, <4 x i1>} %t, 1 271 %res = sext <4 x i1> %obit to <4 x i32> 272 store <4 x i1> %val, <4 x i1>* %p2 273 ret <4 x i32> %res 274} 275 276define <2 x i32> @uaddo_v2i128(<2 x i128> %a0, <2 x i128> %a1, <2 x i128>* %p2) nounwind { 277; CHECK-LABEL: uaddo_v2i128: 278; CHECK: // %bb.0: 279; CHECK-NEXT: adds x9, x2, x6 280; CHECK-NEXT: adcs x10, x3, x7 281; CHECK-NEXT: cmp x9, x2 282; CHECK-NEXT: cset w11, lo 283; CHECK-NEXT: cmp x10, x3 284; CHECK-NEXT: cset w12, lo 285; CHECK-NEXT: csel w11, w11, w12, eq 286; CHECK-NEXT: adds x12, x0, x4 287; CHECK-NEXT: adcs x13, x1, x5 288; CHECK-NEXT: cmp x12, x0 289; CHECK-NEXT: cset w14, lo 290; CHECK-NEXT: cmp x13, x1 291; CHECK-NEXT: cset w15, lo 292; CHECK-NEXT: csel w14, w14, w15, eq 293; CHECK-NEXT: ldr x8, [sp] 294; CHECK-NEXT: fmov s0, w14 295; CHECK-NEXT: mov v0.s[1], w11 296; CHECK-NEXT: shl v0.2s, v0.2s, #31 297; CHECK-NEXT: sshr v0.2s, v0.2s, #31 298; CHECK-NEXT: stp x9, x10, [x8, #16] 299; CHECK-NEXT: stp x12, x13, [x8] 300; CHECK-NEXT: ret 301 %t = call {<2 x i128>, <2 x i1>} @llvm.uadd.with.overflow.v2i128(<2 x i128> %a0, <2 x i128> %a1) 302 %val = extractvalue {<2 x i128>, <2 x i1>} %t, 0 303 %obit = extractvalue {<2 x i128>, <2 x i1>} %t, 1 304 %res = sext <2 x i1> %obit to <2 x i32> 305 store <2 x i128> %val, <2 x i128>* %p2 306 ret <2 x i32> %res 307} 308